CN117476755A - Super-junction IGBT device and manufacturing method thereof - Google Patents

Super-junction IGBT device and manufacturing method thereof Download PDF

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CN117476755A
CN117476755A CN202311281116.2A CN202311281116A CN117476755A CN 117476755 A CN117476755 A CN 117476755A CN 202311281116 A CN202311281116 A CN 202311281116A CN 117476755 A CN117476755 A CN 117476755A
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layer
well region
epitaxial
super
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肖胜安
曾大杰
高宗朋
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Shanghai Dingyangtong Semiconductor Technology Co ltd
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Shanghai Dingyangtong Semiconductor Technology Co ltd
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Abstract

The invention discloses a super-junction IGBT device, a structure positioned in an active region comprises: the planar gate structures are formed at the tops of the first conductive type columns and are of an integral structure; the second well region is formed by annealing an ion implantation region of a second conductivity type taking a planar gate structure as a self-alignment condition; the second well region is laterally diffused to the bottom region of the planar gate structure under the action of annealing treatment; the channel region is comprised of a second well region covered by a planar gate structure, and a self-aligned structure between the second well region and the planar gate structure is used to improve device uniformity. The super junction structure is formed in the first epitaxial layer, the second conductive type is composed of a second epitaxial layer filled in the super junction groove, the bottom area of the first epitaxial layer is provided with a first epitaxial sub-layer with doping concentration larger than that of the top area, and the bottom surface of the super junction groove is located in the first epitaxial sub-layer. The invention also discloses a manufacturing method of the super-junction IGBT device. The invention can improve the consistency of devices.

Description

Super-junction IGBT device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction IGBT device; the invention also relates to a manufacturing method of the super-junction IGBT device.
Background
The existing superjunction device comprises a current flow region, namely an active region, a transition region and a terminal region; a superjunction structure is formed in the current flow region, and the superjunction structure is composed of P-type columns and N-type columns which are alternately arranged, namely P-N type columns. Taking the structure of strip-shaped P-N type columns as an example, a planar gate structure is arranged above each N type column, the planar gate structure can partially cover peripheral P type columns or not, a P type well (Pwell) is arranged above each P type column, an N+ source region is arranged in the P type well, a contact hole is formed in the P type well, emitter metal is connected with the source region through the contact hole, and the contact hole of the emitter metal is connected with the P region through a P+ contact region with high concentration. In the transition region, there is a P-type ring, which covers 1 to a plurality of P-type pillars, the P-type ring can be completed by the same process as the P-type well, there is a p+ contact region with high concentration in the P-type ring, the p+ contact region in the P-type ring and the p+ contact region in the current flow region are formed in the same process, and the concentration and junction depth are the same.
In the device structure, the width of the P-type well below the planar gate structure is actually the channel length of the device, and the size of the channel length influences the on-resistance and the switching characteristic of the device. In the N-type region between P-type wells at the bottom of the planar gate structure, N-type impurities are typically implanted to reduce on-resistance and form an anti-JFET region whose width directly affects the reverse transfer capacitance (Crss) of the device, which consists of gate-drain capacitance (Cgd), which is also Miller capacitance (Miller).
In the prior art, a general Pwell is formed after or before a P-type column, a P-type ring forming area of a transition region is defined by photoetching, the width of the P-type ring is 1-50 microns, and a P-type well forming area of a current flowing region is defined; then, P-type impurities, such as B, or BF2, are implanted by an ion implantation process, thus forming a P-type well.
Thereafter forming a dielectric guard ring, comprising: and forming a dielectric film of the dielectric protection ring, namely a G-field dielectric film, photoetching and etching the G-field dielectric film to ensure that the G-field dielectric film only covers the surfaces of the transition region and the terminal region, and removing the G-field dielectric film on the surface of the active region completely, thereby forming the dielectric protection ring surrounding the active region.
And forming a planar gate structure, namely forming a gate oxide film and a polysilicon gate, defining a gate region in the active region by gate photoetching and etching, defining a gate longitudinal direction (Bus) on the transition region, and defining a gate region in the terminal region or not in the terminal region.
After the planar gate structure is formed, the region where the P-type well and the planar gate structure overlap in the active region forms a channel region, and the length of the channel region is actually influenced by the size of the P-type region formed by photoetching and etching of the P-type well, and also influenced by the position, namely the photoetching overlay accuracy, and also influenced by the size and the position of the polysilicon gate of the active region formed by photoetching and etching of the polysilicon gate. Therefore, the uniformity of the length of the channel regions formed by the prior method, namely the uniformity of the channel length, is poor, and the uniformity of the width of the anti-JFET regions among the channel regions is poor, so that the uniformity of the on-resistance and the threshold voltage of the device is affected, and the uniformity of the device Cgd and the gate-source capacitance (Cgs) is also affected, wherein the Cgd comprises the capacitance formed by covering the anti-JFET regions among the channel regions by a planar gate structure, and the Cgd comprises the capacitance formed by covering the channel regions by the planar gate structure.
The following description is now made with reference to fig. 1 for a conventional super-junction IGBT device:
as shown in fig. 1, the structure of the existing super-junction IGBT device is schematically shown; in fig. 1, only the cross-sectional structure of the active region is shown, taking an N-type super-junction IGBT device as an example, the conventional super-junction IGBT device includes:
a superjunction structure is formed in the semiconductor substrate, the superjunction structure is formed by alternately arranging a plurality of N-type columns and P-type columns 103, and a superjunction unit is formed by one N-type column and an adjacent P-type column 103.
Typically, the semiconductor substrate comprises a silicon substrate. Typically, an N-type epitaxial layer 102 is formed on the surface of the semiconductor substrate, and the N-type pillars are composed of the N-type epitaxial layer 102 between the P-type pillars 103.
The structure of the super junction IGBT device in the active region comprises:
a P-type well region (PWell) 106 formed on top of the P-type pillar 103, the P-type well region 106 further extending into the N-type pillar on both sides of the P-type pillar 103, the P-type well region 106 being defined by photolithography and formed by ion implantation.
The planar gate structures are formed at the top of each N-type column and are of an integral structure; the planar gate structure is formed by overlapping a gate dielectric layer 104 and a gate conductive material layer 105.
Typically, the gate dielectric layer 104 includes a gate oxide layer. The gate conductive material layer 105 comprises a polysilicon gate.
The planar gate structure also needs to be patterned by adopting a photoetching definition and etching process.
N+ doped emitter regions 107 are self-aligned to the surfaces of the P-type well region 106 formed on both sides of the planar gate structure.
The P-type well region 106 and the planar gate structure need to overlap and the P-type well region 106 located at the bottom of the planar gate structure forms a channel region, and in fig. 1, the length of the channel region, that is, the channel length, adopts the Lc surface. The planar gate structure being of unitary construction means that the planar gate structure does not split in the middle, the top of the same N-type pillar will form two of the channel regions, but the two channel regions share one of the planar gate structure, and the layer of gate conductive material 105 will extend from the top of one of the channel regions to the top of the other channel region, such that the top of the region between the channel regions is also covered by the planar gate structure.
The area between the P-well regions 106 at the bottom of the planar gate structure is the area where JFET effect occurs, the width of which is Wj, and N-type ion implantation is typically required to form the JFET resistant region.
The front structure of the super-junction IGBT device further comprises:
an interlayer film 108, a contact hole 109 penetrating the interlayer film 108; a body contact region 110 consisting of a P-type heavily doped region is also formed at the bottom of the contact hole 109 at the top of the emitter region 108, so that the body region 104 is connected to the contact hole 109 at the top through the body contact region 110 and the emitter region 108 together.
The emitter metal and the gate metal are patterned from the front side metal layer 111.
The back structure of the super-junction IGBT device comprises:
and the collector region 101 is formed by P-type back surface ion implantation after the semiconductor substrate is thinned.
A collector composed of a back metal layer 112 is formed on the back surface of the collector region 101.
As shown in fig. 2, a flow chart of a method for manufacturing a conventional super-junction IGBT device is shown, which is used to manufacture the conventional super-junction IGBT device shown in fig. 1; the steps are represented in fig. 2 using a mask level. The manufacturing method of the existing super-junction IGBT device comprises the following steps:
proceeding to step S101 to form the Zero Mark (Zero Mark) requires a photolithography (photo) plus etch (etch) process, step S201 is also denoted by Zero photo & etch in fig. 2.
Step S102 is performed to form the anti-JFET region, which needs to be defined by a photolithography process, so in fig. 2, step S101 is denoted by JFET photo & IMP.
Step S103 is performed to form a super junction structure, i.e., to form P-type pillars 103 shown in fig. 1, where the P-type pillars 103 are formed by a trench (trench) etching and filling process, and the N-type epitaxial layer 102 between the P-type pillars 103 constitutes an N-type pillar. The formation of the superjunction structure requires the use of a mask defining trenches, so step S103 in fig. 2 is denoted by Trench photo & etch.
Step S104 is performed to form P-type well region 106. The P-well 106 is first defined by photolithography and then ion implantation, so in fig. 1, step S104 is denoted by Pwell photo & IMP.
Step S105 is performed to form a dielectric guard ring, where growth of a material layer (Gfield) of the dielectric guard ring is required, and then a photolithography and etching process is performed to remove the material layer of the dielectric guard ring in the active region, and the material layer of the dielectric guard ring remaining in the dielectric guard ring is formed into the dielectric guard ring. Therefore, in fig. 2, step S105 is represented by the Gfield photo & tech.
Step S106 is carried out to form a planar gate structure, wherein the planar gate structure is required to be formed into a superposition structure of a gate oxide layer and a polysilicon gate, and then a photoetching and etching process is carried out to pattern the planar gate structure. Therefore, in fig. 2, step S106 is represented by poly photo & tech.
Step S107 is performed to form the emitter 107. In the active region the emitter region 107 and the planar gate structure are self-aligned. The emitter region 107 is an n+ region (Nplus), and a photomask is used to define the formation region of the emitter region 107 in the formation process step of the emitter region 107, so in fig. 1, step S107 is also denoted by Nplus photo & IMP.
Proceeding to step S108, comprising: an interlayer film 108 is formed, and a contact hole (Cont) 109 is formed through the interlayer film 108. In the process of forming the contact hole 109, a photolithography process is used to define a formation region of the contact hole 109, then etching is performed to form an opening of the contact hole 109, and then metal is filled in the opening of the contact hole 109 to form the contact hole. In the step of forming the contact hole 109, a photomask is used to define the formation area of the contact hole 109, so in fig. 1, step S108 is also denoted by contphoto & etch.
The method further comprises the step of performing P-type heavily doped ion implantation to form the body contact region 211 after opening the contact hole 109 and before filling the metal
Step S109 is performed, which includes: a front side metal layer (metal) 111 is formed and the front side metal layer 111 is patterned to form an emitter metal and a gate metal. In the step of forming the front Metal layer 111, a photomask is used to define the pattern area of the front Metal layer 111, so in fig. 1, step S109 is also denoted by Metal photo & etch.
After the front side process is completed, a back side process is also required:
and thinning the back, and performing back P-type ion implantation to form a collector region to form a back metal layer. As can be seen from fig. 1 and fig. 2, the P-type well region 106 needs to be implemented by photolithography definition and ion implantation, and in the photolithography process, the thickness, the exposure intensity, the developing process and the ion implantation process of the photoresist all have corresponding deviations, so that the dimension of the P-type well region 106 changes, that is, the dimension of the photolithography and the ion implantation processes changes; meanwhile, the photolithography overlay accuracy may also change the pattern position of the P-type well region 106.
Also, the planar gate structure needs to be realized by adopting photoetching definition and etching, and the planar gate structure can generate dimensional changes due to photoetching and etching process parameters and pattern position changes due to photoetching alignment precision in the same line.
On the same semiconductor substrate, the channel length Lc is changed by the dimensional change of the P-type well region 106 due to the photolithography and implantation process, the pattern position change due to the photolithography and etching process, and the pattern position change of the planar gate structure due to the photolithography and etching process. The channel length Lc has a great influence on the on-resistance, the threshold voltage, and the input capacitance, cgs, of the device, which affects the uniformity of the device performance, such as the uniformity of the channel length Lc, the on-resistance, the threshold voltage, and Cgs, is deteriorated.
Because JFET effects are easily generated in the N-type region between the channel regions, an anti-JFET implant is performed to form an anti-JFET region having an N-type impurity concentration higher than that of the N-type epitaxial layer 102, for example, by 1 order of magnitude or more, and a width Wj of the anti-JFET region directly affects the Cgd of the device. The width Wj also varies and therefore affects the uniformity of Cgd of the device.
The adverse effects of the prior art methods on device uniformity are described below in conjunction with specific parameters:
as can be seen from fig. 2, the width and position of the P-type well region 106 are determined by the photolithography process of the P-type well region 106, because the critical dimensions (Critical Dimension, CD) after photolithography vary with the thickness of the photoresist, the energy of the photolithography, the process of development, and the position of the pattern will always vary (for example, within +/-0.2 micrometers, depending on the size of the photolithography pattern, the process selection, etc.), and the overlay accuracy will also vary within a certain range (for example, 60nm-150 nm); similarly, the width of the polysilicon gate is also related to the photoetching process of the polysilicon gate, the etching process is changed within a certain range, and the photoetching alignment precision also fluctuates within a certain range. If a photoresist thickness of approximately 1 micron is used, using a 248nm lithography machine, the single layer width schedule may fluctuate + -0.1 micron, and if the overlay schedule fluctuates + -0.06 microns, the channel length Lc may fluctuate + -0.32 microns, taking into account the difference between the two layers of lithography, which has a significant impact on device uniformity for a 9 micron step (pitch) device, where the poly gate width is set to 7.5 microns (which has been considered in a very wide direction), and the single channel length Lc is designed to be 2-3 microns. If one should scale down the step of the superjunction to a level of 5 microns, for example, the step is set to be less than 3.5 microns, then the contact width is subtracted by 0.5 microns, the contact to poly edge spacing is 0.5 microns, then the width of the entire poly gate is only 3.5 microns, the single sided channel length Lc must be less than 1.7 microns, and this + -0.32 micron variation will result in very poor uniformity.
Even though this range of variation can be reduced by optimization of the lithography and etching processes, in particular the management of the process conditions, on the one hand these solutions require higher manufacturing costs, for example because of the photolithography with increased critical dimensions and overlay accuracy of the lithography process, resulting in an increased photolithography rework rate and increased manufacturing costs. While this variation or consistency must exist, the problem is increasingly accentuated as the superjunction step decreases.
Disclosure of Invention
The technical problem to be solved by the invention is to provide the super-junction IGBT device, which can improve the consistency of the device. Therefore, the invention also provides a manufacturing method of the super-junction IGBT device.
In order to solve the above technical problems, the super-junction IGBT device provided by the invention includes:
and the super junction unit consists of one first conductive type column and one adjacent second conductive type column.
The second conductive type pillars are composed of a second epitaxial layer doped with a second conductive type filled in the super junction trench, and the first conductive type pillars are composed of the first epitaxial layer between the second conductive type pillars.
The structure of the super junction IGBT device in the active region comprises:
a planar gate structure formed on top of each of the first conductivity type pillars, the planar gate structure being of unitary construction; the planar gate structure is formed by laminating a gate dielectric layer and a gate conductive material layer.
The second well region is formed by annealing an ion implantation region of a second conductivity type taking the planar gate structure as a self-alignment condition; and the second well region is laterally diffused to the bottom region of the planar gate structure under the action of annealing treatment.
The channel region is formed by covering the second well region by the planar gate structure, and a self-aligned structure between the second well region and the planar gate structure is used for improving the uniformity of the device.
The depth of each super-junction groove has deviation caused by the etching process of the super-junction groove, the first epitaxial layer comprises a first epitaxial sub-layer positioned in the bottom area of the first epitaxial layer, the bottom surface of each super-junction groove is positioned in the first epitaxial sub-layer, and the doping concentration of the first epitaxial sub-layer is larger than that in the area of the first epitaxial layer positioned at the top of the first epitaxial sub-layer, so that the influence of the depth deviation of the super-junction groove on pressure resistance is reduced, and the pressure resistance uniformity is improved.
And a collector region composed of a second conductivity type back ion implantation region formed in a back region of the first epitaxial sublayer.
The first epitaxial sublayer between the bottom surface of the superjunction structure to the top surface of the collector region acts as both a field stop layer and a barrier layer for minority carriers injected from the collector region.
A further improvement is that the superjunction trench has sloped sides and a top opening that is larger than a bottom opening.
The first epitaxial layer has a doping concentration profile in a region at the top of the first epitaxial sub-layer that becomes larger from bottom to top to compensate for the effect of the laterally sloped superjunction trench on the charge balance of the superjunction structure.
The method is characterized in that the region on the top of the first epitaxial sub-layer of the first epitaxial layer at least comprises a second epitaxial sub-layer and a third epitaxial sub-layer, the second epitaxial sub-layer is stacked on the top surface of the first epitaxial sub-layer, the third epitaxial sub-layer is stacked on the top surface of the second epitaxial sub-layer, and the doping concentration of the third epitaxial sub-layer is larger than that of the second epitaxial sub-layer.
A further improvement is that the resistivity of the first epitaxial sublayer is at least 10% lower than the resistivity of the second epitaxial sublayer.
A further improvement is that the structure of the super junction IGBT device located in the active region further includes:
and the first well region consists of ion implantation regions of the second conductivity type formed on the tops of the second conductivity type columns, and the forming region of the first well region is defined by photoetching.
In the lateral direction, a space is formed between the first well region and the side surface of the planar gate structure, the first well region is aligned with the side surface of the planar gate structure, or the first well region extends to the bottom of the planar gate structure.
The body region is formed by longitudinally superposing the first well region and the second well region, the junction depth of the first well region is larger than that of the second well region, and the doping concentration of the first well is smaller than that of the second well region, so that leakage current of the device is reduced.
The dielectric protection ring covers a transition area and a terminal area and opens the active area, the area surrounded by the dielectric protection ring is the active area, the transition area surrounds the periphery of the active area, and the terminal area surrounds the periphery of the transition area.
And an anti-JFET region is formed in the active region, and the anti-JFET region consists of an ion implantation region of a first conductivity type which is comprehensively formed on the surface of the super junction structure of the active region by taking the dielectric protection ring as a self-alignment condition.
The anti-JFET region is used for improving the first-conductivity-type doping concentration of the first-conductivity-type doping region and reducing the JFET effect.
The anti-JFET region is used for compensating second-conductivity-type doped impurities of the first well region of the surface region of the active region at the same time in the second-conductivity-type doped region so as to reduce the influence of the first well region on the second-conductivity-type doped of the surface region of the active region, and the second-conductivity-type doped of the channel region is determined by the second well region.
A further improvement is that an emitter region of a first conductivity type heavily doped is formed on the body region surface, the emitter region and the planar gate structure being self-aligned.
A further improvement is that the first well region covers at least the center position of the second conductive type column and the width of the first well region on both sides of the center position of the second conductive type column is 0.2 μm or more in the lateral direction; or the first well region covers the second conductive type column, and the width of the first well region is 1-2 microns or more than 2 microns.
In the longitudinal direction, the depth of the first well region is 1-2 microns; alternatively, the depth of the first well region is 2 microns or more.
When the depth of the first well region is 1-2 microns, the dielectric protection ring is formed by laminating a thermal oxidation layer formed by a thermal oxidation process or a deposition dielectric layer formed by a thermal oxidation process and a deposition process, the thermal oxidation layer of the dielectric protection ring consumes the surface of the first epitaxial layer formed with the super junction structure, the surface area of the first well region is removed in the removing process of the dielectric protection ring of the active region, and the doping concentration of the removed surface area of the first well region is higher than that of the bottom reserved area, so that the uniformity of devices is improved.
When the depth of the first well region is more than 2 microns, the dielectric protection ring is formed by superposing a thermal oxidation layer formed by a thermal oxidation process or a deposition dielectric layer formed by a deposition process, and the deposition dielectric layer of the dielectric protection ring reduces the thermal process of the device so as to reduce the specific on-resistance of the device.
A further improvement is that a second conductivity type ring is formed in the transition region, and the first well region and the second conductivity type ring have the same process structure.
The super-junction IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the super-junction IGBT device is a P-type device, the first conduction type is P-type, and the second conduction type is N-type.
In order to solve the technical problems, the manufacturing method of the super-junction IGBT device provided by the invention comprises the following steps:
forming a first epitaxial layer doped with a first conductive type on a semiconductor substrate, forming a plurality of superjunction grooves in selected areas of the first epitaxial layer, filling a second epitaxial layer doped with a second conductive type in the superjunction grooves, taking the second epitaxial layer filled in the superjunction grooves as a component part of the second conductive type columns, and forming first conductive type columns by the first epitaxial layer between the second conductive type columns.
A super junction structure is formed by alternately arranging a plurality of first conductive type columns and second conductive type columns, and a super junction unit is composed of one first conductive type column and one adjacent second conductive type column.
The depth of each super-junction groove has deviation caused by the etching process of the super-junction groove, the first epitaxial layer comprises a first epitaxial sub-layer positioned in the bottom area of the first epitaxial layer, the bottom surface of each super-junction groove is positioned in the first epitaxial sub-layer, and the doping concentration of the first epitaxial sub-layer is larger than that in the area of the first epitaxial layer positioned at the top of the first epitaxial sub-layer, so that the influence of the depth deviation of the super-junction groove on pressure resistance is reduced, and the pressure resistance uniformity is improved.
And step two, defining an active region on the semiconductor substrate.
Forming a planar gate structure in the active region, wherein each planar gate structure is formed on the top of each first conductive type column, and the planar gate structure is of an integral structure; the planar gate structure is formed by laminating a gate dielectric layer and a gate conductive material layer.
And fourthly, performing ion implantation of a second conduction type to form a second well region by taking the planar gate structure as a self-alignment condition, and performing annealing treatment on the second well region, wherein the second well region is laterally diffused to the bottom region of the planar gate structure under the action of the annealing treatment.
The channel region is formed by covering the second well region by the planar gate structure, and a self-aligned structure between the second well region and the planar gate structure is used for improving the uniformity of the device.
And fifthly, carrying out back thinning, wherein the back thinning completely removes the semiconductor substrate and keeps part of the thickness of the first epitaxial sub-layer.
Step six, performing second conductivity type back ion implantation to form a collector region in the back region of the reserved first epitaxial sublayer; the first epitaxial sublayer between the bottom surface of the superjunction structure to the top surface of the collector region acts as both a field stop layer and a barrier layer for minority carriers injected from the collector region.
A further improvement is in step one, wherein the superjunction trench has sloped sides and a top opening that is larger than a bottom opening.
The first epitaxial layer has a doping concentration profile in a region at the top of the first epitaxial sub-layer that becomes larger from bottom to top to compensate for the effect of the laterally sloped superjunction trench on the charge balance of the superjunction structure.
The method is characterized in that the region on the top of the first epitaxial sub-layer of the first epitaxial layer at least comprises a second epitaxial sub-layer and a third epitaxial sub-layer, the second epitaxial sub-layer is stacked on the top surface of the first epitaxial sub-layer, the third epitaxial sub-layer is stacked on the top surface of the second epitaxial sub-layer, and the doping concentration of the third epitaxial sub-layer is larger than that of the second epitaxial sub-layer.
A further improvement is that the resistivity of the first epitaxial sublayer is at least 10% lower than the resistivity of the second epitaxial sublayer.
In a further improvement, the first step further comprises the following steps of forming the first well region:
and photoetching to define a forming area of the first well region, wherein the first well region is positioned at the top of the second conductive type column in the active region.
And performing ion implantation of a second conductivity type to form the first well region.
Annealing and propelling the first well region; in the transverse direction, a space is reserved between the first well region and the side face of the planar gate structure after annealing is advanced, the first well region is aligned with the side face of the planar gate structure, or the first well region extends to the bottom of the planar gate structure.
The body region is formed by longitudinally superposing the first well region and the second well region, the junction depth of the first well region is larger than that of the second well region, and the doping concentration of the first well is smaller than that of the second well region, so that leakage current of the device is reduced.
The further improvement is that the step two comprises the following sub-steps:
and forming a material layer of a dielectric protection ring on the surface of the first epitaxial layer on which the super junction structure is formed.
And photoetching to define a forming area of the active area.
And etching the material layer of the medium protection ring to form the medium protection ring, wherein the medium protection ring covers the transition area and the terminal area and opens the active area, the area surrounded by the medium protection ring is the active area, the transition area surrounds the periphery of the active area, and the terminal area surrounds the periphery of the transition area.
A further improvement is that after the completion of step two and before the performance of step three, the method comprises the steps of forming the anti-JFET region as follows:
and performing first conduction type ion implantation on the surface of the active region by taking the dielectric protection ring as a self-alignment condition to comprehensively form the anti-JFET region.
The anti-JFET region is used for improving the first-conductivity-type doping concentration of the first-conductivity-type doping region and reducing the JFET effect.
The anti-JFET region is used for compensating second-conductivity-type doped impurities of the first well region of the surface region of the active region at the same time in the second-conductivity-type doped region so as to reduce the influence of the first well region on the second-conductivity-type doped of the surface region of the active region, and the second-conductivity-type doped of the channel region is determined by the second well region.
The further improvement is that the step four further comprises: ion implantation of first conductive type heavy doping taking the plane gate structure as a self-alignment condition is conducted in the active region to form an emission region.
A further improvement is that the first well region covers at least the center position of the second conductive type column and the width of the first well region on both sides of the center position of the second conductive type column is 0.2 μm or more in the lateral direction; or the first well region covers the second conductive type column, and the width of the first well region is 1-2 microns or more than 2 microns.
In the longitudinal direction, the depth of the first well region is 1-2 microns; alternatively, the depth of the first well region is 2 microns or more.
When the depth of the first well region is 1-2 microns, the dielectric protection ring is formed by laminating a thermal oxidation layer formed by a thermal oxidation process or a deposition dielectric layer formed by a thermal oxidation process and a deposition process, the thermal oxidation layer of the dielectric protection ring consumes the surface of the first epitaxial layer formed with the super junction structure, the surface area of the first well region is removed in the process of removing the dielectric protection ring of the active region, and the doping concentration of the removed surface area of the first well region is higher than that of a bottom reserved area, so that the uniformity of devices is improved;
When the depth of the first well region is more than 2 microns, the dielectric protection ring is formed by superposing a thermal oxidation layer formed by a thermal oxidation process or a deposition dielectric layer formed by a deposition process, and the deposition dielectric layer of the dielectric protection ring reduces the thermal process of the device so as to reduce the specific on-resistance of the device.
A further improvement is that a second conductivity type ring is formed in the transition region, the first well region and the second conductivity type ring being formed simultaneously using the same process.
A further improvement is that, prior to step three, after the formation of the anti-JFET region, the anti-JFET region inverts the surface of the second conductivity type doped region to be doped of the first conductivity type.
In a further improvement, in the fifth step, after the back surface is thinned, the thickness of the first epitaxial sub-layer is 3 micrometers to 8 micrometers.
In the prior art, the channel region is formed by an ion implantation region defined by a photomask, and the channel region is formed by a second well region which is self-aligned with a planar gate structure.
In addition, if the second well region which is self-aligned with the planar gate structure is independently adopted as the whole body region, the depth of the body region formed by independently adopting the second well region is shallower, and the electric leakage of the device is larger because the forming process of the second well region is limited by the planar gate structure; therefore, the invention can also form a body region together by adopting the first well region formed by the photomask before the basic gate of the second well region is combined with the planar gate structure, thus improving the uniformity of the device by utilizing the second well region and reducing the leakage current of the device by utilizing the deeper junction depth of the first well region and the graded structure.
In addition, after the first well region is introduced into the body region, the first well region extends downwards from the surface of the active region, so that the first well region positioned on the surface of the active region can be used as a component of the channel region, the length of the channel region is affected, and finally the uniformity of the device is affected.
The region in the anti-JFET region, which actually generates the reduced JFET effect, is a region between the channel regions and covered by the planar gate structure, the width of the region is only influenced by the width of the planar gate structure, the width of the planar gate structure is influenced by photoetching and etching processes of the planar gate structure, and the photoetching registration accuracy of the planar gate structure does not influence the width of the anti-JFET region between the channel regions and covered by the planar gate structure, so that the uniformity of the gate-drain capacitance (Cgd) of the device is also greatly improved.
In addition, when the junction depth of the first well region is smaller, the surface region with higher doping concentration of the first well region can be removed through the thermal oxidation layer such as the thermal oxidation layer for forming the medium protection ring, so that adverse effects of the surface region with higher doping concentration of the first well region on the channel region are reduced, and the consistency of devices is further improved.
When the junction depth of the first well region is deeper, the deeper junction depth is utilized to slow down the doping concentration of the whole first well region, so that the doping concentration of the surface region of the first well region is also reduced, the adverse effect of the surface region of the first well region on the channel region can be reduced, and the consistency of devices is further improved.
The invention also sets the first epitaxial layer in a layered manner, sets the doping concentration of the first epitaxial sub-layer at the bottom to be higher, and the bottom surface of the super-junction groove is required to enter the first epitaxial sub-layer, so that the influence of the depth deviation of the super-junction groove on the withstand voltage can be reduced and the withstand voltage uniformity can be improved by utilizing the characteristic that the doping concentration of the first epitaxial sub-layer is higher than that of the first epitaxial layer at the top, because: when the concentration of the first epitaxial sub-layer is increased, the pressure resistance below the top surface of the first epitaxial sub-layer is mainly determined by the first epitaxial sub-layer, so that the effective thickness of the superjunction structure is actually the thickness of the part above the top surface of the first epitaxial sub-layer, even if the depths of the superjunction grooves in different areas deviate, the longitudinal position difference of the bottom surface of the superjunction grooves does not have great influence on the pressure resistance because the bottom surface of the superjunction grooves is ensured to be in the first epitaxial sub-layer, and the invention can reduce the influence of the depth deviation of the superjunction grooves on the pressure resistance and improve the pressure resistance uniformity, namely the consistency of BVDss of devices.
Meanwhile, the collector region is formed on the back surface of the first epitaxial sub-layer, so that the first epitaxial sub-layer located between the bottom surface of the super junction structure and the top surface of the collector region can serve as a field stop layer, and therefore electric field distribution of the drift region can be improved, and withstand voltage of the device is improved.
Meanwhile, the first epitaxial sub-layer can be used as a blocking layer of minority carriers injected from the collector region because of higher concentration, an N-type device is taken as an example, minority carriers are taken as holes, holes are injected into the drift region by the collector region when the device is turned on, and the holes injected when the device is turned off can be quickly compounded in the first epitaxial sub-layer because the first epitaxial sub-layer is high in concentration, so that blocking effect is realized, quick turn-off can be realized, and a super-junction IGBT (insulated gate bipolar transistor) capable of being turned off quickly can be realized.
The doping concentration distribution of the first epitaxial layer in the top region of the first epitaxial sub-layer can be set to be larger from bottom to top according to the requirement of the super-junction groove with inclined compensation side surface on the charge balance of the super-junction structure, for example, the first epitaxial layer in the top region of the first epitaxial sub-layer can be set to be an overlapped layer of the second epitaxial sub-layer and the third epitaxial sub-layer with smaller doping concentration, so that the charge balance at each longitudinal position of the super-junction structure can be improved, and finally the device voltage resistance can be realized.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
fig. 1 is a schematic structural diagram of a conventional superjunction IGBT device;
Fig. 2 is a flow chart of a method of manufacturing a prior art superjunction IGBT device;
fig. 3 is a schematic structural diagram of a superjunction IGBT device according to an embodiment of the present invention;
fig. 4 is a flowchart of a method of manufacturing a superjunction IGBT device according to an embodiment of the present invention;
fig. 5A to 5F are schematic views of device structures in steps of a method for manufacturing a superjunction IGBT device according to an embodiment of the present invention.
Detailed Description
Fig. 3 is a schematic structural diagram of a superjunction IGBT device according to an embodiment of the present invention; the super-junction IGBT device of the embodiment of the invention comprises:
a first epitaxial layer 202 doped with a first conductivity type, and a superjunction structure formed by alternately arranging a plurality of first and second conductivity type pillars 203 in the first epitaxial layer 202, wherein a superjunction unit is composed of one of the first and adjacent second conductivity type pillars 203.
The second conductivity type pillars 203 are composed of a second epitaxial layer doped with a second conductivity type filled in the super junction trench, and the first conductivity type pillars are composed of the first epitaxial layer 202 between the second conductivity type pillars 203.
The depth of each super-junction trench has a deviation caused by the etching process of the super-junction trench, the first epitaxial layer 202 includes a first epitaxial sub-layer 2021 located at the bottom region of the first epitaxial layer 202, the bottom surface of each super-junction trench is located at the first epitaxial sub-layer 2021, and the doping concentration of the first epitaxial sub-layer 2021 is greater than that in the region of the first epitaxial layer 202 located at the top of the first epitaxial sub-layer 2021, so as to reduce the influence of the depth deviation of the super-junction trench on the voltage resistance and improve the voltage resistance uniformity.
In an embodiment of the present invention, the first epitaxial layer 202 is formed on the surface of the semiconductor substrate 201 (see fig. 5A), and the semiconductor substrate 201 comprises a silicon substrate
In the back side thinning process, the semiconductor substrate 201 is completely removed, and the first epitaxial sub-layer 2021 needs to remain with a partial thickness, and the remaining first epitaxial sub-layer 2021 is shown in fig. 1. In some embodiments, the first epitaxial sublayer 2021 is left to have a thickness of 3 micrometers to 8 micrometers.
In the embodiment of the invention, the super junction groove is provided with the inclined side surface, and the top opening is larger than the bottom opening, so that the etching and filling of the super junction groove are facilitated.
The region of the first epitaxial layer 202 at the top of the first epitaxial sub-layer 2021 has a doping concentration profile that becomes larger from bottom to top to compensate for the effect of the laterally inclined superjunction trench on the charge balance of the superjunction structure. In some preferred embodiments, the region on top of the first epitaxial sub-layer 2021 of the first epitaxial layer 202 includes at least a second epitaxial sub-layer 2022 and a third epitaxial sub-layer 2023, the second epitaxial sub-layer 2022 is stacked on the top surface of the first epitaxial sub-layer 2021, the third epitaxial sub-layer 2023 is stacked on the top surface of the second epitaxial sub-layer 2022, and the doping concentration of the third epitaxial sub-layer 2023 is greater than the doping concentration of the second epitaxial sub-layer 2022. As depicted in fig. 3, the first epitaxial layer 202 is formed by the superposition of the first epitaxial sub-layer 2021, the second epitaxial sub-layer 2022 and the third epitaxial sub-layer 2023.
Only the structure of the superjunction IGBT device in the active region is shown in fig. 3, the structure of the superjunction IGBT device in the active region including:
the planar gate structures are formed at the tops of the first conductive type columns, the planar gate structures are of integral structures, the planar gate structures of the integral structures are relative to the split gate structures, two sides of the planar gate structures respectively cover corresponding channel regions, and the middle of the planar gate structures are connected together to form the integral structures; the planar gate structure is formed by overlapping a gate dielectric layer 206 and a gate conductive material layer 207.
In some preferred embodiments, the gate dielectric layer 206 comprises a gate oxide layer.
The gate conductive material layer 207 includes a polysilicon gate.
A second well region 2042 formed by annealing an ion implantation region of a second conductivity type having the planar gate structure as a self-aligned condition; the second well region 2042 is laterally diffused into the bottom region of the planar gate structure by the annealing process. The second well region 2042 also diffuses longitudinally downward at the same time as the annealing process.
The channel region is formed by the second well region 2042 being covered by the planar gate structure, and the self-aligned structure between the second well region 2042 and the planar gate structure is used to improve device uniformity. In fig. 3, the length of the channel region is denoted by Lc, and the channel region is also the second well region 2042 between two straight lines corresponding to the channel length Lc in fig. 3. A conductive channel is formed after inversion of the surface of the channel region.
Because the second well region 2042 is limited by self-alignment with the planar gate structure, the junction depth of the second well region 2042 is shallow, and if the second well region 2042 is solely used as the body region 204, larger leakage current will occur, which is only applicable to occasions with low requirements for leakage current.
Preferably, in order to reduce leakage, a structure of the super-junction IGBT device in the embodiment of the present invention located in the active region further includes:
the first well region 2041 is composed of an ion implantation region of the second conductivity type formed on top of each of the second conductivity type pillars 203, and a formation region of the first well region 2041 is defined by photolithography.
In the lateral direction, there is a space between the first well region 2041 and the side surface of the planar gate structure, an alignment between the first well region 2041 and the side surface of the planar gate structure, or the first well region 2041 may extend to the bottom of the planar gate structure. In fig. 3, the first well region 2041 is shown with an overlap between the planar gate structure.
The body 204 is formed by vertically stacking the first well 2041 and the second well 2042, where the junction depth of the first well 2041 is greater than the junction depth of the second well 2042 and the doping concentration of the first well is less than the doping concentration of the second well 2042, so as to reduce the leakage current of the device. In fig. 3, the first well region 2041 is also denoted by P1 and the second well region 2042 is also denoted by P2.
In the embodiment of the present invention, the first well region 2041 is formed by photolithography definition and ion implantation and annealing and propulsion, and after the annealing and propulsion are completed, at least the following is ensured: in the lateral direction, the first well region 2041 covers at least the center position of the second conductivity type pillar 203 and the width of the first well region 2041 on both sides of the center position of the second conductivity type pillar 203 is 0.2 μm or more; alternatively, the first well region 2041 covers the second conductivity type pillars 203 with a width of 1 micron to 2 microns or greater than 2 microns.
In the longitudinal direction, the depth of the first well region 2041 is 1 to 2 micrometers; alternatively, the depth of the first well region 2041 is 2 microns or more.
A dielectric guard ring (not shown) is formed on the surface of the first epitaxial layer 202 where the superjunction structure is formed, the dielectric guard ring covers a transition region and a terminal region and opens the active region, the region surrounded by the dielectric guard ring is the active region, the transition region surrounds the periphery of the active region, and the terminal region surrounds the periphery of the transition region.
The active region includes the super junction structure of the area surrounded by the dielectric guard ring, since the first well region 2041 may extend downward from the surface of the active region, when the doping concentration of the first well region 2041 on the surface of the active region is higher, the second well region 2042 on the surface of the active region may be adversely affected, and finally, uniformity of the size and doping concentration of the channel region may be affected. To this end, in some preferred embodiments, it can further comprise:
When the depth of the first well region 2041 is 1-2 micrometers, the dielectric guard ring is formed by laminating a thermal oxide layer formed by a thermal oxidation process or a deposition dielectric layer formed by a thermal oxide layer formed by a thermal oxidation process and a deposition process, the thermal oxide layer of the dielectric guard ring consumes the surface of the first epitaxial layer 202 formed with the superjunction structure, the surface area of the first well region 2041 is removed in the process of removing the dielectric guard ring of the active region, and the doping concentration of the removed surface area of the first well region 2041 is higher than that of the bottom reserved area, so as to improve the uniformity of devices.
When the depth of the first well region 2041 is more than 2 micrometers, the dielectric guard ring is formed by stacking a thermal oxide layer formed by a thermal oxidation process, a deposition dielectric layer formed by a deposition process or a deposition dielectric layer formed by a deposition process, and the deposition dielectric layer of the dielectric guard ring reduces the thermal process of the device so as to reduce the specific on-resistance of the device.
An anti-JFET region 205 is also formed in the active region, and the anti-JFET region 205 is composed of an ion implantation region of the first conductivity type formed on the surface of the superjunction structure of the active region in a self-aligned condition with the dielectric guard ring.
The anti-JFET region 205 is used to increase the first conductivity type doping concentration of the first conductivity type doped region to reduce the JFET effect.
The anti-JFET region 205 is used to compensate for the second conductivity type dopant impurities of the first well region 2041 in the surface region of the active region at the same time in the second conductivity type dopant region to reduce the effect of the first well region 2041 on the second conductivity type dopant in the surface region of the active region, such that the second conductivity type dopant of the channel region is determined by the second well region 2042.
The super junction structure comprises the first conductive type column and the second conductive type column 203, so that the surface of the active region is distributed with a first conductive type doping region and a second conductive type doping region; after the first well region 2041 is formed on the surface of the active region, a second conductivity type doped region on the surface of the active region is added. The anti-JFET region 205 can invert the second conductivity type doped region to the first conductivity type entirely before the second well region 2042 is formed, and obviously, can eliminate the adverse effect of the surface area of the first well region 2041 on the channel region, thereby improving the uniformity of the device.
A heavily doped emitter region 208 of the first conductivity type is formed on the surface of the body region 204, the emitter region 208 and the planar gate structure being self-aligned.
A second conductivity type ring is formed in the transition region, and the process structures of the first well region 2041 and the second conductivity type ring are the same.
As shown in fig. 3, the front structure of the super junction IGBT device further includes:
an interlayer film 209, a contact hole 210 passing through the interlayer film 209; a body contact region 211 consisting of a heavily doped region of the second conductivity type is also formed at the bottom of the contact hole 210 at the top of the emitter region 208, so that the body region 204 is connected to the contact hole 210 at the top through the body contact region 211 and the emitter region 208 together.
Emitter metal and gate metal are patterned from front side metal layer 212.
The back structure of the super-junction IGBT device comprises:
the collector region 213 is composed of a second conductivity type back ion implantation region formed in the back region of the first epitaxial sublayer 2021. That is, after the semiconductor substrate 201 is completely removed by the back-side thinning process and a portion of the thickness of the first epitaxial sublayer 2021 is removed, the collector region 213 is formed by second conductivity type back-side ion implantation.
The first epitaxial sub-layer 2021 between the bottom surface of the superjunction structure to the top surface of the collector region 213 serves as both a field stop layer and a barrier to minority carriers injected from the collector region 213.
A back metal layer 214 is formed on the back surface of the collector region 213, and a collector is formed of the back metal layer 214.
In the embodiment of the invention, the super-junction IGBT device is an N-type device, the first conduction type is N-type, and the second conduction type is P-type. In other embodiments can also be: the super-junction IGBT device is a P-type device, the first conduction type is P-type, and the second conduction type is N-type.
In general, the doping concentrations of the first epitaxial sublayer 2021, the second epitaxial sublayer 2022, and the third epitaxial sublayer 2023 can also be expressed in terms of resistivity, with higher resistivity having lower doping concentrations and vice versa. In some embodiments, the first epitaxial sublayer 2021 is a high concentration layer, corresponding to a resistivity of, for example, 1 to 1.5ohm. The second epitaxial sub-layer 2022 is a low concentration layer, the corresponding resistivity is, for example, 2.5 ohm.cm-3 ohm.cm, the third epitaxial sub-layer 2023 has a resistivity lower than that of the second epitaxial sub-layer 2022, for example, 2.4ohm.cm, and the resistivity and thickness of the second epitaxial sub-layer 2022 and the third epitaxial sub-layer 2023 are mainly set according to the inclination angle of the second conductivity type pillars 203 in the superjunction trench, so as to obtain better charge balance.
In some embodiments, the process conditions for the backside ion implantation of the collector region 213 are: b60-100 Kev,1-3E13/cm 2 I.e. the implantation impurity is B, the implantation energy is 60keV-100keV, the implantation dosage is 1-3E13/cm 2 . The collector region 213 is also activated by backside laser annealing.
The arrangement of the first epitaxial sub-layer 2021, the second epitaxial sub-layer 2022 and the third epitaxial sub-layer 2023 stacked to form the first epitaxial layer 202 has the following advantages:
1. the concentration of the first epitaxial sub-layer 2021 is increased, and at the same time, the P-type pillars, that is, the second conductive type pillars 203, are ensured to be contacted with the first epitaxial sub-layer 2021, and the effect of the depth change of the P-type pillars on BVdss can be reduced due to the high concentration of the first epitaxial sub-layer 2021, so that the uniformity of the BVdss is improved.
2. The high concentration of the first epitaxial sublayer 2021 acts simultaneously as a field stop layer; in addition, the high concentration of the first epitaxial sub-layer 2021 is easy to make a SJ IGBT that turns off rapidly, because the high concentration of the first epitaxial sub-layer 2021 has a blocking effect on holes injected from the back surface P.
In the embodiment of the invention, the channel region is formed by adopting a second well region 2042 which is self-aligned with the planar gate structure, and the second well region 2042 is not required to be defined by adopting the photomask, so that the influence of a photoetching process on the pattern width and the photoetching alignment on the pattern position can be eliminated, namely the length of the channel region formed by the second well region 2042 is not influenced by the photoetching process and the photoetching alignment precision corresponding to the well region, and the length of the channel region is not influenced by the photoetching and etching processes and the photoetching alignment precision of a polysilicon gate, so that the length consistency of the channel region can be improved, the consistency of the on-resistance of a device and the consistency of threshold voltage can be improved, the consistency of a gate source capacitor (Cgs) can be improved, and finally the consistency of the device can be greatly improved.
In addition, if the second well region 2042 self-aligned to the planar gate structure is adopted alone as the whole body region 204, the depth of the body region 204 formed by adopting the second well region 2042 alone is shallower, and the device leakage is larger because the formation process of the second well region 2042 is limited by the planar gate structure; therefore, the body region 204 can also be formed by using the first well region 2041 formed by using a photomask before the base gate of the second well region 2042 is combined with the planar gate structure, so that the uniformity of the device can be improved by using the second well region 2042, and the leakage current of the device can be reduced by using the deeper junction depth and the graded structure of the first well region 2041.
In addition, after the first well region 2041 is introduced into the body region 204, the first well region 2041 may extend downward from the surface of the active region, so that the first well region 2041 located on the surface of the active region may be used as a component of the channel region, thereby affecting the length of the channel region and finally affecting the uniformity of the device.
The region of the anti-JFET region 205 where the JFET effect is actually reduced is a region between the channel regions covered by the planar gate structure, where the width of the region is only affected by the width of the planar gate structure, and the width of the planar gate structure is affected by the photolithography and etching processes of the planar gate structure, so that the photolithography alignment accuracy of the planar gate structure does not affect the width of the anti-JFET region 205 between the channel regions covered by the planar gate structure, and the uniformity of the gate-drain capacitance (Cgd) of the device is also greatly improved.
In addition, when the junction depth of the first well region 2041 is smaller, the surface region with higher doping concentration of the first well region 2041 can be removed through a thermal oxide layer, such as a thermal oxide layer for forming a dielectric protection ring, so that adverse effects of the surface region with higher doping concentration of the first well region 2041 on a channel region are reduced, and uniformity of devices is further improved.
When the junction depth of the first well region 2041 is deeper, the deeper junction depth is utilized to slow down the doping concentration of the whole first well region 2041, so that the doping concentration of the surface region of the first well region 2041 is also reduced, thereby reducing the adverse effect of the surface region of the first well region 2041 on the channel region and further improving the uniformity of the device.
As can be seen from the above, in the embodiment of the present invention, since the self-alignment is adopted, the second well region 2042 is not inconsistent in position due to the alignment progress, and is not different due to the different widths of the polysilicon gates. Therefore, the uniformity of the channel length of the device is obviously improved, the uniformity of the threshold voltage is improved, the uniformity of the on-resistance is improved, and the uniformity of Cgs is improved. The width of the N-type anti-JFET region between channels with the Cgd size is directly influenced, and the width of the N-type anti-JFET region only changes along with the width change of a polysilicon gate, so that the influence of the alignment precision of the photoetching of the polysilicon gate and the size and the alignment precision of a Pwell in the prior art are eliminated, and the consistency is greatly improved.
The first well region 2041 in the embodiment of the present invention is set before the polysilicon gate in the process, and different depths can be obtained by adjusting the implantation energy, the annealing temperature and the annealing time according to the process requirements, and the leakage current Ids of the device can be reduced by increasing the depth generally. Meanwhile, because the impurity concentration of the first well region 2041 can be designed to be relatively low, particularly, by designing the dielectric guard ring such as the guard ring oxide film to be made of the thermal oxide film, the process will adsorb more P-type impurities of the first well region 2041 to the interface between the oxide film and SI, and the surface P-type impurity concentration with higher concentration will be depleted, only the P-type impurities pushed into the deeper position remain, thus further improving the uniformity of the device.
In the embodiment of the present invention, the first epitaxial layer 202 is layered, the doping concentration of the first epitaxial sub-layer 2021 at the bottom is set to be relatively high, the bottom surface of the superjunction trench is required to enter into the first epitaxial sub-layer 2021, and the influence of the depth deviation of the superjunction trench on the withstand voltage can be reduced and the withstand voltage uniformity can be improved by using the characteristic that the doping concentration of the first epitaxial sub-layer 2021 is higher than that of the first epitaxial layer 202 at the top, because: when the concentration of the first epitaxial sub-layer 2021 increases, the withstand voltage below the top surface of the first epitaxial sub-layer 2021 is mainly determined by the first epitaxial sub-layer 2021, so that the effective thickness of the superjunction structure is actually located on the top surface of the first epitaxial sub-layer 2021, and even if the depths of the superjunction trenches in different areas deviate, the bottom surface of the superjunction trench is guaranteed to be inside the first epitaxial sub-layer 2021, and the longitudinal position difference of the bottom surface of the superjunction trench does not have a great influence on the withstand voltage, so that the influence of the depth deviation of the superjunction trench on the withstand voltage can be reduced and the uniformity of the withstand voltage is improved.
Meanwhile, the collector region 213 is formed on the back surface of the first epitaxial sub-layer 2021, so that the first epitaxial sub-layer 2021 located between the bottom surface of the superjunction structure and the top surface of the collector region 213 can serve as a field stop layer, thereby improving the electric field distribution of the drift region and increasing the withstand voltage of the device.
Meanwhile, the first epitaxial sublayer 2021 also serves as a barrier layer for injecting minority carriers into the collector region 213, so that the turn-off speed of the device is improved.
The doping concentration distribution of the first epitaxial layer 202 in the top region of the first epitaxial sub-layer 2021 can also be set to be larger from bottom to top according to the requirement of the super junction trench which compensates the side inclination on the charge balance of the super junction structure, for example, the first epitaxial layer 202 in the top region of the first epitaxial sub-layer 2021 can be set to be an overlapped layer of the second epitaxial sub-layer 2022 and the third epitaxial sub-layer 2023 with smaller doping concentration, so that the charge balance at each longitudinal position of the super junction structure can be improved and the device withstand voltage can be finally achieved.
Fig. 4 is a flowchart of a method for manufacturing a superjunction IGBT device according to an embodiment of the present invention; the steps are represented in fig. 4 using a mask level. Fig. 5A to 5E are schematic views of device structures in each step of the method for manufacturing a superjunction IGBT device according to the embodiment of the invention; the manufacturing method of the super-junction IGBT device comprises the following steps:
first, step S201 is performed, where step S201 is used to form a Zero Mark (Zero Mark), and a photolithography (photo) plus etching (etching) process is required to form the Zero Mark, and in fig. 4, step S201 is also denoted by Zero photo & etching.
Step one, as shown in fig. 5A, a first epitaxial layer 202 doped with a first conductivity type is formed on a semiconductor substrate 201, a plurality of superjunction trenches are formed in selected regions of the first epitaxial layer 202, a second epitaxial layer doped with a second conductivity type is filled in the superjunction trenches, the second conductivity type pillars 203 are composed of the second epitaxial layer filled in the superjunction trenches, and a first conductivity type pillar is composed of the first epitaxial layer 202 between the second conductivity type pillars 203.
A super junction structure is formed by alternately arranging a plurality of the first conductive type pillars and the second conductive type pillars 203, and a super junction unit is composed of one of the first conductive type pillars and an adjacent one of the second conductive type pillars 203.
The depth of each super-junction trench has a deviation caused by the etching process of the super-junction trench, the first epitaxial layer 202 includes a first epitaxial sub-layer 2021 located at the bottom region of the first epitaxial layer 202, the bottom surface of each super-junction trench is located at the first epitaxial sub-layer 2021, and the doping concentration of the first epitaxial sub-layer 2021 is greater than that in the region of the first epitaxial layer 202 located at the top of the first epitaxial sub-layer 2021, so as to reduce the influence of the depth deviation of the super-junction trench on the voltage resistance and improve the voltage resistance uniformity.
In the method of the embodiment of the present invention, the semiconductor substrate 201 includes a silicon substrate.
The superjunction trench has sloped sides and a top opening that is larger than a bottom opening, which facilitates etching and filling of the superjunction trench.
The region of the first epitaxial layer 202 at the top of the first epitaxial sub-layer 2021 has a doping concentration profile that becomes larger from bottom to top to compensate for the effect of the laterally inclined superjunction trench on the charge balance of the superjunction structure. In some preferred embodiment methods, at least a second epitaxial sub-layer 2022 and a third epitaxial sub-layer 2023 are included in the region on top of the first epitaxial sub-layer 2021 of the first epitaxial layer 202, the second epitaxial sub-layer 2022 being superimposed on the top surface of the first epitaxial sub-layer 2021, the third epitaxial sub-layer 2023 being superimposed on the top surface of the second epitaxial sub-layer 2022, the doping concentration of the third epitaxial sub-layer 2023 being greater than the doping concentration of the second epitaxial sub-layer 2022. As shown in fig. 5A, the first epitaxial layer 202 is formed by stacking the first epitaxial sub-layer 2021, the second epitaxial sub-layer 2022, and the third epitaxial sub-layer 2023.
In some embodiment methods, the first epitaxial sublayer 2021 is a high concentration layer, corresponding to a resistivity of, for example, 1 to 1.5ohm. The second epitaxial sub-layer 2022 is a low concentration layer, the corresponding resistivity is, for example, 2.5 ohm.cm-3 ohm.cm, the third epitaxial sub-layer 2023 has a resistivity lower than that of the second epitaxial sub-layer 2022, for example, 2.4ohm.cm, and the resistivity and thickness of the second epitaxial sub-layer 2022 and the third epitaxial sub-layer 2023 are mainly set according to the inclination angle of the second conductivity type pillars 203 in the superjunction trench, so as to obtain better charge balance.
In the method of the embodiment of the present invention, the second conductive type pillar 203 is formed by using a Trench (Trench) etching and Trench filling process, and step S202 in fig. 4 corresponds to step one, and step S202 in fig. 4 is also denoted by Trench photo & etch.
In the method of the embodiment of the present invention, as shown in fig. 5A, after the step one is completed, the step of forming the first well region 2041 further includes:
patterning the photoresist 301 using a photolithography process defines a formation region of the first well region 2041, and the first well region 2041 is located on top of the second conductivity type pillars 203 in the active region.
Ion implantation of the second conductivity type is performed to form the first well region 2041.
Annealing and advancing the first well region 2041; in the lateral direction, a space is provided between the first well region 2041 and the side surface of the planar gate structure after annealing, the first well region 2041 is aligned with the side surface of the planar gate structure, or the first well region 2041 extends to the bottom of the planar gate structure.
In the lateral direction, the first well region 2041 covers at least the center position of the second conductivity type pillar 203 and the width of the first well region 2041 on both sides of the center position of the second conductivity type pillar 203 is 0.2 μm or more; alternatively, the first well region 2041 covers the second conductivity type pillars 203 with a width of 1 micron to 2 microns or greater than 2 microns.
In the longitudinal direction, the depth of the first well region 2041 is 1 to 2 micrometers; alternatively, the depth of the first well region 2041 is 2 microns or more.
Preferably, a second conductive type ring is formed in the transition region, and the first well region 2041 and the second conductive type ring are formed simultaneously using the same process. Taking an N-type device as an example, the second conductive type ring is a P-type ring (pring). Step S203 in fig. 4 corresponds to a process of forming the P-type ring and the first well region 2041, and in fig. 4, step S203 is also denoted by Pring photo & IMP, and IMP denotes ion implantation. In other embodiments can also be: the second conductivity type ring and the first well region 2041 are formed separately; alternatively, the formation process of the second conductivity type ring and the first well region 2041 is simultaneously canceled; alternatively, the formation process of the first well region 2041 is separately canceled, leaving the formation process of the second conductivity type ring.
Step two, an active region is defined on the semiconductor substrate 201.
In the method of the embodiment of the invention, the second step comprises the following sub-steps:
as shown in fig. 5B, a material layer (Gfield) 303 of a dielectric guard ring is formed on the surface of the first epitaxial layer 202 on which the superjunction structure is formed.
And photoetching to define a forming area of the active area.
As shown in fig. 5C, the material layer 303 of the dielectric protection ring is etched to form the dielectric protection ring, the dielectric protection ring covers a transition region and a terminal region, and opens the active region, the area surrounded by the dielectric protection ring is the active region, the transition region surrounds the periphery of the active region, and the terminal region surrounds the periphery of the transition region.
In fig. 5A, surface 302 represents the surface of the active region. When the depth of the first well region 2041 is 1 to 2 micrometers, the doping concentration of the first well region 2041 is higher near the surface 302. In this case, in some preferred embodiments, the surface higher doping concentration of the first well region 2041 is removed by the following method, which includes: the dielectric guard ring is formed by laminating a thermal oxide layer formed by a thermal oxidation process or a deposition dielectric layer formed by a thermal oxide layer formed by a thermal oxidation process and a deposition process, and the thermal oxide layer of the dielectric guard ring consumes the surface of the first epitaxial layer 202 on which the superjunction structure is formed. As shown in fig. 5B, the surface 304 is located on the bottom surface of the material layer 303 of the dielectric guard ring, and it is obvious that the surface 304 is located below the surface 302, and the material, such as silicon, of the first epitaxial layer 202, where the superjunction structure is formed, between the surface 302 and the surface 304 is oxidized, so that the surface area 2041a of the first well region 2041 is oxidized.
And removing the surface area 2041a of the first well region 2041 in the process of removing the dielectric protection ring of the active region, wherein the doping concentration of the removed surface area 2041a of the first well region 2041 is higher than that of the bottom reserved area, so as to improve the uniformity of the device. In fig. 5C, the surface of the active region is shown lowered to surface 304.
In other preferred embodiments, it can also be: when the depth of the first well region 2041 is 2 μm or more, the doping concentration of the first well region 2041 becomes weak near the surface 302 in fig. 5A after diffusion promotion. At this time, the dielectric protection ring is formed by superposing a thermal oxidation layer formed by a thermal oxidation process or a deposition dielectric layer formed by a deposition process or by superposing a deposition dielectric layer formed by a deposition process, and the deposition dielectric layer of the dielectric protection ring reduces the thermal process of the device so as to reduce the specific on-resistance of the device. That is, in this case, the material layer 303 of the dielectric protection ring may be formed by a plurality of processes, for example, when the material layer 303 of the dielectric protection ring is formed by depositing a dielectric layer, the thermal process of the device may be reduced, so that the specific on-resistance of the device may be reduced.
Step S204 in fig. 4 corresponds to step two, and since the mask of step two mainly involves lithography and etching of the material layer 303 of the dielectric guard ring, i.e., gfield, step S204 is also denoted by Gfield photo & etch in fig. 4.
As shown in fig. 5D, the method of the embodiment of the present invention includes the following steps of forming the JFET resistant region 205 after the completion of the second step and before the third step is performed:
and performing first conductivity type ion implantation on the surface of the active region by taking the dielectric protection ring as a self-alignment condition to comprehensively form the anti-JFET region 205.
The anti-JFET region 205 is used to increase the first conductivity type doping concentration of the first conductivity type doped region to reduce the JFET effect.
The anti-JFET region 205 is used to compensate for the second conductivity type dopant impurities of the first well region 2041 in the surface region of the active region at the same time in the second conductivity type dopant region to reduce the effect of the first well region 2041 on the second conductivity type dopant in the surface region of the active region, such that the second conductivity type dopant of the channel region is determined by the subsequent second well region 2042.
As shown in fig. 5D, since the width of the first well region 2041 is greater than the width of the second conductivity type pillars 203, the second conductivity type doped region of the surface region of the active region is the surface region of the first well region 2041, and the first conductivity type doped region of the surface region of the active region is the surface region of the first conductivity type pillars between the first well regions 2041. After the anti-JFET region 205 is formed, the anti-JFET region 205 inverts the surface of the second conductivity type doped region to be doped with the first conductivity type, so that the entire surface area of the active region is doped with the first conductivity type, and taking an N-type device as an example, after the anti-JFET region 205 is formed, the surface of the active region is doped with the N-type, thereby preventing the P-type doping of the active region from adversely affecting the uniformity of the channel region.
Step S205 in fig. 4 corresponds to the step of forming the anti-JFET region 205, and step S205 in fig. 4 is also denoted by JFET IMP. As can be seen from comparing the flow chart corresponding to fig. 2, the method of the embodiment of the present invention changes the JFET IMP in flow, and the JFET IMP is not required to be defined by the mask, so the step S205 is located outside the mask flow.
Step three, as shown in fig. 5E, forming planar gate structures in the active region, where each planar gate structure is formed on top of each first conductivity type pillar, and the planar gate structures are in a monolithic structure; the planar gate structure is formed by overlapping a gate dielectric layer 206 and a gate conductive material layer 207.
In the method of the embodiment of the present invention, the gate dielectric layer 206 includes a gate oxide layer.
The gate conductive material layer 207 includes a polysilicon (poly) gate.
Step S206 in fig. 4 corresponds to step three, in which a mask is used to define the polysilicon, so in fig. 4, step S206 is also denoted by poly photo & etch.
Step four, as shown in fig. 5E, performing ion implantation of the second conductivity type with the planar gate structure as a self-aligned condition to form a second well region 2042, and performing annealing treatment on the second well region 2042, wherein the second well region 2042 is laterally diffused to the bottom region of the planar gate structure under the action of the annealing treatment.
The channel region is formed by the second well region 2042 being covered by the planar gate structure, and the self-aligned structure between the second well region 2042 and the planar gate structure is used to improve device uniformity.
The body 204 is formed by vertically stacking the first well 2041 and the second well 2042, where the junction depth of the first well 2041 is greater than the junction depth of the second well 2042 and the doping concentration of the first well is less than the doping concentration of the second well 2042, so as to reduce the leakage current of the device.
Step S207 in fig. 4 corresponds to step four, and step S207 in fig. 4 is also denoted by Pwell IMP. As can be seen from comparing the flow chart corresponding to fig. 2, the method of the embodiment of the present invention changes the flow of the Pwell IMP, and the Pwell IMP does not need to use the mask definition, so the step S207 is located outside the mask flow.
The fourth step further comprises the following steps:
as shown in fig. 5F, ion implantation of the first conductivity type heavily doped with the planar gate structure as a self-aligned condition is performed in the active region to form an emitter region 208. Taking an N-type device as an example, the emitter region 208 is an n+ region (Nplus), and step S208 in fig. 4 corresponds to a process step of forming the emitter region 208, in which a photomask is used to define a formation region of the emitter region 208, so that step S208 is also denoted as Nplus photo & IMP in fig. 4.
After that, an interlayer film 209.
A contact hole (Cont) 210 is formed through the interlayer film 209. In the process of forming the contact hole 210, a photolithography process is used to define a formation region of the contact hole 210, then etching is performed to form an opening of the contact hole 210, and then metal is filled in the opening of the contact hole 210 to form the contact hole. Step S209 in fig. 4 corresponds to a process step of forming the contact hole 210, in which a mask is used to define a formation region of the contact hole 210, so in fig. 4, step S209 is also denoted by contphoto & etch.
A body contact region 211 consisting of a heavily doped region of the second conductivity type is also formed at the bottom of the contact hole 210 at the top of the emitter region 208, so that the body region 204 is connected to the contact hole 210 at the top through the body contact region 211 and the emitter region 208 together. The body contact region 211 is formed by second conductive type heavily doped ion implantation after the opening of the contact hole 210 is opened.
A front side metal layer (metal) 212 is formed and the front side metal layer 212 is patterned to form an emitter metal and a gate metal. Step S210 in fig. 4 corresponds to a process step of forming the front Metal layer 212, in which a mask is used to define a pattern region of the front Metal layer 212, so in fig. 4, step S210 is also denoted by Metal photo & etch.
After the front side process is completed, the following back side process is further included:
step five, as shown in fig. 3, a back side thinning is performed, which completely removes the semiconductor substrate 201 and leaves a portion of the thickness of the first epitaxial sub-layer 2021. In some embodiments, the thickness of the first epitaxial sub-layer 2021 is 10 microns or less prior to back side thinning; after the back side is thinned, the thickness of the first epitaxial sub-layer 2021 is left to be 3 micrometers to 8 micrometers.
In the method of the embodiment of the present invention, the photomask is not used in the back side process, so the flow of the back side process is not shown in fig. 4.
Step six, as shown in fig. 3, performing a second conductivity type back ion implantation to form a collector region 213 in the back region of the remaining first epitaxial sub-layer 2021; the first epi-sub-layer 2021 between the bottom surface of the superjunction structure to the top surface of the collector region 213 serves as both a field stop layer and a minority carrier injection barrier layer of the collector region 213, improving the turn-off speed of the device.
In some embodiments, the process conditions for the backside ion implantation of the collector 213 are: b60-100Kev,1-3E13/cm 2 I.e. the implant impurity is B, implant energy 60keV-100keV, and 1-3E13/cm injection dose 2 . The collector region 213 is also activated by backside laser annealing.
As shown in fig. 3, a back metal layer 214 is formed on the back surface of the collector region 213, and the collector is composed of the back metal layer 214.
In the method of the embodiment of the invention, the super-junction IGBT device is an N-type device, the first conduction type is N-type, and the second conduction type is P-type. Other embodiments of the method can also be: the super-junction IGBT device is a P-type device, the first conduction type is P-type, and the second conduction type is N-type.
In the embodiment of the invention, the formation of the P-type channel region of the active region is self-aligned, and meanwhile, in order to solve the problem of large device leakage caused by the relatively shallow depth of the P-type well possibly brought by the self-aligned process, the process of injecting the P-type ring (ring) is also set for solving. In order to solve the problem that the inconsistent p-type ring injection position possibly affects the consistency of devices, JFET overall injection of an active region is set, so that the overall inversion process of the surface of the active region is realized, and the consistency of Cgs and Cgd of a chip is improved.
The embodiment of the invention also particularly designs at least three layers of N epitaxy with different concentrations, thereby improving the consistency of BVDss of the device.
The embodiment of the invention eliminates the influence of P well (Pwell) photoetching and the alignment precision of polysilicon photoetching on the performance of the device, so that the uniformity of the channel width of the device is obviously improved, the uniformity of threshold voltage is improved, the uniformity of on-resistance is improved, and the uniformity of Cgs is improved. The width of the N-type JFET region between channels with the Cgd size is directly influenced, and the width of the N-type JFET region only changes along with the width change of the polycrystalline gate, so that the influence of the photoetching overlay accuracy of the polycrystalline gate and the size and the overlay accuracy of a Pwell in the prior art are eliminated, and the consistency is greatly improved.
The method of the embodiment of the invention is further described with specific parameters:
taking a 650V super-junction IGBT as an example, a super-junction (SJ) structure with a step of 9 microns is used, the width of the top trench, that is, the top width of the super-junction trench, is set to 4.5 microns, and the width of the top N-type epitaxy, that is, the top width of the first epitaxial layer 202, is set to 4.5 microns. The top width of the super junction trench is the top width of the formed second conductive type pillar 203, and the top width of the first epitaxial layer 202 is the top width of the first conductive type pillar.
The semiconductor substrate 201 is N-type, and P-type can be selected in other embodiments, the resistivity of the P-type is 1-10ohm cm, and the resistivity of the first epitaxial layer 202 is on the same order of magnitude, so as to avoid the influence of impurity diffusion on the performance of the chip.
In step one, the first epitaxial layer 202 deposited on the high concentration semiconductor substrate 201 can be set as:
the total thickness of the first epitaxial layer 202 is 55 micrometers, and the thicknesses of the three sublayers of the first epitaxial layer 202 are respectively: the sub-layer 2021 was 10 microns, the sub-layer 2022 was 25 microns, and the sub-layer 2023 was 20 microns.
The superjunction trench has a certain inclination angle, for example, between 89 degrees and 89.5 degrees, and can be designed into epitaxial layers with different resistivity according to the central value of the inclination angle of the superjunction trench, and mainly, the upper region and the lower region of the superjunction trench can be better balanced as much as possible, so that higher BVDss can be obtained, or better BVDss and Rsp can be balanced. One implementation is to deposit first 10 microns of an N-type epitaxial sub-layer 2021 having a resistivity of 1.0 ohm-cm on a high concentration semiconductor substrate 201, then to deposit an N-type epitaxial sub-layer 2022 having a resistivity of 2.5 ohm-cm at a thickness of 25 microns, then to deposit an N-type epitaxial sub-layer 2023 having a resistivity of 2.0 ohm-cm at a thickness of 20 microns, maintaining the overall N-type epitaxial layer 202 thickness of 55 microns.
The first process of forming the superjunction structure mainly includes forming the P-type pillar 203, including photolithography and etching of the trench, i.e., the superjunction trench, and P-type epitaxial filling and planarization in the trench.
A dielectric film may be deposited on the N-type epitaxial layer, i.e., the first epitaxial layer 202, where the dielectric film may be a single oxide film, e.g., an oxide film with a thickness exceeding 1 micron, and the oxide film may be used as a hard mask during trench etching, and a certain thickness of the oxide film may be left after the trench is formed, e.g., an oxide film with a thickness of 0.1-0.2 micron, and during the process of performing the epitaxial filling, the oxide film may be used as a protective layer for N-type epitaxy during CMP, so that SI at the location is not to be damaged by the CMP process, resulting in leakage or quality problems.
The dielectric film can also be composed of an oxide film with the thickness of 0.1-0.15 microns, an SIN film with the thickness of 0.1-0.2 microns and an oxide film with the thickness of more than 1um on top, so that uniformity can be better controlled in the manufacturing process: for example, after the trench etching is completed, at least a part of the SIN remains on the underlying oxide film, and the SIN is removed before the epitaxial growth, so that the uniformity of the oxide film before the epitaxial growth is good and the uniformity of CMP in the outer eye can be improved.
A further improvement to the above-described multilayer film structure is that the first oxide film is formed by thermal oxidation, which further improves uniformity.
In the filling process of the P-type epitaxial layer, if the super-junction trench has a certain inclination angle, the second conductivity type column, namely the P-type column, is formed by superposing two resistivity layers, namely the sublayers 2022 and 2023, and the concentration of the P-type impurity in the trench can be divided into different sections according to the optimal charge balance requirement. For example, P-type epitaxy with different resistivity or P-type epitaxy with single concentration is adopted. The goal is to obtain the best balance of BVdss and Rsp.
In the process steps of forming the first well region 2041 and the P-type ring: by P ring lithography, a P-type ring of the transition region is defined, and a region of the first P-type well, i.e. a region of the first well region 2041, of the P-type region of the active region is defined. The P-ring surrounds the active area of the chip and may have a width of 1 micron to 50 microns, and in the case of a very wide gate bus, the P-ring may be widened accordingly because no additional chip area is added, and when the gate bus is small or even some areas do not have a gate bus, the P-ring may be reduced, and the design may be performed in consideration of the capability requirement of EAS. The P-type region of the active region, i.e., the first well region 2041, may have a certain overlap with the later active region poly gate, may be aligned with the poly gate, or even have a certain distance from the poly gate, so long as it is ensured that, when the final process is completed, the first well region 2041 must cover the top 1-2 microns of the P-type pillar, or more, or at least the top 1-2 microns of the P-type pillar in the longitudinal direction, and laterally cover at least the region about 0.2 microns around the trench center.
The P-type ring implant impurity can be B, BF2, or a combination thereof, the energy can be selected to be 30Kev-2Mev, which is the depth of the P-type column to be covered, and the temperature and time of the subsequent thermal process. The dosage can be 5E12-5E13 atoms/cm 2, one is designed as B60 Kev 1E13/cm2
The second step of forming the dielectric protection ring comprises:
the dielectric guard ring will cover the transition region and the termination region except for the outermost n+ region, which is not necessarily required, but will be removed in the active region. In some embodiments, the material layer 303 of the dielectric guard ring is formed by thermal oxidation at a temperature of 850-1050 ℃ and a thickness of 8000-10000 angstroms, or at least partially formed from a thermal oxide film. Thus, the P-type impurity in the first well region 2041 implanted in advance is pushed into the Si depth direction, and at the same time, a part of Si on the surface, for example, 3500 a to 4000 a, is oxidized off.
At least the surface material layer 303 in the active region is completely removed by dielectric guard ring lithography and etching.
In the step of forming the anti-JFET region 205:
after the photoetching and etching of the dielectric protection ring are completed, the dielectric protection ring is used as a mask to perform at least full anti-JFET injection on the active region to form an N-type anti-JFET region 205 with higher concentration, wherein the injected N-type impurity can be phosphorus or arsenic. The method mainly forms a region with concentration higher than that of N-type epitaxial impurities on the surface of the silicon wafer, and reduces the Rsp of the device. Here, the process may compensate the P-type impurity on the surface of the first well region 2041 at the same time, so that the surface of the active region becomes N-type overall. Therefore, the influence of the first well region 2041 technology on the surface of the device is reduced, namely the influence on the performances such as the threshold voltage (Vth) of the device, which are caused by the photoetching critical dimension and the alignment precision of the first well region 2041 is reduced.
The process of forming the second well region 2042 includes the following parameters:
the ion implantation of the second well region 2042 is self-aligned with a polysilicon gate, and the impurity may be B, BF2, or a combination thereof. In the method of the embodiment of the invention, B is adopted; the energy and dose are set according to the threshold voltage requirement and the desired depth of the second well region 2042, for example: the ion implantation process parameters include: the implantation impurity is B, the implantation energy is 120keV-150keV, and the implantation dosage is 1E14-2E14/cm 2 The Vth obtained is between 2V-4V.
The thickness of the gate oxide film, i.e., the gate dielectric layer 206, is set to 700 a to 1000 a, and the temperature of the thermal oxide film is set to 850 c to 1050 c.
The polysilicon gate, i.e., the gate conductive material layer 207, is high-concentration N-type polysilicon doped in situ, and has a thickness of 4000 angstroms to 8000 angstroms, such as 4000 angstroms.
The ion implantation of the second well region 2042 can be performed after the photoresist removal by the polycrystalline lithography, or can be performed after the polycrystalline lithography etching is completed but before the photoresist removal. In the case of implantation with the photoresist left, a higher energy P-type ion implantation may be employed.
After the ion implantation of the second well region 2042 is completed, the second well region 2042 is pushed to a desired lateral and longitudinal position by an annealing process at 1000-1150 ℃ for 30-180 min.
In the process of forming the emitter region 208, it includes:
after the polycrystalline electrode is formed, at least the emitter region 208 of the device is formed by n+ lithography and ion implantation, and a terminal n+ region can be formed in the outermost region of the terminal, the terminal periphery n+ region can be used to prevent surface inversion of the terminal region, the stability of the breakdown characteristics of the device is better improved, and the terminal periphery n+ region can be omitted.
The N + implant of the emitter region 208 may generally be formed by an AS or Phos implant, or a combination thereof. The implantation conditions are typically in the range of 30-100keV,1-5E15/cm 2 the injection may be followed by activation by a thermal process at 9000-1050 ℃.
The process of forming the interlayer film 209 and the contact hole 210 includes:
the interlayer film 209 is deposited by using undoped oxide film and BPSG film, forming the opening of the contact hole 210 by photolithography and etching of the contact hole 210, and performing high-concentration P injection after forming the opening of the contact hole 210 to form a body contact region 211 with a high-concentration P-type region, thereby ensuring good ohmic contact between the metal and the body region 204. The injection impurity of the body contact region 211 can be B, BF2, the injection energy is set to 20-60keV, and the dose is set to 1E13-3E15/cm 2 . After ion implantation, thermal processes at 690-900 ℃ can be used for activation.
In the opening etching of the contact hole 210, silicon in the high concentration region of n+ impurity at the bottom of the interlayer film 209 can be etched, the etching amount can be 2000 to 4000 angstroms, and the thickness of the interlayer film is generally 6000 to 10000 angstroms according to the n+ implantation condition, i.e., implantation energy and dose.
The process of forming the interlayer film 209, the contact hole 210, and the front metal layer 212 includes:
the interlayer film 209 is deposited by using undoped oxide film and BPSG film, forming the opening of the contact hole 210 by photolithography and etching of the contact hole 210, and performing high-concentration P injection after forming the opening of the contact hole 210 to form a body contact region 211 with a high-concentration P-type region, thereby ensuring good ohmic contact between the metal and the body region 204. The injection impurity of the body contact region 211 can be B, BF2, the injection energy is set to 20-60keV, and the dose is set to 1E13-3E15/cm 2 . After ion implantation, thermal processes at 690-900 ℃ can be used for activation.
In the opening etching of the contact hole 210, silicon in the high concentration region of n+ impurity at the bottom of the interlayer film 209 can be etched, the etching amount can be 2000 to 4000 angstroms, and the thickness of the interlayer film is generally 6000 to 10000 angstroms according to the n+ implantation condition, i.e., implantation energy and dose.
The metal filled in the opening of the contact hole 210 can employ: ti and TiN and W, after which W is etched back or CMP. Thereafter, alSi is performed to deposit a front side metal layer 212 on the front side of the wafer. In a preferred embodiment, the width of the contact hole 210 is set to 0.5 μm, the thickness of the interlayer film 209 is set to 8000-10000 angstrom, and the contact hole 210 is formed by filling and etching back Ti/TIN plus W or CMP.
If the contact hole 210 is large enough, ti, tiN, alCu or AlSiCu, or ALSiCu deposition can be used to directly fill the opening of the contact hole 210 and form the front side metal layer 212, followed by photolithography of the front side metal layer 212 to form the active region emitter metal and the gate metal. The thickness of the barrier layer can be TiTiNThe thickness of AlCu or AlSiCu metal is generally 4-6 μm.
In the backside process:
in step five, the thickness of the back-thinned epitaxial sub-layer 2021 is 3-8 μm
In the sixth step, the back ion implantation is P-type impurity implantation, and the implantation conditions are as follows: b60 keV-100keV,1-3E13/cm 2 I.e. the implantation impurity is B, the implantation energy is 60keV-100keV, the implantation dosage is 1-3E13/cm 2 。
The implanted ions are activated by laser annealing, after which a backside metal layer 214 is deposited on the backside to form the collector.
Such a superjunction IGBT device is formed.
In some embodiments, after the silicon wafer, that is, the front side metal layer 212 of the semiconductor substrate 201 is formed, deposition and lithography and etching of a passivation film can be further performed, or lithography of polyimide (polyimide) is further performed, and then back side thinning and deposition of the back side metal layer 214 are further performed, so as to further improve the reliability of the device. Passivation film thickness is generallyCan be oxide film, SIN, SION or their combination. The Polyimide is typically 5-10 microns thick after being subjected to a high temperature bake (bak). The passivation film and polyimide both cover the termination region and the boundary of the front side metal layer 212, typically 5-10 microns, and form a 0-10 micron guard over the scribe line edges.
In a modified example method, the following process parameters can be used:
the photoresist in the formation process of the first well region 2041 has a thickness of more than 3 micrometers, and the P-type implantation of the first well region 2041 has a thickness of 1.5-2Mev, so that the peak concentration of the ion implantation is more than 1 micrometer away from the Si surface, thereby keeping the junction depth of the least first well region 2041 more than 2 micrometers, and reducing the leakage current Idss of the device
In a modified example method, the following process parameters can be used:
After the P-type implantation of the first well region 2041 is completed and before the dielectric guard ring is formed, a high-temperature well pushing process is added, for example, annealing at a temperature of 1000-1150 ℃ for 30-180 minutes is adopted, the depth of the region of the first well region 2041 is pushed to a position which is 2 micrometers or deeper from the surface of Si, the P-type well impurity distribution of the first well region 2041 is reduced and changed slowly in the depth direction, the leakage current Ids of the device is further reduced, and the characteristics of the device body diode are improved.
In a modified example method, the following process parameters can be used:
after the P-type implantation of the first well region 2041 is completed and before the dielectric guard ring is formed, a high-temperature well pushing process is added, for example, annealing at a temperature of 1000-1150 ℃ for 30-180 minutes is adopted, the depth of the region of the first well region 2041 is pushed to a position which is 2 micrometers or deeper from the surface of Si, the P-type well impurity distribution of the first well region 2041 is reduced and changed slowly in the depth direction, the leakage current Ids of the device is further reduced, and the characteristics of the device body diode are improved. Meanwhile, the material layer of the dielectric protection ring adopts a deposited dielectric film instead of a thermal oxide film, so that the thermal process of the process flow is reduced.
In a modified example method, the following process parameters can be used:
in the process of forming the first well region 2041, the overlap of the first well region 2041 and the polysilicon gate can be set to be between 0.32 and 0.5 micrometers, so that under normal control of the process, the overlap of 0 micrometers or more is ensured between the first well region 2041 and the polysilicon gate of all the cells, and the uniformity of electric leakage Idss of the device can be improved.
In a modified example method, the following process parameters can be used:
in the fourth step, the ion implantation of the second well region 2042 can be performed with a high energy implantation, for example, the energy of the B ion implantation is higher than 1Mev, so that increasing the implantation energy can increase the effective channel length of the device, and reducing the leakage current Idss of the device can be performed with the following process parameters in an improved embodiment:
the formation process of the first well region 2041 is omitted, that is, step S203 in fig. 4 is omitted, and only the second well region 2042 is formed as the body region by the self-aligned process, so that the leakage ids of the device increases, but the uniformity of the switching characteristics, vth, on-resistance (Rdson) and the like further increases.
In a modified example method, the following process parameters can be used:
The formation process of the first well region 2041 is canceled, but the step S203 in fig. 4 is retained, in which step S203, a P-type ring is formed only in the transition region, the first well region 2041 is not formed in the active region, and only the second well region 2042 is formed as the body region by using the self-aligned process, so that the leakage ids of the device increases, but the uniformity of the switching characteristics, vth, rdson, etc. further increases.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (24)

1. A superjunction IGBT device, comprising:
a first epitaxial layer doped with a first conductive type, wherein a super junction structure is formed in the first epitaxial layer, the super junction structure is formed by alternately arranging a plurality of first conductive type columns and second conductive type columns, and a super junction unit consists of one first conductive type column and one adjacent second conductive type column;
the second conductive type columns comprise second epitaxial layers doped with a second conductive type, wherein the second epitaxial layers are filled in the super junction grooves, and the first conductive type columns consist of the first epitaxial layers between the second conductive type columns;
The structure of the super junction IGBT device in the active region comprises:
a planar gate structure formed on top of each of the first conductivity type pillars, the planar gate structure being of unitary construction; the planar gate structure is formed by laminating a gate dielectric layer and a gate conductive material layer;
the second well region is formed by annealing an ion implantation region of a second conductivity type taking the planar gate structure as a self-alignment condition; the second well region is laterally diffused to the bottom region of the planar gate structure under the action of annealing treatment;
the channel region is formed by covering the second well region by the planar gate structure, and a self-aligned structure between the second well region and the planar gate structure is used for improving the uniformity of the device;
the depth of each super-junction groove has deviation caused by the etching process of the super-junction groove, the first epitaxial layer comprises a first epitaxial sub-layer positioned in the bottom area of the first epitaxial layer, the bottom surface of each super-junction groove is positioned in the first epitaxial sub-layer, and the doping concentration of the first epitaxial sub-layer is larger than that in the area of the first epitaxial layer positioned at the top of the first epitaxial sub-layer, so that the influence of the depth deviation of the super-junction groove on the pressure resistance is reduced, and the pressure resistance uniformity is improved;
A collector region composed of a second conductivity type back ion implantation region formed in a back region of the first epitaxial sublayer;
the first epitaxial sublayer between the bottom surface of the superjunction structure to the top surface of the collector region acts as both a field stop layer and a barrier layer for minority carriers injected from the collector region.
2. The superjunction IGBT device of claim 1, wherein: the superjunction trench has sloped sides and a top opening that is larger than a bottom opening;
the first epitaxial layer has a doping concentration profile in a region at the top of the first epitaxial sub-layer that becomes larger from bottom to top to compensate for the effect of the laterally sloped superjunction trench on the charge balance of the superjunction structure.
3. The superjunction IGBT device of claim 2, wherein: the region at the top of the first epitaxial sub-layer of the first epitaxial layer at least comprises a second epitaxial sub-layer and a third epitaxial sub-layer, wherein the second epitaxial sub-layer is stacked on the top surface of the first epitaxial sub-layer, the third epitaxial sub-layer is stacked on the top surface of the second epitaxial sub-layer, and the doping concentration of the third epitaxial sub-layer is larger than that of the second epitaxial sub-layer.
4. The superjunction IGBT device of claim 3 wherein: the resistivity of the first epitaxial sublayer is at least 10% lower than the resistivity of the second epitaxial sublayer.
5. The superjunction IGBT device of claim 1, wherein the structure of the superjunction IGBT device in the active region further comprises:
a first well region composed of ion implantation regions of a second conductivity type formed on top of each of the second conductivity type pillars, the formation region of the first well region being defined by photolithography;
in the transverse direction, a space is arranged between the first well region and the side surface of the planar gate structure, the first well region is aligned with the side surface of the planar gate structure, or the first well region extends to the bottom of the planar gate structure;
the body region is formed by longitudinally superposing the first well region and the second well region, the junction depth of the first well region is larger than that of the second well region, and the doping concentration of the first well is smaller than that of the second well region, so that leakage current of the device is reduced.
6. The superjunction IGBT device of claim 5 wherein: a dielectric protection ring is formed on the surface of the first epitaxial layer on which the super junction structure is formed, the dielectric protection ring covers a transition region and a terminal region and opens the active region, the area surrounded by the dielectric protection ring is the active region, the transition region surrounds the periphery of the active region, and the terminal region surrounds the periphery of the transition region;
An anti-JFET region is formed in the active region, and consists of an ion implantation region of a first conductivity type which is comprehensively formed on the surface of the super junction structure of the active region by taking the dielectric protection ring as a self-alignment condition;
the anti-JFET region is used for improving the first conduction type doping concentration of the first conduction type doping region and reducing the JFET effect;
the anti-JFET region is used for compensating second-conductivity-type doped impurities of the first well region of the surface region of the active region at the same time in the second-conductivity-type doped region so as to reduce the influence of the first well region on the second-conductivity-type doped of the surface region of the active region, and the second-conductivity-type doped of the channel region is determined by the second well region.
7. The superjunction IGBT device of claim 5 wherein: and forming a heavily doped emitting region of the first conductivity type on the surface of the body region, wherein the emitting region and the planar gate structure are self-aligned.
8. The superjunction IGBT device of claim 6 wherein: in the transverse direction, the first well region at least covers the central position of the second conductive type column and the width of the first well region at two sides of the central position of the second conductive type column is more than 0.2 micrometers; or the first well region covers the second conductive type column, and the width of the first well region is 1-2 microns or more than 2 microns;
In the longitudinal direction, the depth of the first well region is 1-2 microns; alternatively, the depth of the first well region is 2 microns or more.
9. The superjunction IGBT device of claim 8 wherein: when the depth of the first well region is 1-2 microns, the dielectric protection ring is formed by laminating a thermal oxidation layer formed by a thermal oxidation process or a deposition dielectric layer formed by a thermal oxidation process and a deposition process, the thermal oxidation layer of the dielectric protection ring consumes the surface of the first epitaxial layer formed with the superjunction structure, the surface area of the first well region is removed in the process of removing the dielectric protection ring of the active region, and the doping concentration of the removed surface area of the first well region is higher than that of a bottom reserved area for improving the uniformity of devices;
when the depth of the first well region is more than 2 microns, the dielectric protection ring is formed by superposing a thermal oxidation layer formed by a thermal oxidation process or a deposition dielectric layer formed by a deposition process, and the deposition dielectric layer of the dielectric protection ring reduces the thermal process of the device so as to reduce the specific on-resistance of the device.
10. The superjunction IGBT device of claim 9, wherein: and a second conductive type ring is formed in the transition region, and the first well region and the second conductive type ring have the same process structure.
11. The superjunction IGBT device of any of claims 1 to 10, characterized by: the super-junction IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the super-junction IGBT device is a P-type device, the first conduction type is P-type, and the second conduction type is N-type.
12. The manufacturing method of the super-junction IGBT device is characterized by comprising the following steps of:
forming a first epitaxial layer doped with a first conductive type on a semiconductor substrate, forming a plurality of superjunction grooves in selected areas of the first epitaxial layer, filling a second epitaxial layer doped with a second conductive type in the superjunction grooves, forming first conductive type columns by taking the second epitaxial layer filled in the superjunction grooves as a component part of second conductive type columns and forming first conductive type columns by the first epitaxial layer between the second conductive type columns;
forming a super junction structure by alternately arranging a plurality of first conductive type columns and second conductive type columns, wherein a super junction unit consists of one first conductive type column and one adjacent second conductive type column;
The depth of each super-junction groove has deviation caused by the etching process of the super-junction groove, the first epitaxial layer comprises a first epitaxial sub-layer positioned in the bottom area of the first epitaxial layer, the bottom surface of each super-junction groove is positioned in the first epitaxial sub-layer, and the doping concentration of the first epitaxial sub-layer is larger than that in the area of the first epitaxial layer positioned at the top of the first epitaxial sub-layer, so that the influence of the depth deviation of the super-junction groove on the pressure resistance is reduced, and the pressure resistance uniformity is improved;
step two, defining an active region on the semiconductor substrate;
forming a planar gate structure in the active region, wherein each planar gate structure is formed on the top of each first conductive type column, and the planar gate structure is of an integral structure; the planar gate structure is formed by laminating a gate dielectric layer and a gate conductive material layer;
performing ion implantation of a second conductivity type to form a second well region by taking the planar gate structure as a self-alignment condition, and performing annealing treatment on the second well region, wherein the second well region is laterally diffused to the bottom region of the planar gate structure under the action of the annealing treatment;
The channel region is formed by covering the second well region by the planar gate structure, and a self-aligned structure between the second well region and the planar gate structure is used for improving the uniformity of the device;
fifthly, carrying out back thinning, wherein the back thinning completely removes the semiconductor substrate and keeps part of the thickness of the first epitaxial sub-layer;
step six, performing second conductivity type back ion implantation to form a collector region in the back region of the reserved first epitaxial sublayer; the first epitaxial sublayer between the bottom surface of the superjunction structure to the top surface of the collector region acts as both a field stop layer and a barrier layer for minority carriers injected from the collector region.
13. The method for manufacturing the super-junction IGBT device according to claim 12, wherein: in the first step, the super junction groove is provided with an inclined side surface, and the top opening is larger than the bottom opening;
the first epitaxial layer has a doping concentration profile in a region at the top of the first epitaxial sub-layer that becomes larger from bottom to top to compensate for the effect of the laterally sloped superjunction trench on the charge balance of the superjunction structure.
14. The method for manufacturing the super-junction IGBT device according to claim 13, wherein: the region at the top of the first epitaxial sub-layer of the first epitaxial layer at least comprises a second epitaxial sub-layer and a third epitaxial sub-layer, wherein the second epitaxial sub-layer is stacked on the top surface of the first epitaxial sub-layer, the third epitaxial sub-layer is stacked on the top surface of the second epitaxial sub-layer, and the doping concentration of the third epitaxial sub-layer is larger than that of the second epitaxial sub-layer.
15. The method for manufacturing the super-junction IGBT device according to claim 14, wherein: the resistivity of the first epitaxial sublayer is at least 10% lower than the resistivity of the second epitaxial sublayer.
16. The method for manufacturing the super-junction IGBT device according to claim 12, wherein: the first step further comprises the following steps of forming a first well region:
photoetching to define a forming area of the first well region, wherein the first well region is positioned at the top of the second conductive type column in the active region;
performing ion implantation of a second conductivity type to form the first well region;
annealing and propelling the first well region; in the transverse direction, a space is reserved between the first well region and the side surface of the planar gate structure after annealing is advanced, the first well region is aligned with the side surface of the planar gate structure, or the first well region extends to the bottom of the planar gate structure;
the body region is formed by longitudinally superposing the first well region and the second well region, the junction depth of the first well region is larger than that of the second well region, and the doping concentration of the first well is smaller than that of the second well region, so that leakage current of the device is reduced.
17. The method for manufacturing the super-junction IGBT device according to claim 16, wherein: the second step comprises the following sub-steps:
forming a material layer of a dielectric protection ring on the surface of the first epitaxial layer with the super junction structure;
photoetching to define a forming area of the active area;
and etching the material layer of the medium protection ring to form the medium protection ring, wherein the medium protection ring covers the transition area and the terminal area and opens the active area, the area surrounded by the medium protection ring is the active area, the transition area surrounds the periphery of the active area, and the terminal area surrounds the periphery of the transition area.
18. The method for manufacturing the super-junction IGBT device of claim 17, wherein: after the second step is completed and before the third step is performed, the method comprises the following steps of forming an anti-JFET region:
performing first conduction type ion implantation on the surface of the active region by taking the dielectric protection ring as a self-alignment condition to comprehensively form the anti-JFET region;
the anti-JFET region is used for improving the first conduction type doping concentration of the first conduction type doping region and reducing the JFET effect;
the anti-JFET region is used for compensating second-conductivity-type doped impurities of the first well region of the surface region of the active region at the same time in the second-conductivity-type doped region so as to reduce the influence of the first well region on the second-conductivity-type doped of the surface region of the active region, and the second-conductivity-type doped of the channel region is determined by the second well region.
19. The method for manufacturing the super-junction IGBT device of claim 18 wherein: the fourth step further comprises the following steps: ion implantation of first conductive type heavy doping taking the plane gate structure as a self-alignment condition is conducted in the active region to form an emission region.
20. The method for manufacturing the super-junction IGBT device of claim 18 wherein: in the transverse direction, the first well region at least covers the central position of the second conductive type column and the width of the first well region at two sides of the central position of the second conductive type column is more than 0.2 micrometers; or the first well region covers the second conductive type column, and the width of the first well region is 1-2 microns or more than 2 microns;
in the longitudinal direction, the depth of the first well region is 1-2 microns; alternatively, the depth of the first well region is 2 microns or more.
21. The method for manufacturing the super-junction IGBT device of claim 20 wherein: when the depth of the first well region is 1-2 microns, the dielectric protection ring is formed by laminating a thermal oxidation layer formed by a thermal oxidation process or a deposition dielectric layer formed by a thermal oxidation process and a deposition process, the thermal oxidation layer of the dielectric protection ring consumes the surface of the first epitaxial layer formed with the superjunction structure, the surface area of the first well region is removed in the process of removing the dielectric protection ring of the active region, and the doping concentration of the removed surface area of the first well region is higher than that of a bottom reserved area for improving the uniformity of devices;
When the depth of the first well region is more than 2 microns, the dielectric protection ring is formed by superposing a thermal oxidation layer formed by a thermal oxidation process or a deposition dielectric layer formed by a deposition process, and the deposition dielectric layer of the dielectric protection ring reduces the thermal process of the device so as to reduce the specific on-resistance of the device.
22. The method for manufacturing the super-junction IGBT device of claim 20 wherein: a second conductivity type ring is formed in the transition region, and the first well region and the second conductivity type ring are formed simultaneously using the same process.
23. The method for manufacturing the super-junction IGBT device of claim 18 wherein: and step three, before the formation of the anti-JFET region, the anti-JFET region inverts the surface of the second-conductivity-type doped region into first-conductivity-type doped regions.
24. The method for manufacturing the super-junction IGBT device according to claim 12, wherein: and step five, after the back surface is thinned, the thickness of the reserved first epitaxial sub-layer is 3-8 microns.
CN202311281116.2A 2023-09-28 2023-09-28 Super-junction IGBT device and manufacturing method thereof Pending CN117476755A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118099199A (en) * 2024-04-23 2024-05-28 洛阳鸿泰半导体有限公司 Three-dimensional semiconductor substrate wafer and method suitable for IGBT device manufacturing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118099199A (en) * 2024-04-23 2024-05-28 洛阳鸿泰半导体有限公司 Three-dimensional semiconductor substrate wafer and method suitable for IGBT device manufacturing

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