CN116314246A - Superjunction device and method of manufacturing the same - Google Patents

Abstract

The invention discloses a super junction device, the structure of the super junction device in an active region comprises: the planar gate structures are formed at the tops of the first conductive type columns and are of an integral structure; the second well region is formed by annealing an ion implantation region of a second conductivity type taking a planar gate structure as a self-alignment condition; the second well region is laterally diffused to the bottom region of the planar gate structure under the action of annealing treatment; the channel region is comprised of a second well region covered by a planar gate structure, and a self-aligned structure between the second well region and the planar gate structure is used to improve device uniformity. The invention also discloses a manufacturing method of the superjunction device. The invention can improve the consistency of devices.

Description

Superjunction device and method of manufacturing the same

technical field

The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to a super junction device; the invention also relates to a method for manufacturing the super junction device.

Background technique

Existing super-junction devices include current flow regions, i.e. active regions, transition regions and terminal regions; a super-junction structure is formed in the current flow region, and the super-junction structure is composed of alternately arranged P-type pillars and N-type pillars, namely P-N-type pillars . Taking the structure of striped P-N pillars as an example, there is a planar grid structure above each N-shaped pillar, which can partially cover the surrounding P-shaped pillars or not. The top of each P-shaped pillar There is a P-type well (Pwell), there is an N+ source region in the P-type well, there is a contact hole, the source metal is connected to the source region through the contact hole, and the source metal contact hole passes through a high-concentration P+ contact The area is connected to the P area. In the transition region, there is a P-type ring, and the P-type ring covers one or more P-type pillars. The P-type ring can be completed in the same process as the P-type well, and there is also a high-concentration P+ contact in the P-type ring. In the region, the formation process of the P+ contact region in the P-type ring and the P+ contact region in the current flow region are the same, and the concentration and junction depth are also the same.

In the above device structure, the width of the P-type well under the planar gate structure is actually the channel length of the device, and the channel length affects the on-resistance and switching characteristics of the device. In the N-type region between the P-type wells at the bottom of the planar gate structure, N-type impurities are generally implanted in order to reduce the on-resistance and form an anti-JFET region. The width of this anti-JFET region will directly affect the reverse direction of the device. Transfer capacitance (Crss), Crss is composed of gate-drain capacitance (Cgd), and Cgd is also Miller capacitance.

In the prior art, the Pwell is generally formed after or before the formation of the P-type pillars. First, the formation area of the P-type ring in the transition region is defined by photolithography. The width of the P-type ring is 1 micron to 50 microns, and the current is defined at the same time. The formation area of the P-type well in the flow region; after that, P-type impurities such as B or BF2 are implanted through an ion implantation process, thus forming a P-type well.

Afterwards, a dielectric protection ring is formed, including: forming the dielectric film of the dielectric protection ring, that is, the G-field dielectric film, performing photolithography and etching on the G-field dielectric film so that the G-field dielectric film only covers the surface of the transition zone and the terminal zone, The G-field dielectric film on the surface of the active area is completely removed to form a dielectric protection ring surrounding the active area.

Then form a planar gate structure, including forming a gate oxide film and a polysilicon gate, and define a gate area in the active area by gate photolithography and etching, and define a gate vertical (Bus) on the transition area, and in The termination region defines a gate region or there is no gate region in the termination region.

After the planar gate structure is formed, in the active region, the overlapping region of the P-type well and the planar gate structure forms the channel region, and the length of the channel region is actually determined by the P-type region formed by the photolithography and etching of the P-type well. The size of the polysilicon gate, as well as the influence of the position, that is, the influence of the overlay accuracy of the lithography, is also affected by the size and position of the polysilicon gate in the active region formed by the lithography and etching of the polysilicon gate. Therefore, the length of the channel region formed by the existing method, that is, the consistency of the channel length is relatively poor, and the width consistency of the anti-JFET region between the same channel regions is also relatively poor, which not only affects the on-resistance, The consistency of threshold voltage also affects the consistency of device Cgd and gate-source capacitance (Cgs), where Cgd includes the capacitance formed by the coverage of the anti-JFET region between the channel regions by the planar gate structure, and Cgd includes the capacitance formed by the planar gate structure. The capacitance formed by the gate structure covering the channel region.

The existing super junction device is described as follows in conjunction with accompanying drawing 1:

As shown in Figure 1, it is a schematic structural diagram of an existing super-junction device; Figure 1 only shows the cross-sectional structure of the active region, taking an N-type super-junction MOSFET as an example, the existing super-junction devices include:

A super junction structure is formed in the semiconductor substrate 101, the super junction structure is formed by a plurality of N-type pillars and P-type pillars 103 arranged alternately, and a super-junction unit consists of one N-type pillar and an adjacent one. The above-mentioned P-type column 103 is composed.

Typically, the semiconductor substrate 101 includes a silicon substrate. Usually, an N-type epitaxial layer 102 is formed on the surface of the semiconductor substrate 101 , and the N-type columns are composed of the N-type epitaxial layer 102 between the P-type columns 103 .

Structures in the active region of superjunction devices include:

A P-type well region (PWell) 106 formed on the top of the P-type pillar 103, the P-type well region 106 will also extend into the N-type pillars on both sides of the P-type pillar 103, the P-type Well region 106 is defined by photolithography and formed by ion implantation.

A planar gate structure is formed on the top of each of the N-type pillars, and the planar gate structure is an integral structure; the planar gate structure is formed by stacking a gate dielectric layer 104 and a gate conductive material layer 105 .

Generally, the gate dielectric layer 104 includes a gate oxide layer. The gate conductive material layer 105 includes a polysilicon gate.

The planar gate structure also needs to adopt photolithography definition and etching process to realize patterning.

N+ doped source regions 107 are self-aligned and formed on the surface of the P-type well region 106 on both sides of the planar gate structure.

The P-type well region 106 and the planar gate structure need to overlap and have the P-type well region 106 at the bottom of the planar gate structure to form a channel region. In FIG. 1, the length of the channel region is the channel region. The length adopts the Lc surface.

The region between the P-type well regions 106 at the bottom of the planar gate structure is a region where a JFET effect will occur, and the width of this region is Wj. Usually, N-type ion implantation needs to be performed in this region to form an anti-JFET region.

The front structure of the super junction device also includes:

The interlayer film 108 passes through the contact hole 109 of the interlayer film 108; the bottom of the contact hole 109 at the top of the source region 108 is also formed with a body contact region 110 composed of a P-type heavily doped region, The body region 104 is connected to the contact hole 109 at the top through the body contact region 110 and the source region 108 together.

Source metal and gate metal are formed by patterning the front metal layer 111 .

The back structure of the super junction device includes:

Thinning the semiconductor substrate 101, and then forming a drain region; the drain region is directly formed after thinning the heavily doped semiconductor substrate 101, or, the drain region is formed from the semiconductor substrate 101 After thinning, it is formed by N-type heavily doped backside ion implantation.

A backside metal layer 112 is formed.

As shown in FIG. 2 , it is a flowchart of a manufacturing method of an existing super junction device, which is used to manufacture the existing super junction structure shown in FIG. 1 ; in FIG. 2 , each step is represented by a photomask layer. The manufacturing method of the existing super junction device includes the following steps:

To perform step S101 to form the zeroth layer mark (Zero Mark), it needs to be formed by photolithography (photo) plus etching (etch) process. In FIG. 2, step S201 is also represented by Zero photo&etch.

Step S102 is performed to form the anti-JFET region, and the anti-JFET region needs to be defined by a photolithography process, so in FIG. 2, step S101 is represented by JFET photo&IMP.

Perform step S103 to form a super junction structure, that is, form the P-type pillars 103 shown in FIG. form an N-shaped column. Forming a super junction structure requires the use of a mask defining trenches, so step S103 in FIG. 2 is represented by Trench photo&etch.

Step S104 is performed to form a P-type well region 106 . The P-type well region 106 first needs to be defined by photolithography, and then formed by ion implantation. Therefore, in FIG. 1 , step S104 is represented by Pwell photo&IMP.

Carry out step S105 to form a dielectric protection ring, the dielectric protection ring needs to use the growth of the material layer (Gfield) of the dielectric protection ring, and then perform photolithography and etching to remove the material layer of the dielectric protection ring in the active region, and the remaining The material layers of the dielectric protection ring constitute the dielectric protection ring. Therefore, in FIG. 2, step S105 is represented by Gfield photo&etch.

Step S106 is performed to form a planar gate structure. The planar gate structure needs to first form a stacked structure of a gate oxide layer and a polysilicon gate, and then perform photolithography and etching to pattern the planar gate structure. Therefore, in FIG. 2, step S106 is represented by poly photo&etch.

Step S107 is performed to form the source region 107 . The active region 107 is self-aligned with the planar gate structure in the active region. The source region 107 is an N+ region (Nplus), and in the process step of forming the source region 107, a photomask is required to define the formation region of the source region 107, so in FIG. 1, step S107 is also represented by Nplus photo&IMP .

Step S108 is performed, including: forming an interlayer film 108 , and forming a contact hole (Cont) 109 passing through the interlayer film 108 . In the formation process of the contact hole 109, the formation area of the contact hole 109 needs to be defined by a photolithography process, and then the opening of the contact hole 109 is formed by etching, and then in the opening of the contact hole 109 Filling metal forms the contact hole. In the process step of forming the contact hole 109 , a photomask is needed to define the formation area of the contact hole 109 , so in FIG. 1 , step S108 is also represented by Cont photo&etch.

After the opening of the contact hole 109 is opened and before the metal is filled, a step of performing P-type heavily doped ion implantation to form the body contact region 211 is also included.

Step S109 is performed, including: forming a front metal layer (metal) 111 and patterning the front metal layer 111 to form source metal and gate metal. In the process steps of forming the front metal layer 111 , a photomask is needed to define the graphic area of the front metal layer 111 , so in FIG. 1 , step S109 is also represented by Metal photo&etch.

1 and 2, it can be seen that the P-type well region 106 needs to be realized by photolithographic definition and ion implantation. Corresponding deviation, so that the size of the P-type well region 106 changes, that is, the photolithography and implantation process will produce dimensional changes; at the same time, the photolithographic overlay accuracy will also cause the pattern position of the P-type well region 106 to change. Variety.

Similarly, the planar gate structure needs to be realized by photolithography definition and etching, and the planar gate structure will also produce dimensional changes due to photolithography and etching process parameters and pattern position changes due to photolithography overlay precision.

On the same semiconductor substrate 101, the size variation of the P-type well region 106 due to the photolithography and implantation process and the pattern position variation due to the photolithography alignment precision parameters and the planar gate structure due to the photolithography and etching process The resulting dimensional change and the pattern position change due to the photolithographic alignment precision parameters will cause the channel length Lc to change. The channel length Lc has a great influence on the on-resistance, threshold voltage, and input capacitance (Cgs) of the device, which will affect the consistency of device performance, such as the consistency of the channel length Lc, on-resistance, threshold voltage and Cgs will get worse.

Since the JFET effect is likely to occur in the N-type region between the channel regions, anti-JFET implantation will be performed to form an anti-JFET region. The N-type impurity concentration of the anti-JFET region is higher than the impurity concentration of the N-type epitaxial layer 102, for example, 1 An order of magnitude or higher, the width Wj of the anti-JFET region will directly affect the size of the Cgd of the device. The width Wj will also change, so it will affect the consistency of Cgd of the device.

The following describes the adverse effects of the existing method on device consistency in combination with specific parameters:

As can be seen from FIG. 2, the width and position of the P-type well region 106 are determined by the photolithography process of the P-type well region 106, because the critical dimension (Critical Dimension, CD) after the photolithography depends on the thickness of the photoresist. There will always be certain changes in the energy change of lithography and the change of development process (for example, within +/-0.2 microns, related to the size of lithography pattern and process selection, etc.), and the position of the pattern will also be due to the overlay accuracy. Changes within a certain range (such as 60nm-150nm); similarly, the width of the polysilicon gate is also related to the photolithography process and etching process of the polysilicon gate. It changes within a certain range, and the overlay accuracy of the lithography also fluctuates within a certain range. . If the thickness of the photoresist used is about 1 micron, and a 248nm photolithography machine is used, then the single-layer width progress may fluctuate at +-0.1 microns, and the overlay progress may fluctuate at +-0.06 microns, considering the two-layer photoresist The difference between engravings, then the channel length Lc may vary by +-0.32 microns. For a device with a pitch of 9 microns, if the polycrystalline gate width is set to 7.5 microns (already according to very wide Considering the direction), the single channel length Lc is designed to be 2-3 microns, and this fluctuation of +-0.32 microns has had a great impact on the consistency of the device. If you want to further reduce the step of the super junction, for example, set the step to 5 microns, then deduct the contact hole width of 0.5 microns, and the distance from the contact hole to the edge of the polysilicon is 0.5 microns, then the width of the entire polysilicon gate is only 3.5 microns. The side channel length Lc is definitely less than 1.7 microns, this +-0.32 microns variation will make the uniformity very poor.

Even if the range of variation can be reduced through the optimization of lithography and etching processes, especially the control of process conditions, on the one hand, these solutions require higher manufacturing costs, for example, because of the tightening of the critical dimensions and sets of lithography processes. The lithography with high engraving precision increases the rework rate of lithography and increases the manufacturing cost. At the same time, this change or consistency must exist, and at the same time, as the superjunction step decreases, this problem will become more and more prominent.

Contents of the invention

The technical problem to be solved by the present invention is to provide a super junction device, which can improve the consistency of the device. To this end, the invention also provides a method for manufacturing a super junction device.

In order to solve the above technical problems, the super junction device provided by the present invention includes:

A super junction structure is formed in the semiconductor substrate, the super junction structure is formed by a plurality of columns of the first conductivity type and columns of the second conductivity type alternately arranged, and a super junction unit is formed of a column of the first conductivity type and a phase An adjacent column of the second conductivity type.

Structures in the active region of superjunction devices include:

A planar gate structure is formed on the top of each of the pillars of the first conductivity type, and the planar gate structure is an integral structure; the planar gate structure is formed by stacking a gate dielectric layer and a gate conductive material layer.

The second well region is composed of an ion implantation region of the second conductivity type with the planar gate structure as the self-alignment condition after annealing treatment; the second well region diffuses laterally to the plane under the action of annealing treatment bottom region of the gate structure.

The channel region is composed of the second well region covered by the planar gate structure, and the self-alignment structure between the second well region and the planar gate structure is used to improve the uniformity of the device.

A further improvement is that the structure of the super junction device located in the active region further includes:

The first well region is composed of an ion implantation region of the second conductivity type formed on the top of each column of the second conductivity type, and the formation region of the first well region is defined by photolithography.

In the lateral direction, there is a space between the first well region and the side faces of the planar gate structure, alignment between the first well region and the side faces of the planar gate structure, or the first well region will extend to bottom of the planar grid structure.

The body region is vertically stacked by the first well region and the second well region, the junction depth of the first well region is greater than the junction depth of the second well region and the doping concentration of the first well region The doping concentration is lower than the doping concentration of the second well region, which is used to reduce the leakage current of the device.

A further improvement is that a dielectric protection ring is formed on the surface of the semiconductor substrate, the dielectric protection ring covers the transition region and the terminal region and opens the active region, and the area surrounded by the dielectric protection ring is the The active region, the transition region surrounds the active region, and the terminal region surrounds the transition region.

An anti-JFET region is also formed in the active region, and the anti-JFET region is fully formed on the surface of the super junction structure of the active region by using the dielectric guard ring as a self-alignment condition. Types of ion implantation regions.

The anti-JFET region is used to increase the doping concentration of the first conductivity type in the doping region of the first conductivity type to reduce the JFET effect.

The anti-JFET region is also used in the second conductivity type doping region to realize compensation for the second conductivity type doping impurities of the first P well in the surface area of the active region, so as to reduce the first P The influence of the well on the doping of the second conductivity type in the surface region of the active region makes the doping of the second conductivity type in the channel region determined by the second well region.

A further improvement is that a heavily doped source region of the first conductivity type is formed on the surface of the body region, and the source region is self-aligned with the planar gate structure.

A further improvement is that, in the lateral direction, the first well region at least covers the central position of the column of the second conductivity type and the width of the first well region on both sides of the central position of the column of the second conductivity type is 0.2 micron or more; or, the width of the first well region covering the second conductivity type column is 1 micron to 2 micron or more.

In the vertical direction, the depth of the first well region is 1-2 microns; or, the depth of the first well region is more than 2 microns.

A further improvement is that when the depth of the first well region is 1 micron to 2 microns, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process or a thermal oxide layer formed by a thermal oxidation process and The deposition medium layer formed by the deposition process is superimposed, the thermal oxide layer of the dielectric protection ring consumes the surface of the semiconductor substrate, and the first A surface region of the well region is removed, and the doping concentration of the removed surface region of the first well region is higher than that of the bottom remaining region, so as to improve the uniformity of the device.

When the depth of the first well region is more than 2 microns, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process or a thermal oxide layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process It is formed by stacking or adopting a deposition medium layer formed by a deposition process, and the deposition dielectric layer of the dielectric protection ring reduces the thermal process of the device, so as to reduce the specific on-resistance of the device.

A further improvement is that a ring of the second conductivity type is formed in the transition region, and the process structures of the first well region and the ring of the second conductivity type are the same.

A further improvement is that the semiconductor substrate includes a silicon substrate;

A first epitaxial layer doped with a first conductivity type is formed on the surface of the semiconductor substrate;

The second conductivity type column is composed of a second conductivity type doped second epitaxial layer filled in the trench;

The first conductivity type pillars consist of the first epitaxial layer between the second conductivity type pillars;

The distance between the bottom surface of the second conductivity type pillar and the top surface of the semiconductor substrate is more than 5 microns to improve the body diode characteristics of the device;

The gate dielectric layer includes a gate oxide layer;

The gate conductive material layer includes a polysilicon gate.

A further improvement is that the super-junction device includes a super-junction MOSFET or a super-junction IGBT.

A further improvement is that the super-junction device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the super-junction device is a P-type device, and the first conductivity type is P-type , the second conductivity type is N type.

In order to solve the above-mentioned technical problems, the manufacturing method of the super junction device provided by the present invention includes the following steps:

Step 1, forming a super junction structure in the semiconductor substrate, the super junction structure is formed by a plurality of columns of the first conductivity type and columns of the second conductivity type arranged alternately, and a super junction unit is formed by one column of the first conductivity type and an adjacent column of the second conductivity type.

Step 2, defining an active region on the semiconductor substrate.

Step 3, forming a planar gate structure in the active region, each of the planar gate structures is formed on the top of each of the first conductivity type columns, and the planar gate structure is an integral structure; the planar gate structure is composed of a gate The dielectric layer and the gate conductive material layer are stacked.

Step 4. Perform ion implantation of the second conductivity type under the self-alignment condition of the planar gate structure to form a second well region, and perform annealing treatment on the second well region. The role of the second well region in the annealing treatment lower lateral diffusion into the bottom region of the planar gate structure.

The channel region is composed of the second well region covered by the planar gate structure, and the self-alignment structure between the second well region and the planar gate structure is used to improve the uniformity of the device.

A further improvement is that, after step 1 is completed, the following step of forming the first well region is also included:

Photolithography defines a formation region of the first well region located on top of the second conductivity type pillars in the active region.

Ion implantation of the second conductivity type is performed to form the first well region.

performing annealing on the first well region; in the lateral direction, there is a space between the annealed first well region and the side of the planar gate structure, the first well region and the planar gate structure or the first well region will extend to the bottom of the planar gate structure.

The body region is vertically stacked by the first well region and the second well region, the junction depth of the first well region is greater than the junction depth of the second well region and the doping concentration of the first well region The doping concentration is lower than the doping concentration of the second well region, which is used to reduce the leakage current of the device.

A further improvement is that step 2 includes the following sub-steps:

A material layer of a dielectric protection ring is formed on the surface of the semiconductor substrate.

Photolithography defines the formation area of the active region.

Etching the material layer of the dielectric protection ring to form the dielectric protection ring, the dielectric protection ring covers the transition region and the terminal region and opens the active region, and the area surrounded by the dielectric protection ring is the The active region, the transition region surrounds the active region, and the terminal region surrounds the transition region.

A further improvement is to include the steps of forming the anti-JFET region as follows after step 2 is completed and before step 3 is performed:

The anti-JFET region is formed on the surface of the active region by using the dielectric guard ring as a self-alignment condition to perform ion implantation of the first conductivity type.

The anti-JFET region is used to increase the doping concentration of the first conductivity type in the doping region of the first conductivity type to reduce the JFET effect.

The anti-JFET region is also used in the second conductivity type doping region to realize compensation for the second conductivity type doping impurities of the first P well in the surface area of the active region, so as to reduce the first P The influence of the well on the doping of the second conductivity type in the surface region of the active region makes the doping of the second conductivity type in the channel region determined by the second well region.

A further improvement is that after step 4, the method further includes: performing heavily doped ion implantation of the first conductivity type with the planar gate structure as a self-alignment condition in the active region to form a source region.

A further improvement is that, in the lateral direction, the first well region at least covers the central position of the column of the second conductivity type and the width of the first well region on both sides of the central position of the column of the second conductivity type is 0.2 micron or more; or, the width of the first well region covering the second conductivity type column is 1 micron to 2 micron or more.

In the vertical direction, the depth of the first well region is 1-2 microns; or, the depth of the first well region is more than 2 microns.

A further improvement is that when the depth of the first well region is 1 micron to 2 microns, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process or a thermal oxide layer formed by a thermal oxidation process and The deposition medium layer formed by the deposition process is superimposed, the thermal oxide layer of the dielectric protection ring consumes the surface of the semiconductor substrate, and the first Removing the surface region of a well region, the doping concentration of the removed surface region of the first well region is higher than the doping concentration of the bottom remaining region, which is used to improve the uniformity of the device;

When the depth of the first well region is more than 2 microns, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process or a thermal oxide layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process It is formed by stacking or adopting a deposition medium layer formed by a deposition process, and the deposition dielectric layer of the dielectric protection ring reduces the thermal process of the device, so as to reduce the specific on-resistance of the device.

A further improvement is that a ring of the second conductivity type is formed in the transition region, and the first well region and the ring of the second conductivity type are formed simultaneously using the same process.

A further improvement is that the semiconductor substrate includes a silicon substrate;

A first epitaxial layer doped with a first conductivity type is formed on the surface of the semiconductor substrate;

The second conductivity type column is composed of a second conductivity type doped second epitaxial layer filled in the trench;

The first conductivity type pillars consist of the first epitaxial layer between the second conductivity type pillars;

The distance between the bottom surface of the second conductivity type pillar and the top surface of the semiconductor substrate is more than 5 microns to improve the body diode characteristics of the device;

The gate dielectric layer includes a gate oxide layer;

The gate conductive material layer includes a polysilicon gate.

A further improvement is that, before step 3, after the formation of the anti-JFET region, the anti-JFET region inverts the surface of the second conductivity type doped region to the first conductivity type doping.

A further improvement is that the super-junction device includes a super-junction MOSFET or a super-junction IGBT.

A further improvement is that the super-junction device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the super-junction device is a P-type device, and the first conductivity type is P-type , the second conductivity type is N type.

Different from the composition of the ion implantation region defined by the photomask in the prior art, the channel region of the present invention is composed of the second well region self-aligned with the planar gate structure, because the second well region and the planar The gate structure is self-aligned, and the second well region does not need to be defined by a mask, so the influence of the photolithography process on the pattern width and the photolithography registration on the pattern position can be eliminated, that is, the channel region formed by the second well region The length of the channel region will not be affected by the lithography process corresponding to the well region and the lithography registration accuracy. Similarly, the length of the channel region will not be affected by the lithography and etching process of the polysilicon gate and the lithography registration accuracy. In this way, the length consistency of the channel region can be improved, the consistency of the on-resistance of the device and the consistency of the threshold voltage can be improved, and the consistency of the gate-source capacitance (Cgs) can be improved, and finally the consistency of the device can be greatly improved.

In addition, if the second well region self-aligned with the planar gate structure is used alone as the entire body region, since the formation process of the second well region will be limited by the planar gate structure, the body region formed by the second well region alone The depth of the device is relatively shallow, and the leakage of the device will be large; for this reason, the present invention can also combine the basic gate of the second well region with the first well region formed by a photomask before the planar gate structure to form a bulk region, so that it can be used The consistency of the device is improved by using the second well region, and the leakage current of the device is reduced by using the deeper junction depth and the slowly changing structure of the first well region.

In addition, after the first well region is introduced into the body region, the first well region will extend downward from the surface of the active region, so that the first well region located on the surface of the active region may serve as a component of the channel region, thereby Affect the length of the channel region and finally affect the uniformity of the device. In order to solve the new problem introduced, the present invention increases the anti-JFET region implanted in the active region, because the anti-JFET region is only located on the surface of the active region and The doping of the first conductivity type opposite to the doping type of the first well region will compensate the doping impurities of the second conductivity type in the surface region of the first well region. Usually, the doping concentration of the anti-JFET region will be greater than that of the first well region. The doping concentration of the surface area of the well region, so before the second well region is formed, the anti-JFET region will make the surface of the second conductivity type doped region in the active region invert to the first conductivity type doping, so that The surface of the entire active region is doped with the first conductivity type, which can eliminate the adverse effects of the introduction of the first well region on the length and doping concentration of the channel region, so that the consistency of the device includes the consistency of the channel length and threshold voltage consistency are improved.

In the anti-JFET region, the region that actually reduces the JFET effect is the region covered by the planar gate structure between the channel regions. The width of this region is only affected by the width of the planar gate structure, and the width of the planar gate structure is affected by the planar gate structure. Due to the influence of photolithography and etching process, the photolithography registration accuracy of the planar gate structure will not affect the width of the anti-JFET area covered by the planar gate structure between the channel regions, so the gate-to-drain capacitance (Cgd) of the device Consistency has also been drastically improved.

In addition, when the junction depth of the first well region of the present invention is small, the surface region of the first well region with a higher doping concentration can be removed through a thermal oxidation layer such as a thermal oxidation layer forming a dielectric protection ring, thereby reducing the density of the first well region. The adverse effect of the surface region with higher doping concentration of the region on the channel region further improves the uniformity of the device.

When the junction depth of the first well region of the present invention is deeper, the doping concentration of the entire first well region is slowed down by using the deeper junction depth, so that the doping concentration of the surface region of the first well region will also be reduced, Therefore, the adverse effect of the surface area of the first well region on the channel region can be reduced, thereby improving the uniformity of the device.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

FIG. 1 is a schematic structural diagram of an existing superjunction device;

Fig. 2 is the flowchart of the manufacturing method of existing superjunction device;

3 is a schematic structural diagram of a superjunction device according to an embodiment of the present invention;

4 is a flowchart of a method for manufacturing a super junction device according to an embodiment of the present invention;

5A-5E are schematic diagrams of the device structure in each step of the manufacturing method of the super junction device according to the embodiment of the present invention.

Detailed ways

As shown in Figure 3, it is a schematic structural diagram of a super junction device according to an embodiment of the present invention; the super junction device according to an embodiment of the present invention includes:

A super junction structure is formed in the semiconductor substrate 201, the super junction structure is formed by alternately arranging a plurality of columns of the first conductivity type and columns of the second conductivity type 203, and a super junction unit is formed by one column of the first conductivity type and an adjacent column 203 of the second conductivity type.

In the embodiment of the present invention, the semiconductor substrate 201 includes a silicon substrate. Usually, a first conductivity type epitaxial layer 202 is formed on the surface of the semiconductor substrate 201, and the first conductivity type columns are composed of the first conductivity type epitaxial layer 202 between the second conductivity type columns 203 .

The distance between the bottom surface of the second conductivity type pillar 203 and the top surface of the semiconductor substrate 201 is more than 5 microns, generally set at 5 microns to 10 microns, so as to improve the body diode characteristics of the device.

Figure 3 only shows the structure of the super junction device located in the active region, and the structure of the super junction device located in the active region includes:

A planar gate structure is formed on the top of each of the columns of the first conductivity type, and the planar gate structure is an integral structure; the planar gate structure is formed by stacking a gate dielectric layer 206 and a gate conductive material layer 207 .

In some preferred embodiments, the gate dielectric layer 206 includes a gate oxide layer.

The gate conductive material layer 207 includes a polysilicon gate.

The second well region 2042 is composed of an ion implantation region of the second conductivity type with the planar gate structure as a self-alignment condition after annealing; the second well region 2042 laterally diffuses into the bottom region of the planar gate structure. The second well region 2042 also vertically diffuses downward under the action of the annealing treatment.

The channel region is composed of the second well region 2042 covered by the planar gate structure, and the self-alignment structure between the second well region 2042 and the planar gate structure is used to improve the uniformity of the device. In FIG. 3 , the length of the channel region is represented by Lc, and the length of the channel region is also the second well region 2042 between the two straight lines corresponding to the channel length Lc in FIG. 3 . The surface of the channel region is inverted to form a conductive channel.

Since the second well region 2042 is limited by self-alignment with the planar gate structure, the junction depth of the second well region 2042 is relatively shallow. If the second well region 2042 is used alone as the body region 204, It will produce a large leakage, which is only applicable in occasions where the requirements for leakage are not high.

Preferably, in order to reduce leakage, the structure of the super junction device in the embodiment of the present invention located in the active region further includes:

The first well region 2041 is composed of an ion implantation region of the second conductivity type formed on the top of each column 203 of the second conductivity type, and the formation region of the first well region 2041 is defined by photolithography.

In the lateral direction, there is a space between the first well region 2041 and the side of the planar gate structure, alignment between the first well region 2041 and the side of the planar gate structure, or the first well region 2041 will extend to the bottom of the planar gate structure. In FIG. 3 , it is shown that there is an overlap between the first well region 2041 and the planar gate structure.

The body region 204 is vertically stacked by the first well region 2041 and the second well region 2042, and the junction depth of the first well region 2041 is greater than the junction depth of the second well region 2042 and the first well region 2042. The doping concentration of the well is lower than the doping concentration of the second well region 2042 for reducing the leakage current of the device. In FIG. 3 , the first well region 2041 is also represented by P1 and the second well region 2042 is also represented by P2 .

In the embodiment of the present invention, the first well region 2041 is formed by photolithographic definition, ion implantation and annealing. The central position of the second conductivity type column 203 and the width of the first well region 2041 located on both sides of the central position of the second conductivity type column 203 are more than 0.2 microns; or, the first well region 2041 covers the The width of the second conductivity type pillars 203 is 1 micrometer to 2 micrometers or more.

In the vertical direction, the depth of the first well region 2041 is 1 micron-2 microns; or, the depth of the first well region 2041 is more than 2 microns.

A dielectric protection ring (not shown) is formed on the surface of the semiconductor substrate 201. The dielectric protection ring covers the transition region and the terminal region and opens the active region. The area surrounded by the dielectric protection ring is the The active region, the transition region surrounds the active region, and the terminal region surrounds the transition region.

The active region includes the super junction structure of the region surrounded by the dielectric guard ring, since the first well region 2041 extends downward from the surface of the active region, when the first well region When the doping concentration of 2041 located on the surface of the active region is high, it may have an adverse effect on the second well region 2042 located on the surface of the active region, and finally affect the size and size of the channel region. Consistency of doping concentration. For this reason, in some preferred embodiments can further include:

When the depth of the first well region 2041 is 1 micron to 2 microns, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process or a thermal oxide layer formed by a thermal oxidation process and a deposition process. The thermal oxide layer of the dielectric protection ring consumes the surface of the semiconductor substrate 201, and the first well region is removed during the removal of the dielectric protection ring of the active region. 2041 surface region removal, the doping concentration of the removed surface region of the first well region 2041 is higher than the doping concentration of the bottom remaining region, so as to improve the uniformity of the device.

When the depth of the first well region 2041 is more than 2 microns, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process or a deposition medium formed by a thermal oxidation layer formed by a thermal oxidation process and a deposition process. Layers are superimposed or composed of deposited dielectric layers formed by a deposition process, and the deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device to reduce the specific on-resistance of the device.

An anti-JFET region 205 is also formed in the active region, and the anti-JFET region 205 is fully formed on the surface of the super junction structure of the active region by taking the dielectric guard ring as a self-alignment condition. An ion implantation region of a conductivity type is formed.

The anti-JFET region 205 is used to increase the doping concentration of the first conductivity type in the doped region of the first conductivity type to reduce the JFET effect.

The anti-JFET region 205 is also used in the second conductivity type doping region to realize compensation for the second conductivity type doping impurities of the first well region 2041 in the surface area of the active region, so as to reduce the second conductivity type The effect of a P well on the doping of the second conductivity type in the surface region of the active region makes the doping of the second conductivity type in the channel region determined by the second well region 2042 .

Since the active region includes a super junction structure, the super junction structure includes the first conductivity type pillars and the second conductivity type pillars 203, the super junction structure makes the surface distribution of the active region have the first conductivity type doped region and the second conductivity type doped region; after the first well region 2041 is formed on the surface of the active region, the second conductivity type doped region on the surface of the active region will be added. Before the formation of the first well region 2042, the anti-JFET region 205 can invert all the doped regions of the second conductivity type to the first conductivity type, obviously, the surface area of the first well region 2041 can be eliminated. The adverse effect of the channel region is from improving the uniformity of the device.

A heavily doped source region 208 of the first conductivity type is formed on the surface of the body region 204 , and the source region 208 is self-aligned with the planar gate structure.

A ring of the second conductivity type is formed in the transition region, and the process structures of the first well region 2041 and the ring of the second conductivity type are the same.

In an embodiment of the present invention, the super-junction device includes a super-junction MOSFET. In other embodiments, it can also be: or, the super-junction device is a super-junction IGBT.

As shown in Figure 3, the front structure of the super junction device also includes:

The interlayer film 209 passes through the contact hole 210 of the interlayer film 209; the bottom of the contact hole 210 at the top of the source region 208 is also formed with a body contact region composed of a heavily doped region of the second conductivity type 211 , connecting the body region 204 to the contact hole 210 at the top through the body contact region 211 and the source region 208 together.

Source metal and gate metal are patterned from the front metal layer 212 .

The back structure of the super junction device includes:

The semiconductor substrate 201 is thinned, and then a drain region is formed; the drain region is directly formed after thinning the heavily doped semiconductor substrate 201, or the drain region is formed by the semiconductor substrate 201 After thinning, it is formed by ion implantation on the back side of the heavily doped first conductivity type.

A back metal layer 213 is formed on the back of the drain region, and the back metal layer 213 forms the drain.

In the embodiment of the present invention, the super junction device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, it can also be: the super junction device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

Different from the composition of the ion implantation region defined by the photomask in the prior art, the channel region in the embodiment of the present invention is composed of the second well region 2042 self-aligned with the planar gate structure, because the second well The region 2042 and the planar gate structure are self-aligned, and the second well region 2042 does not need to be defined by a photomask, so the influence of the photolithography process on the pattern width and the photolithography registration on the pattern position can be eliminated, that is, the second well region The length of the channel region formed by 2042 will not be affected by the lithography process corresponding to the well region and the lithography registration accuracy. Similarly, the length of the channel region will not be affected by the lithography and etching process of the polysilicon gate and the photolithography The impact of registration accuracy can improve the length consistency of the channel region, the consistency of the on-resistance of the device and the consistency of the threshold voltage, and the consistency of the gate-source capacitance (Cgs), which can be greatly improved. Improve device consistency.

In addition, if the second well region 2042 self-aligned with the planar gate structure is used alone as the entire body region 204, since the formation process of the second well region 2042 will be limited by the planar gate structure, the second well region 2042 alone The formed body region 204 has a shallow depth, and the leakage of the device will be large; therefore, in the embodiment of the present invention, the first well region 2041 formed by a photomask can also be used before the basic gate of the second well region 2042 is combined with the planar gate structure To form the body region 204 together, the uniformity of the device can be improved by using the second well region 2042 , and the leakage current of the device can be reduced by using the deeper junction depth and the slowly changing structure of the first well region 2041 .

In addition, after the first well region 2041 is introduced into the body region 204, the first well region 2041 will extend downward from the surface of the active region, so that the first well region 2041 located on the surface of the active region may serve as the channel region. components, thereby affecting the length of the channel region and finally affecting the consistency of the device. In order to solve the new problem introduced, the present invention increases the anti-JFET region 205 fully implanted in the active region, because the anti-JFET region 205 is only located in the active region. The surface of the source region is doped with the first conductivity type opposite to the doping type of the first well region 2041, so the doping impurities of the second conductivity type in the surface region of the first well region 2041 will be compensated. Usually, the anti-JFET region The doping concentration of 205 will be greater than the doping concentration of the surface region of the first well region 2041, so before the formation of the second well region 2042, the anti-JFET region 205 will make the surface of the second conductivity type doped region in the active region all The inversion type is doped with the first conductivity type, so that the entire surface of the active region is doped with the first conductivity type, which can eliminate the adverse effects of the introduction of the first well region 2041 on the length and doping concentration of the channel region , so that the consistency of the device including the consistency of the channel length and the consistency of the threshold voltage are improved.

The region in the anti-JFET region 205 that actually reduces the JFET effect is the region covered by the planar gate structure between the channel regions. The width of this region is only affected by the width of the planar gate structure, and the width of the planar gate structure is influenced by the Influenced by photolithography and etching process, the photolithographic alignment accuracy of the planar gate structure will not affect the width of the anti-JFET region 205 covered by the planar gate structure between the channel regions, so the gate-to-drain capacitance (Cgd ) has also been greatly improved.

In addition, in the first well region 2041 of the embodiment of the present invention, when the junction depth is small, the surface region of the first well region 2041 with higher doping concentration can also be removed through a thermal oxidation layer such as a thermal oxidation layer forming a dielectric protection ring, so that The adverse effect of the surface region with higher doping concentration of the first well region 2041 on the channel region is reduced, further improving the uniformity of the device.

When the junction depth of the first well region 2041 in the embodiment of the present invention is relatively deep, the doping concentration of the entire first well region 2041 is slowed down by using the deeper junction depth, so that the doping concentration of the surface region of the first well region 2041 The concentration is also reduced, so that the adverse effect of the surface area of the first well region 2041 on the channel region can be reduced, thereby improving the uniformity of the device.

It can be seen from the above that, in the embodiment of the present invention, since the self-alignment is adopted, the position of the second well region 2042 has no inconsistency due to overlay progress, nor is it different due to the width of the polysilicon gate. Therefore, the consistency of the channel length of the device is significantly improved, the consistency of the threshold voltage is improved, the consistency of the on-resistance is improved, and the consistency of Cgs is improved. The width of the N-type anti-JFET region between the channels that directly affects the size of Cgd also changes only with the width of the polysilicon gate, eliminating the overlay accuracy of polysilicon gate photolithography in the prior art, And Pwell's size and overlay accuracy impact, so consistency is also greatly improved.

The setting of the first well region 2041 in the embodiment of the present invention is formed before the polysilicon gate in the process, and different depths can be obtained by adjusting the implantation energy and annealing temperature and time according to the needs of the process. Usually, increasing the depth can reduce the Device leakage current Ids. At the same time, because the impurity concentration of the first well region 2041 can be designed to be relatively low, especially by designing a thermal oxide film to manufacture a dielectric protection ring such as a protective epoxy film, this process will take more of the first well region 2041 The P-type impurities are adsorbed to the interface between the oxide film and SI, and the higher concentration of the surface P-type impurities will be depleted, and only the P-type impurities that are pushed into the deeper position remain, which further improves the device. consistency.

As shown in FIG. 4 , it is a flowchart of a method for manufacturing a super junction device according to an embodiment of the present invention; in FIG. 4 , each step is represented by a photomask layer. As shown in FIG. 5A to FIG. 5E, it is a schematic diagram of the device structure in each step of the manufacturing method of the super-junction device according to the embodiment of the present invention; the manufacturing method of the super-junction device according to the embodiment of the present invention includes the following steps:

First, step S201 is performed. Step S201 is used to form the zeroth layer mark (Zero Mark), which needs to be formed by photolithography (photo) plus etching (etch) process. In FIG. 4, step S201 is also represented by Zero photo&etch.

Step 1, as shown in FIG. 5A , a super junction structure is formed in the semiconductor substrate 201, the super junction structure is formed by a plurality of pillars of the first conductivity type and columns 203 of the second conductivity type arranged alternately, and the super junction unit is formed by One pillar of the first conductivity type and one adjacent pillar of the second conductivity type 203 are formed.

In the method of the embodiment of the present invention, the semiconductor substrate 201 includes a silicon substrate. Usually, a first conductivity type epitaxial layer 202 is formed on the surface of the semiconductor substrate 201, and the first conductivity type columns are composed of the first conductivity type epitaxial layer 202 between the second conductivity type columns 203 .

The distance between the bottom surface of the second conductivity type pillar 203 and the top surface of the semiconductor substrate 201 is more than 5 microns, generally set at 5 microns to 10 microns, so as to improve the body diode characteristics of the device.

In the method of the embodiment of the present invention, the second conductivity type column 203 is formed by a trench (trench) etching and trench filling process, and step S202 in FIG. 4 corresponds to step 1. In FIG. photo&etch said.

In the method of the embodiment of the present invention, as shown in FIG. 5A , after step 1 is completed, the following step of forming the first well region 2041 is also included:

The pattern of photoresist 301 is formed by photolithography process to define the formation area of the first well region 2041 , and the first well region 2041 is located on the top of the second conductivity type pillar 203 in the active region.

Ion implantation of the second conductivity type is performed to form the first well region 2041 .

Perform annealing on the first well region 2041; in the lateral direction, there is a distance between the annealed first well region 2041 and the side of the planar gate structure, the first well region 2041 and the The sides of the planar gate structure are aligned or the first well region 2041 extends to the bottom of the planar gate structure.

In the lateral direction, the first well region 2041 covers at least the central position of the second conductivity type pillar 203 and the width of the first well region 2041 located on both sides of the central position of the second conductivity type pillar 203 is 0.2 or more than 1 micron; or, the width of the first well region 2041 covering the second conductivity type pillar 203 is 1 micron to 2 microns or more.

In the vertical direction, the depth of the first well region 2041 is 1 micron-2 microns; or, the depth of the first well region 2041 is more than 2 microns.

Preferably, a ring of the second conductivity type is formed in the transition region, and the first well region 2041 and the ring of the second conductivity type are formed simultaneously using the same process. Taking an N-type device as an example, the ring of the second conductivity type is a P-type ring (pring). Step S203 in FIG. 4 corresponds to the formation process of the P-type ring and the first well region 2041 . In FIG. 4 , step S203 is also represented by Pring photo&IMP, and IMP represents ion implantation. In other embodiments, it can also be: the ring of the second conductivity type and the first well region 2041 are formed separately; or, the formation processes of the ring of the second conductivity type and the first well region 2041 are canceled at the same time; Alternatively, the formation process of the first well region 2041 is canceled separately, and the formation process of the second conductivity type ring is retained.

Step 2, defining an active region on the semiconductor substrate 201 .

In the method of the embodiment of the present invention, step 2 includes the following sub-steps:

As shown in FIG. 5B , a material layer (Gfield) 303 of a dielectric protection ring is formed on the surface of the semiconductor substrate 201 .

Photolithography defines the formation area of the active region.

As shown in FIG. 5C, the material layer 303 of the dielectric protection ring is etched to form the dielectric protection ring. The dielectric protection ring covers the transition region and the terminal region and opens the active region. The dielectric The area surrounded by the guard ring is the active area, the transition area surrounds the active area, and the terminal area surrounds the transition area.

In FIG. 5A, surface 302 represents the surface of the active region. When the depth of the first well region 2041 is 1 micrometer to 2 micrometers, the doping concentration of the first well region 2041 is relatively high near the surface 302 . In this case, in some preferred embodiments, the following method is used to remove the high doping concentration on the surface of the first well region 2041, including: the dielectric protection ring adopts a thermal oxidation layer formed by a thermal oxidation process Composition or superposition of a thermal oxide layer formed by a thermal oxidation process and a deposition medium layer formed by a deposition process, the thermal oxide layer of the dielectric protection ring consumes the surface of the semiconductor substrate 201 . As shown in FIG. 5B, the surface 304 is the bottom surface of the material layer 303 of the dielectric protection ring. Obviously, the surface 304 is located below the surface 302, and the material of the semiconductor substrate 201 between the surface 302 and the surface 304 is oxidized, so that the surface region 2041a of the first well region 2041 is also oxidized.

In the process of removing the dielectric guard ring of the active region, the surface region 2041a of the first well region 2041 is removed, and the doping concentration of the removed surface region 2041a of the first well region 2041 is higher than that retained at the bottom The doping concentration of the region is used to improve the uniformity of the device. In FIG. 5C , the surface of the active region is shown lowered to surface 304 .

In some other preferred embodiments, it can also be: when the depth of the first well region 2041 is more than 2 microns, after diffusion advances, in FIG. 5A , near the surface 302, the depth of the first well region 2041 The doping concentration will be lightened. At this time, the dielectric protection ring is composed of a thermal oxidation layer formed by a thermal oxidation process, or a thermal oxidation layer formed by a thermal oxidation process and a deposition medium layer formed by a deposition process are superimposed, or a deposition medium formed by a deposition process is used. Layer composition, the deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device, so as to reduce the specific on-resistance of the device. That is, in this case, the material layer 303 of the dielectric protection ring has a variety of forming processes to choose from. For example, when the material layer 303 of the dielectric protection ring is all made of a deposited dielectric layer, the thermal process of the device will be reduced. , which can reduce the specific on-resistance of the device.

Step S204 in FIG. 4 corresponds to step 2. Since the photomask in step 2 mainly involves the photolithography and etching of the material layer 303 of the dielectric protection ring, that is, Gfield, step S204 is also represented by Gfield photo&etch in FIG. 4 .

As shown in FIG. 5D, in the method of the embodiment of the present invention, after step 2 is completed and before step 3 is performed, the steps of forming the anti-JFET region 205 are included as follows:

The anti-JFET region 205 is fully formed on the surface of the active region by performing the first conductivity type ion implantation under the self-alignment condition of the dielectric guard ring.

The anti-JFET region 205 is used to increase the doping concentration of the first conductivity type in the doped region of the first conductivity type to reduce the JFET effect.

The anti-JFET region 205 is also used in the second conductivity type doping region to realize compensation for the second conductivity type doping impurities of the first P well in the surface area of the active region, so as to reduce the first The effect of the P well on the doping of the second conductivity type in the surface region of the active region makes the doping of the second conductivity type in the channel region determined by the subsequent second well region 2042 .

As can be seen from FIG. 5D , since the width of the first well region 2041 is greater than the width of the second conductivity type pillar 203, the second conductivity type doped region of the surface region of the active region is the second conductivity type doped region. The surface area of a well region 2041 , the doped region of the first conductivity type in the surface area of the active region is the surface area of the columns of the first conductivity type between the first well regions 2041 . After the anti-JFET region 205 is formed, the anti-JFET region 205 inverts the surface of the second conductivity type doped region to the first conductivity type doping, so that the entire surface area of the active region is the first conductivity type. Conductive type doping, taking N-type devices as an example, after the anti-JFET region 205 is formed, the surface of the active region is all N-type doped, which can prevent the P-type doping of the active region from affecting the channel region. Consistency is adversely affected.

Step S205 in FIG. 4 corresponds to the step of forming the anti-JFET region 205 . In FIG. 4 , step S205 is also represented by JFET IMP. Compared with the flow chart corresponding to FIG. 2 , it can be seen that the method of the embodiment of the present invention has made changes to the JFET IMP process. The JFET IMP no longer needs to be defined by a mask, so step S205 is located outside the mask process.

Step 3, as shown in FIG. 5E , forming a planar gate structure in the active region, each of the planar gate structures is formed on the top of each of the first conductivity type pillars, and the planar gate structure is an integral structure; The above-mentioned planar gate structure is formed by stacking a gate dielectric layer 206 and a gate conductive material layer 207 .

In the method of the embodiment of the present invention, the gate dielectric layer 206 includes a gate oxide layer.

The gate conductive material layer 207 includes a polysilicon (poly) gate.

Step S206 in FIG. 4 corresponds to step three. In step three, a photomask is required to define the polysilicon. Therefore, in FIG. 4, step S206 is also represented by poly photo&etch.

Step 4. As shown in FIG. 5E , perform ion implantation of the second conductivity type under the self-alignment condition of the planar gate structure to form a second well region 2042 , and perform annealing treatment on the second well region 2042 . The second well region 2042 laterally diffuses to the bottom region of the planar gate structure under the effect of annealing treatment.

The channel region is composed of the second well region 2042 covered by the planar gate structure, and the self-alignment structure between the second well region 2042 and the planar gate structure is used to improve the uniformity of the device.

The body region 204 is vertically stacked by the first well region 2041 and the second well region 2042, and the junction depth of the first well region 2041 is greater than the junction depth of the second well region 2042 and the first well region 2042. The doping concentration of the well is lower than the doping concentration of the second well region 2042 for reducing the leakage current of the device.

Step S207 in FIG. 4 corresponds to step 4. In FIG. 4, step S207 is also represented by Pwell IMP. Compared with the flow chart corresponding to FIG. 2 , it can be seen that the method of the embodiment of the present invention changes the flow of Pwell IMP. Pwell IMP no longer needs to use mask definition, so step S207 is located outside the mask flow.

After step four also include:

As shown in FIG. 3 , a source region 208 is formed by performing heavily doped ion implantation of the first conductivity type under the self-alignment condition of the planar gate structure in the active region. Taking an N-type device as an example, the source region 208 is an N+ region (Nplus), step S208 in FIG. The mask defines the formation area of the source region 208, so in FIG. 4, step S208 is also represented by Nplus photo&IMP.

After that, the interlayer film 209 .

A contact hole (Cont) 210 is formed through the interlayer film 209 . In the formation process of the contact hole 210, the formation area of the contact hole 210 needs to be defined first by photolithography, and then the opening of the contact hole 210 is formed by etching, and then in the opening of the contact hole 210 Filling metal forms the contact hole. Step S209 in Fig. 4 corresponds to the forming process step of the contact hole 210, which needs to use a photomask to define the forming area of the contact hole 210 in the forming process step of the contact hole 210, so in Fig. 4, the step S209 is also represented by Cont photo&etch.

The bottom of the contact hole 210 located at the top of the source region 208 is also formed with a body contact region 211 composed of a heavily doped region of the second conductivity type, so that the body region 204 passes through the body contact region 211 and the The source region 208 is connected together to the contact hole 210 on top. The body contact region 211 is formed by implanting heavily doped ions of the second conductivity type after the opening of the contact hole 210 is opened.

A front metal layer (metal) 212 is formed and patterned to form source metal and gate metal. Step S210 in Fig. 4 corresponds to the formation process step of the front metal layer 212, in the formation process step of the front metal layer 212, it is necessary to use a photomask to define the pattern area of the front metal layer 212, so Fig. 4 , step S210 is also represented by Metal photo&etch.

In the method of the embodiment of the present invention, the super-junction device is a super-junction MOSFET. In other embodiments, the method can also be: the super-junction device is a super-junction IGBT.

After the front process is completed, the following back process is also included:

The semiconductor substrate 201 is thinned, and then a drain region is formed; the drain region is directly formed after thinning the heavily doped semiconductor substrate 201, or the drain region is formed by the semiconductor substrate 201 After thinning, it is formed by ion implantation on the back side of the heavily doped first conductivity type.

A back metal layer 213 is formed on the back of the drain region, and the back metal layer 213 forms the drain.

In the method of the embodiment of the present invention, the super junction device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the method can also be: the super junction device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

The method of the embodiment of the present invention is further described below in conjunction with specific parameters:

Taking a 600V N-type super-junction MOSFET as an example, a super-junction (SJ) structure with a step size of 9 microns is used, the width of the top trench is set to 4 microns, and the width of the top N-type epitaxial layer is 5 microns.

The semiconductor substrate 201 is a high-concentration substrate with a resistivity of 0.001-0.003 Ohm.cm.

The epitaxial layer of the first conductivity type, that is, the N-type epitaxial layer 202, can be set as follows:

The thickness of the N-type epitaxial layer 202 may be 50 microns, or other values within 45-55 microns.

If the groove of the second conductivity type column, that is, the P-type column 203 is very close to the vertical, for example, the inclination angle is between 89-90 degrees, then the N-type epitaxial layer 202 can be selected as a single layer with a resistivity of 1-1.5 ohm.cm N-type epitaxy:

If the P-type trench has a certain inclination angle, such as between 88-89 degrees, then it can be designed as an epitaxial layer with different resistivity according to the central value of the inclination angle of the trench. The lower region can get a better charge balance, resulting in a higher breakdown voltage (BVdss), or a better balance between BVdss and specific on-resistance (Rsp). For example, if the P-type trench of the device is implemented, an N-type epitaxy with a resistivity of 1.5 ohms. cm is deposited on a high-concentration N-type substrate first, and then deposited with a thickness of 30-20 microns. The resistivity of the N-type epitaxial layer is 1.25 ohm.cm, and the thickness of the entire N-type epitaxial layer is kept at 50 microns

For a P-type trench with a certain inclination angle, another epitaxial setting scheme is to use a PN structure with a continuously changing concentration of N-type impurities. For example, for a device with a P-type column thickness of 40 microns, the N-type Deposit a resistivity of 1 ohm.cm with a thickness of 10 microns on a high-concentration substrate, and then deposit an N-type epitaxy with a thickness of 40 μm and a continuously changing N-type impurity concentration. The resistivity of the N-type epitaxy changes according to PN in each horizontal plane The upper balance is used to design, that is, the center value of the tilt angle of the P-type column is calculated, and the N-type impurity concentration at the top and bottom to achieve charge balance is calculated, and then the resistivity of other positions in the middle is linearized between these two values. Variety. The P-type impurity concentration is set to be consistent in the trench, because the size of the P-type column is large at the top, requiring a high charge-balanced N-type impurity concentration and low resistivity; a small bottom requires a charge-balanced N-type impurity concentration. The resistivity is high, so the N-type resistivity can increase linearly from the top to the bottom of the PN column.

Step 1 The process of forming the super junction structure is mainly to form P-type pillars 203, including trench photolithography and etching, trench P-type epitaxial filling and planarization

A dielectric film can be deposited on the N-type epitaxial layer 202 first, where the dielectric film can be a single oxide film such as an oxide film with a thickness of more than 1 micron, and this oxide film can be used as a hard mask during trench etching. After formation, there is still an oxide film with a certain thickness left, for example, an oxide film with a thickness of 0.1-0.2 microns. After the epitaxial filling is completed and the process of CMP is performed, the oxide film is used as a protective layer for N-type epitaxy during CMP, so that The SI at this place should not be defective by the CMP process, causing leakage or quality problems.

The dielectric film here can also be composed of a layer of oxide film with a thickness of 0.1-0.15 microns, a layer of SIN film with a thickness of 0.1-0.2 microns, and an oxide film with a thickness of more than 1um on the top, which can be better in the manufacturing process. Perfectly control the uniformity: for example, after the trench etching is completed, at least part of the SIN remains on the oxide film under it, and the SIN is removed before the epitaxial growth, so that the uniformity of the oxide film before the epitaxial growth is good, The uniformity of CMP in the outer eye can also be improved.

A further improvement to the above multilayer film structure is that the first oxide film is formed by thermal oxidation, which further improves the uniformity.

Here, in the P-type filling process, if the trench is very vertical, such as 89-90 degrees, then epitaxy with a single concentration of impurity concentration can be used; if the P-type trench has a certain inclination angle, such as between 88-89 degrees , no matter whether the N-type epitaxy adopts a single resistivity or two resistivity, the P-type impurity concentration in the trench can be divided into different segments according to the requirements of the best charge balance. It is to use P-type epitaxy with different resistivity. For example, if the N-type epitaxial layer 202 is a single layer, the bottom of the trench can be filled with P-type epitaxy with high concentration and low resistivity, and the top of the trench can be filled with P-type epitaxy with high resistivity. If the N-type impurity concentration has set a continuous change in resistivity according to the trench inclination angle, then the P-type epitaxy can adopt a single resistivity. The goal is to get the best balance of BVdss and Rsp.

In the process step of forming the first well region 2041 and the P-type ring: the P-type ring of the transition region is defined by photolithography of the P-type ring, and the region of the first well region 2041 is defined at the same time. The P-type ring surrounds the active area of the chip, and its width can be from 1 micron to 50 microns. In the case of a very wide gate (gate) bus (bus), the P-type ring can also be widened accordingly because no additional The chip area increases. When the gate bus is small or even there is no gate bus in some areas, then the P-ring can also be reduced, and the design can be done considering the capability requirements of EAS. The first well region 2041 may have a certain overlap with the polycrystalline gate in the subsequent active region, or may be aligned with the polycrystalline, or even have a certain distance from the polycrystalline gate, as long as it is ensured that when the final process is completed, The first well region 2041 must cover the top of the P-type pillar 203 by 1-2 microns, or more, or at least cover the top of the P-type pillar 203 by 1-2 microns in the longitudinal direction, and cover at least 0.2 microns from the center of the groove in the lateral direction. area.

The implanted impurity of the P-type ring can be B, or BF2, or their combination, and the energy can be selected between 30Kev-2Mev, which is designed according to the depth of the P-type column 203 that needs to be covered, and the temperature and time of the subsequent thermal process. The dose can be 5E12-5E13 atoms/cm ² ; one design is B 60keV 1E13/cm ² , that is, implantation impurity is B, implantation energy is 60keV, and implantation dose is 1E13/cm ² .

Step 2 of forming a dielectric protection ring includes:

The dielectric guard ring will cover the transition region and the termination region except for the outermost N+ region, which is not required and will be removed in the active region. In some embodiments, the material layer 303 of the dielectric protection ring is formed by thermal oxidation at a temperature of 850° C.-1050° C. with a thickness of 8000 angstroms to 10000 angstroms, or at least partly formed of a thermal oxidation film. In this way, while pushing the previously implanted P-type impurities in the first well region 2041 to the Si depth direction, the surface part of Si, such as 3500-4000A, containing the implanted P-type impurities is also oxidized.

At least the surface material layer 303 in the active region is completely removed by photolithography and etching of the dielectric protection ring.

In the step of forming the anti-JFET region 205:

After the dielectric protection ring photolithography and etching are completed, use the dielectric protection ring as a mask to at least perform a comprehensive anti-JFET implantation on the active region to form an N-type anti-JFET region 205 with a higher concentration. The implanted N-type impurities can Phosphorus, or arsenic. This is mainly to form a region with a concentration higher than the N-type epitaxial impurity concentration on the surface of the silicon wafer to reduce the Rsp of the device. Here, this process can simultaneously compensate the P-type impurities on the surface of the first well region 2041, so that the surface of the active region becomes N-type in its entirety. Therefore, the influence of the process of the first well region 2041 on the surface of the device is reduced, that is, the influence of the critical dimension of the first well region 2041 photolithography and the overlay accuracy on the device threshold voltage (Vth) and other performances is reduced.

The formation process of the second well region 2042 includes the following parameters:

The ion implantation in the second well region 2042 is self-aligned with the polysilicon gate, and the impurity can be B, BF2 or their combination. In the method of the embodiment of the present invention, B is used; the energy and dose are set according to the requirements of the threshold voltage and the desired depth of the second well region 2042. For example, an ion implantation process parameter includes: the implanted impurity is B, and The energy is 120keV-150keV, the implant dose is 1E14-2E14/cm ² ., and the obtained Vth is between 2V-4V.

Here, the thickness of the gate oxide film, that is, the gate dielectric layer 206 is set to 700A-1000A, and the manufacturing temperature of the thermal oxide film is 850°C-1050°C.

The polysilicon gate, that is, the gate conductive material layer 207 is in-situ doped high-concentration N-type polysilicon with a thickness of 4000 angstroms to 8000 angstroms, such as 4000 angstroms.

The ion implantation of the second well region 2042 can be performed after the photoresist of the polycrystalline lithography is removed, or after the polycrystalline lithography is etched, but before the photoresist is removed. In the case of retaining the photoresist for implantation, higher energy P-type ion implantation can be used.

After the ion implantation of the second well region 2042 is completed, the second well region 2042 is pushed to the desired horizontal and vertical positions through an annealing process at 1000° C.-1150° C. for 30-180 minutes.

In the formation process of the source region 208, including:

After the polycrystalline electrode is formed, at least the source region 10 of the device is formed by N+ lithography and ion implantation, and the terminal N+ region can also be formed in the outermost region of the terminal, and the terminal peripheral N+ region can be used to prevent surface inversion of the terminal region , which better improves the stability of the breakdown characteristics of the device, and the N+ region around the terminal can also be omitted.

The N+ implantation of the source region 208 can generally be formed by AS or Phos implantation, or a combination thereof. The injection conditions are generally 30-100keV, 1-5E15/cm ² , and can be activated by a thermal process at 9000-1050°C after injection.

The formation process of the interlayer film 209 and the contact hole 210 includes:

For depositing the interlayer film 209, a combination of an undoped oxide film and a BPSG film can be used, and then the opening of the contact hole 210 is formed by photolithography and etching of the contact hole 210, and a high concentration is performed after the opening of the contact hole 210 is formed. P implantation forms a body contact region 211 composed of a high-concentration P-type region to ensure good ohmic contact between the metal and the body region 204. The implanted impurities in this body contact region 211 can be B, BF2, and the implantation energy is set at 20-60keV. The dose was set at 1E13-3E15/cm ² . After ion implantation, a thermal process at a temperature of 690-900°C can be used for activation.

During the etching of the opening of the contact hole 210, the silicon in the N+ impurity high-concentration region at the bottom of the interlayer film 209 can also be etched away. The etching amount can be 2000 angstroms to 4000 angstroms, according to the N+ implantation conditions, that is, the implantation energy and dose. Generally, the thickness of the interlayer film is 6000-10000 Angstroms.

The formation process of the interlayer film 209, the contact hole 210 and the front metal layer 212 includes:

For depositing the interlayer film 209, a combination of an undoped oxide film and a BPSG film can be used, and then the opening of the contact hole 210 is formed by photolithography and etching of the contact hole 210, and a high concentration is performed after the opening of the contact hole 210 is formed. P implantation forms a body contact region 211 composed of a high-concentration P-type region to ensure good ohmic contact between the metal and the body region 204. The implanted impurities in this body contact region 211 can be B, BF2, and the implantation energy is set at 20-60keV. The dose was set at 1E13-3E15/cm ² . After ion implantation, a thermal process at a temperature of 690-900°C can be used for activation.

During the etching of the opening of the contact hole 210, the silicon in the N+ impurity high-concentration region at the bottom of the interlayer film 209 can also be etched away. The etching amount can be 2000 angstroms to 4000 angstroms, according to the N+ implantation conditions, that is, the implantation energy and dose. Generally, the thickness of the interlayer film is 6000-10000 Angstroms.

The metal filled in the opening of the contact hole 210 can be: Ti, TiN and W, and W is then etched back or CMP. Then perform AlSi to deposit the front metal layer 212 on the front side of the silicon wafer. In a preferred embodiment, the width of the contact hole 210 is set to 0.5 microns, the thickness of the interlayer film 209 is set to 8000-10000 angstroms, and the opening of the contact hole 210 is contacted by Ti/TIN plus W filling plus etching or CMP. Hole 210.

以及TiN

AlCu或者AlSiCu金属的厚度一般在4-6μm。If the size of the contact hole 210 is large enough, Ti, TiN, AlCu or AlSiCu, or AlSiCu deposition can also be used to directly fill the opening of the contact hole 210 and form the front metal layer 212, and then carry out the photoelectric process of the front metal layer 212. At the same time, the source metal and gate metal of the active area are formed. The thickness of the barrier layer can be Ti as

and TiN

The thickness of AlCu or AlSiCu metal is generally 4-6 μm.

Afterwards, the back side of the silicon wafer 201 is thinned, and a back metal layer 213 is deposited on the back side to form a drain.

Such a super junction MOSFET device is formed.

能是氧化膜，SIN，SION或者他们的组合。Polyimide一般进入高温烘烤(bake)后，厚度在5-10微米。钝化膜和polyimide都主要覆盖住终端区域，和正面金属层212的边界，一般覆盖5-10微米，并在划片槽最边上形成0-10微米的保护。In some embodiments, after the silicon wafer, that is, the front metal layer 212 of the semiconductor substrate 201 is formed, the deposition, photolithography and etching of the passivation film can be performed, or polyimide ( polyimide) photolithography, followed by back thinning and deposition of the back metal layer 213, which further improves the reliability of the device. passivation film thickness

It can be oxide film, SIN, SION or their combination. Polyimide is generally baked at high temperature, with a thickness of 5-10 microns. Both the passivation film and the polyimide mainly cover the terminal area and the boundary of the front metal layer 212, generally covering 5-10 microns, and forming a protection of 0-10 microns on the edge of the scribe line.

In an improved embodiment method, the following process parameters can be adopted:

In the formation process of the first well region 2041, the thickness of the photoresist is more than 3 microns, and the P-type implantation of the first well region 2041 is 1.5-2 Mev, so that the position of the peak concentration of ion implantation is greater than 1 micron from the Si surface, Therefore, the junction depth of the minimum first well region 2041 is kept greater than 2 microns, and the leakage current Idss of the device can be reduced.

In an improved embodiment method, the following process parameters can be adopted:

After the P-type implantation of the first well region 2041 is completed and before the dielectric protection ring is formed, a high-temperature push-well process is added, for example, annealing at a temperature of 1000-1150° C. for 30-180 minutes, and the first well region The depth of the 2041 region is pushed to a position 2 microns or deeper from the Si surface, and the P-type well impurity distribution in the first well region 2041 is reduced and gradually changed in the depth direction, further reducing the leakage current Ids of the device, and improving the device body. Diode Characteristics

In an improved embodiment method, the following process parameters can be adopted:

In the formation process of the first well region 2041, the thickness of the photoresist is more than 3 microns, and the P-type implantation of the first well region 2041 is 1.5-2 Mev, so that the position of the peak concentration of ion implantation is greater than 1 micron from the Si surface, Therefore, the junction depth of the minimum Pwell is kept greater than 2 microns, and at the same time, the material layer of the dielectric protection ring adopts a deposited dielectric film instead of a thermal oxide film, thus reducing the thermal process of the process flow and improving the Rsp of the device.

In an improved embodiment method, the following process parameters can be adopted:

After the P-type implantation of the first well region 2041 is completed and before the dielectric protection ring is formed, a high-temperature push-well process is added, for example, annealing at a temperature of 1000-1150° C. for 30-180 minutes, and the first well region The depth of the 2041 region is pushed to a position 2 microns or deeper from the Si surface, and the P-type well impurity distribution in the first well region 2041 is reduced and gradually changed in the depth direction, further reducing the leakage current Ids of the device, and improving the device body. characteristics of diodes. At the same time, the material layer of the dielectric protection ring adopts a deposited dielectric film instead of a thermal oxide film, thus reducing the thermal process of the process flow.

In an improved embodiment method, the following process parameters can be adopted:

In the formation process of the first well region 2041, the overlap between the first well region 2041 and the polysilicon gate can be set between 0.32-0.5 microns to ensure that under the normal control of the process, the first well region 2041 and the polysilicon gate of all original cells There is an overlap greater than or equal to 0 microns between the gates, which can improve the consistency of the leakage Idss of the device.

In an improved embodiment method, the following process parameters can be adopted:

In step 4, the ion implantation of the second well region 2042 can adopt high-energy implantation, for example, the energy of B ion implantation is higher than 1 Mev, so increasing the implantation energy can increase the effective channel length of the device and reduce the leakage current Idss of the device

In an improved embodiment method, the following process parameters can be adopted:

Canceling the formation process of the first well region 2041 means canceling step S203 in FIG. The consistency of characteristics, Vth, on-resistance (Rdson), etc. will be further improved.

In an improved embodiment method, the following process parameters can be adopted:

Cancel the formation process of the first well region 2041, but retain step S203 in FIG. The alignment process forms the second well region 2042 as the body region. At this time, the leakage ids of the device will increase, but the consistency of switching characteristics, Vth, Rdson, etc. will be further improved.

The present invention has been described in detail through specific examples above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (22)

1. A superjunction device, characterized in that, comprising: A super junction structure is formed in the semiconductor substrate, the super junction structure is formed by a plurality of columns of the first conductivity type and columns of the second conductivity type alternately arranged, and a super junction unit is formed of a column of the first conductivity type and a phase An adjacent column of the second conductivity type; Structures in the active region of superjunction devices include: A planar gate structure, formed on the top of each of the first conductivity type pillars, the planar gate structure is an integral structure; the planar gate structure is formed by stacking a gate dielectric layer and a gate conductive material layer; The second well region is composed of an ion implantation region of the second conductivity type with the planar gate structure as the self-alignment condition after annealing treatment; the second well region diffuses laterally to the plane under the action of annealing treatment the bottom region of the gate structure; The channel region is composed of the second well region covered by the planar gate structure, and the self-alignment structure between the second well region and the planar gate structure is used to improve the uniformity of the device. 2. The super junction device according to claim 1, wherein the structure of the super junction device located in the active region further comprises: The first well region is composed of an ion implantation region of the second conductivity type formed on the top of each column of the second conductivity type, and the formation area of the first well region is defined by photolithography; In the lateral direction, there is a space between the first well region and the side faces of the planar gate structure, alignment between the first well region and the side faces of the planar gate structure, or the first well region will extend to the bottom of the planar grid structure; The body region is vertically stacked by the first well region and the second well region, the junction depth of the first well region is greater than the junction depth of the second well region and the doping concentration of the first well region The doping concentration is lower than the doping concentration of the second well region, which is used to reduce the leakage current of the device. 3. The super junction device according to claim 2, characterized in that: a dielectric guard ring is formed on the surface of the semiconductor substrate, and the dielectric guard ring covers the transition region and the terminal region and covers the active region Open, the area surrounded by the dielectric guard ring is the active area, the transition area surrounds the active area, and the terminal area surrounds the transition area; An anti-JFET region is also formed in the active region, and the anti-JFET region is fully formed on the surface of the super junction structure of the active region by using the dielectric guard ring as a self-alignment condition. The type of ion implantation area composition; The anti-JFET region is used to increase the first conductivity type doping concentration of the first conductivity type doped region to reduce the JFET effect; The anti-JFET region is also used in the second conductivity type doping region to realize compensation for the second conductivity type doping impurities of the first P well in the surface area of the active region, so as to reduce the first P The influence of the well on the doping of the second conductivity type in the surface region of the active region makes the doping of the second conductivity type in the channel region determined by the second well region. 4. The super junction device according to claim 3, wherein a heavily doped source region of the first conductivity type is formed on the surface of the body region, and the source region is self-aligned with the planar gate structure. 5. The super junction device according to claim 3, characterized in that: in the lateral direction, the first well region covers at least the central position of the second conductivity type column and the first well region is located at the first The width on both sides of the central position of the column of the second conductivity type is more than 0.2 microns; or, the width of the first well region covering the column of the second conductivity type is more than 1 micron to 2 microns; In the vertical direction, the depth of the first well region is 1-2 microns; or, the depth of the first well region is more than 2 microns. 6. The super junction device according to claim 5, wherein when the depth of the first well region is 1 micron to 2 microns, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process Alternatively, a thermal oxide layer formed by a thermal oxidation process and a deposition medium layer formed by a deposition process are superimposed, and the thermal oxide layer of the dielectric protection ring consumes the surface of the semiconductor substrate, and in the active region The surface region of the first well region is removed during the removal of the dielectric protection ring, and the doping concentration of the removed surface region of the first well region is higher than that of the bottom remaining region, which is used to improve the performance of the device. consistency; When the depth of the first well region is more than 2 microns, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process or a thermal oxide layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process It is formed by stacking or adopting a deposition medium layer formed by a deposition process, and the deposition dielectric layer of the dielectric protection ring reduces the thermal process of the device, so as to reduce the specific on-resistance of the device. 7. The super junction device according to claim 6, wherein a ring of the second conductivity type is formed in the transition region, and the process structure of the first well region and the ring of the second conductivity type are the same. 8. The super junction device according to claim 1, wherein the semiconductor substrate comprises a silicon substrate; A first epitaxial layer doped with a first conductivity type is formed on the surface of the semiconductor substrate; The second conductivity type column is composed of a second conductivity type doped second epitaxial layer filled in the trench; The first conductivity type pillars consist of the first epitaxial layer between the second conductivity type pillars; The distance between the bottom surface of the second conductivity type pillar and the top surface of the semiconductor substrate is more than 5 microns to improve the body diode characteristics of the device; The gate dielectric layer includes a gate oxide layer; The gate conductive material layer includes a polysilicon gate. 9. The super-junction device according to any one of claims 1-8, characterized in that: the super-junction device comprises a super-junction MOSFET or a super-junction IGBT. 10. The super-junction device according to claim 9, characterized in that: the super-junction device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the super-junction device It is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type. 11. A method for manufacturing a super junction device, comprising the steps of: Step 1, forming a super junction structure in the semiconductor substrate, the super junction structure is formed by a plurality of columns of the first conductivity type and columns of the second conductivity type arranged alternately, and a super junction unit is formed by one column of the first conductivity type Composed of an adjacent column of the second conductivity type; Step 2, defining an active region on the semiconductor substrate; Step 3, forming a planar gate structure in the active region, each of the planar gate structures is formed on the top of each of the first conductivity type columns, and the planar gate structure is an integral structure; the planar gate structure is composed of a gate The dielectric layer and the gate conductive material layer are stacked; Step 4. Perform ion implantation of the second conductivity type under the self-alignment condition of the planar gate structure to form a second well region, and perform annealing treatment on the second well region. The role of the second well region in the annealing treatment lower lateral diffusion into the bottom region of the planar gate structure; The channel region is composed of the second well region covered by the planar gate structure, and the self-alignment structure between the second well region and the planar gate structure is used to improve the uniformity of the device. 12. The method for manufacturing a super junction device according to claim 11, characterized in that: after step 1 is completed, it further comprises the following step of forming the first well region: defining a formation region of the first well region by photolithography, and the first well region is located on top of the second conductivity type pillar in the active region; performing ion implantation of the second conductivity type to form the first well region; performing annealing on the first well region; in the lateral direction, there is a space between the annealed first well region and the side of the planar gate structure, the first well region and the planar gate structure or the first well region will extend to the bottom of the planar gate structure; The body region is vertically stacked by the first well region and the second well region, the junction depth of the first well region is greater than the junction depth of the second well region and the doping concentration of the first well region The doping concentration is lower than the doping concentration of the second well region, which is used to reduce the leakage current of the device. 13. The manufacturing method of a super junction device as claimed in claim 12, characterized in that: step 2 comprises the following sub-steps: forming a material layer of a dielectric protection ring on the surface of the semiconductor substrate; Photolithography defines the formation area of the active region; Etching the material layer of the dielectric protection ring to form the dielectric protection ring, the dielectric protection ring covers the transition region and the terminal region and opens the active region, and the area surrounded by the dielectric protection ring is the The active region, the transition region surrounds the active region, and the terminal region surrounds the transition region. 14. The method for manufacturing a super junction device according to claim 13, characterized in that: after step 2 is completed and before step 3 is performed, the step of forming an anti-JFET region is included as follows: Using the dielectric guard ring as a self-alignment condition, performing ion implantation of the first conductivity type to completely form the anti-JFET region on the surface of the active region; The anti-JFET region is used to increase the first conductivity type doping concentration of the first conductivity type doped region to reduce the JFET effect; The anti-JFET region is also used in the second conductivity type doping region to realize compensation for the second conductivity type doping impurities of the first P well in the surface area of the active region, so as to reduce the first P The influence of the well on the doping of the second conductivity type in the surface region of the active region makes the doping of the second conductivity type in the channel region determined by the second well region. 15. The manufacturing method of a super junction device as claimed in claim 14, characterized in that: after step 4, further comprising: performing the first conductivity type in the active region with the planar gate structure as a self-alignment condition The heavily doped ion implantation forms the source region. 16. The method for manufacturing a super junction device according to claim 14, wherein in the lateral direction, the first well region at least covers the center of the second conductivity type column and the first well region is located The width on both sides of the central position of the second conductivity type column is more than 0.2 microns; or, the width of the first well region covering the second conductivity type column is 1 micron to 2 microns or more. In the vertical direction, the depth of the first well region is 1-2 microns; or, the depth of the first well region is more than 2 microns. 17. The manufacturing method of a super junction device according to claim 16, characterized in that: when the depth of the first well region is 1 micron to 2 microns, the dielectric protection ring adopts thermal oxidation process formed The oxide layer is composed of a thermal oxide layer formed by a thermal oxidation process and a deposition medium layer formed by a deposition process. The thermal oxide layer of the dielectric protection ring consumes the surface of the semiconductor substrate. During the process of removing the dielectric protection ring of the source region, the surface region of the first well region is removed, and the doping concentration of the removed surface region of the first well region is higher than the doping concentration of the bottom remaining region, for Improve device consistency; When the depth of the first well region is more than 2 microns, the dielectric protection ring is composed of a thermal oxide layer formed by a thermal oxidation process or a thermal oxide layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process It is formed by stacking or adopting a deposition medium layer formed by a deposition process, and the deposition dielectric layer of the dielectric protection ring reduces the thermal process of the device, so as to reduce the specific on-resistance of the device. 18. The manufacturing method of a super junction device according to claim 16, characterized in that: a second conductivity type ring is formed in the transition region, and the first well region and the second conductivity type ring use the same The process is formed simultaneously. 19. The method for manufacturing a super junction device according to claim 11, wherein the semiconductor substrate comprises a silicon substrate; A first epitaxial layer doped with a first conductivity type is formed on the surface of the semiconductor substrate; The second conductivity type column is composed of a second conductivity type doped second epitaxial layer filled in the trench; The first conductivity type pillars consist of the first epitaxial layer between the second conductivity type pillars; The distance between the bottom surface of the second conductivity type pillar and the top surface of the semiconductor substrate is more than 5 microns to improve the body diode characteristics of the device; The gate dielectric layer includes a gate oxide layer; The gate conductive material layer includes a polysilicon gate. 20. The method for manufacturing a super junction device according to claim 14, characterized in that: before step 3, after the formation of the anti-JFET region, the anti-JFET region inverts the surface of the doped region of the second conductivity type Doped for the first conductivity type. 21. The method for manufacturing a super-junction device according to any one of claims 11-20, wherein the super-junction device comprises a super-junction MOSFET or a super-junction IGBT. 22. The manufacturing method of a super junction device according to claim 21, characterized in that: the super junction device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the The super junction device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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