CN111883583A - Shielded gate trench power device and method of making same - Google Patents
Shielded gate trench power device and method of making same Download PDFInfo
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- CN111883583A CN111883583A CN202010756193.9A CN202010756193A CN111883583A CN 111883583 A CN111883583 A CN 111883583A CN 202010756193 A CN202010756193 A CN 202010756193A CN 111883583 A CN111883583 A CN 111883583A
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- 239000004065 semiconductor Substances 0.000 claims description 34
- 238000000151 deposition Methods 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
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- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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Abstract
The invention discloses a power device of a shielded gate groove, wherein a gate structure of a device unit area comprises: filling polysilicon gates in isotropic etching areas on two sides of a top groove formed in the epitaxial layer; forming a side wall on the second side surface of the polysilicon gate; self-aligning the bottom groove and the side wall; a thermal oxidation layer is formed on the inner side surface of the bottom groove, and the forming area of the thermal oxidation layer is defined by self-alignment of the side wall so as to prevent the second side surface of the polysilicon gate from being oxidized; forming a deposited oxide layer on the inner side surface of the thermal oxide layer and the second side surface of the polysilicon gate, and filling active polysilicon in a middle groove surrounded by the deposited oxide layer; and forming a shielding dielectric layer by overlapping the thermal oxidation layer and the deposition oxidation layer. The invention also discloses a manufacturing method of the shielding grid groove power device. The invention can reduce the risk that the gate contact hole can not contact the polysilicon gate, and can improve the thickness of the shielding dielectric layer so as to improve the withstand voltage of the device and reduce the on-resistance of the device.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a Shielded Gate (SGT) gate trench power device. The invention also relates to a manufacturing method of the shielding grid groove power device.
Background
Fig. 1 is a schematic structural diagram of a conventional shielded gate trench power device; the gate structure of the device unit region of the existing shielded gate trench power device includes:
a top trench is formed on the first conductive type doped epitaxial layer 101, and the top trench is usually formed by first performing anisotropic etching according to a photolithography definition opening and then performing isotropic etching to enlarge an anisotropic etching region, so that the top trench is formed by overlapping the anisotropic etching region and the isotropic etching region.
Typically, the epitaxial layer 101 is formed on a semiconductor substrate.
And filling a polysilicon gate 109 in the isotropic etching areas at two sides of the top groove, wherein a gate dielectric layer 108 is arranged between the polysilicon gate 109 and the surface of the top groove. The material of the gate dielectric layer 108 includes an oxide layer.
The bottom trench is formed at the bottom of the top trench by continuing the anisotropic etch of the epitaxial layer 101 at the bottom of the top trench using the same lithographically defined opening of the top trench.
The field oxide layer 103 is formed by simultaneously thermally oxidizing the side surfaces of the epitaxial layer 101 and the polysilicon gate 109 on the inner surface of the bottom trench. The field oxide layer 103 serves as both a shield dielectric layer and an interpoly dielectric layer.
The source polysilicon 102 is formed in a middle trench surrounded by a middle region of a gate trench formed by overlapping a top trench and a bottom trench after the field oxide layer 103 is formed.
The power device of the shielding grid groove is a power MOSFET device of the shielding grid groove, and the structure of the device unit area further comprises:
a body region 104 doped with the second conductivity type formed on the surface of the epitaxial layer 101, the top trench passing through the body region 104, and the surface of the body region 104 laterally covered by the polysilicon gate 109 for forming a channel.
A source region 105 heavily doped with the first conductivity type is formed on the surface of the body region 104.
The semiconductor substrate is provided with a first conduction type heavily doped structure, and the drain region is formed on the back surface of the thinned semiconductor substrate.
A gate contact hole 110 passing through the interlayer film 106 is formed at the top of the polysilicon gate 109, and the top of the gate contact hole 110 connects a gate electrode formed of the front metal layer 107.
A source contact hole 111 is formed at the top of the source region 105, the source contact hole 111 also contacts the body region 104 through the source region 105, and the top of the source contact hole 111 connects to a source electrode composed of the front metal layer 107.
A source polysilicon contact hole 112 is formed at the top of the source polysilicon 102, the top of the source polysilicon contact hole 112 being connected to the source.
The drain region has a drain electrode formed on its back surface, the drain electrode being composed of a back metal layer 113.
Generally, the shielded gate trench power device is an N-type device, the first conductivity type is an N-type, and the second conductivity type is a P-type. Can also be: the shielding grid groove power device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.
The polysilicon gates 109 of the conventional shielded gate trench power device shown in fig. 1 are located on the left and right sides of the top of the source polysilicon 102, and are therefore also referred to as left and right shielded gate trench power devices. The gate structure of the left and right shield gate trench power device is formed by a top-down process, i.e., a top trench is formed first, and a gate dielectric layer 108 and a polysilicon gate 109 are formed on two side surfaces of the top trench, and then a bottom trench is formed, and a shield dielectric layer and source polysilicon 102 are formed. In the conventional top-down forming process, the shield dielectric layer and the interpoly dielectric layer are formed simultaneously by the same thermal oxidation process, i.e., both are formed of the field oxide layer 103.
Since the shield dielectric layer and the inter-polysilicon dielectric layer are formed together by a thermal oxidation process, in order to obtain a thicker shield dielectric layer, the growth of the field oxide layer 3 needs to be increased, but the polysilicon gate 109 is simultaneously oxidized and narrowed, so that the risk that the gate contact hole 110 cannot contact the polysilicon gate 109 is increased, as shown in a region corresponding to a mark 114 in fig. 1, the thickness of the shield dielectric layer of the structure is limited, and the breakdown capability of the device is also limited.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a power device of a shield gate groove, wherein a gate structure is provided with a top-down process structure, and the influence of the thickness of a shield dielectric layer on the width of a polysilicon gate can be eliminated, so that the risk that a gate contact hole cannot contact the polysilicon gate can be reduced, and meanwhile, the thickness of the shield dielectric layer can be increased, so that the withstand voltage of the device can be improved, and the on-resistance of the device can be reduced. Therefore, the invention also provides a manufacturing method of the shielded gate trench power device.
In order to solve the above technical problem, the gate structure of the device unit region of the shielded gate trench power device provided by the present invention comprises:
and forming a top groove on the epitaxial layer doped with the first conductivity type, wherein the top groove is formed by superposing an anisotropic etching region and an isotropic etching region.
And filling a polysilicon gate in isotropic etching areas on two sides of the top groove, wherein a gate dielectric layer is arranged between the polysilicon gate and the surface of the top groove.
And forming a side wall on a second side surface of the polysilicon gate close to one side in the middle of the top groove.
And the bottom groove is formed at the bottom of the top groove and is self-aligned with the side wall.
And forming a thermal oxidation layer on the inner side surface of the bottom groove, wherein the forming area of the thermal oxidation layer is defined by the self-alignment of the side wall so as to prevent the second side surface of the polysilicon gate from being oxidized.
A deposited oxide layer is formed on the inner side surface of the thermal oxide layer, and the deposited oxide layer is also formed on the second side surface of the polysilicon gate; the deposited oxide layer does not completely fill the top groove and the bottom groove and a middle groove is formed in the middle area of the top groove and the bottom groove; and filling active polysilicon in the middle groove.
And forming a shielding dielectric layer by overlapping the thermal oxidation layer and the deposition oxidation layer which are formed on the inner side surface of the bottom groove.
The side wall is reserved or removed, and when the side wall is reserved, the inter-polycrystalline silicon dielectric layer is formed by superposing the deposited oxide layer between the source polycrystalline silicon and the polycrystalline silicon gate and the side wall; and when the side wall is removed, the inter-polysilicon dielectric layer consists of the deposited oxide layer between the source polysilicon and the polysilicon gate.
In a further improvement, the epitaxial layer is formed on a semiconductor substrate.
In a further improvement, the semiconductor substrate comprises a silicon substrate, and the epitaxial layer is a silicon epitaxial layer.
The thermal oxidation layer is a thermal oxidation silicon layer, the deposition oxidation layer is a deposition silicon oxide layer, and the material layer of the side wall is a silicon nitride layer or a superposed layer of silicon oxide and silicon nitride.
In a further improvement, the material of the gate dielectric layer comprises an oxide layer.
In a further improvement, the shielded gate trench power device is a shielded gate trench power MOSFET device, and the structure of the device unit region further includes:
and the top groove penetrates through the body region, and the surface of the body region covered by the side surface of the polysilicon gate is used for forming a channel.
And a source region heavily doped with the first conductivity type is formed on the surface of the body region.
The semiconductor substrate is provided with a first conduction type heavily doped structure, and the drain region is formed on the back surface of the thinned semiconductor substrate.
In a further improvement, a gate contact hole is formed at the top of the polysilicon gate, the top of the gate contact hole connecting a gate formed from the front metal layer.
And the source contact hole is formed at the top of the source region, the source contact hole also penetrates through the source region to be in contact with the body region, and the top of the source contact hole is connected with a source electrode consisting of a front metal layer.
A source polysilicon contact hole is formed at the top of the source polysilicon, the top of the source polysilicon contact hole being connected to the source electrode.
And a drain electrode consisting of a back metal layer is formed on the back surface of the drain region.
The power device of the shielding grid groove is an N-type device, the first conduction type is an N type, and the second conduction type is a P type; or, the shielding grid groove power device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.
In order to solve the above technical problem, in the method for manufacturing a shielded gate trench power device according to the present invention, a gate structure of a device cell region is formed by the following steps:
step one, forming a top groove in the epitaxial layer of the first conduction type, and forming a gate dielectric layer and a polysilicon gate in the top groove.
The top groove is formed by superposing an anisotropic etching area and an isotropic etching area.
The polysilicon gate is formed in isotropic etching areas on two sides of the top groove, and the gate dielectric layer is arranged between the polysilicon gate and the surface of the top groove at intervals.
And secondly, forming a side wall on a second side surface of the polysilicon gate close to the middle side of the top groove by adopting a deposition and overall etching process.
And thirdly, etching the epitaxial layer at the bottom of the top groove by taking the side wall as a self-alignment boundary to form a bottom groove.
And fourthly, performing a thermal oxidation process to form a thermal oxidation layer, wherein the second side face of the polysilicon gate in the thermal oxidation process is protected by the side wall, so that the thermal oxidation layer is formed on the inner side surface of the bottom groove in a self-aligned mode.
Fifthly, carrying out CVD deposition to form a deposited oxide layer, wherein the deposited oxide layer is formed on the inner side surface of the thermal oxide layer and the second side surface of the polysilicon gate; the deposited oxide layer does not completely fill the top groove and the bottom groove and a middle groove is formed in the middle area of the top groove and the bottom groove; and the side wall is reserved or removed before the deposited oxide layer is formed.
And step six, filling source polysilicon in the middle groove.
And forming a shielding dielectric layer by overlapping the thermal oxidation layer and the deposition oxidation layer which are formed on the inner side surface of the bottom groove.
When the side wall is reserved, the inter-polysilicon dielectric layer is formed by overlapping the deposited oxide layer between the source polysilicon and the polysilicon gate with the side wall; and when the side wall is removed, the inter-polysilicon dielectric layer consists of the deposited oxide layer between the source polysilicon and the polysilicon gate.
In a further improvement, the step one comprises the following sub-steps:
and 11, forming a hard mask layer on the epitaxial layer and patterning the hard mask layer.
And step 12, carrying out anisotropic etching on the epitaxial layer by taking the hard mask layer as a mask to form the anisotropic etching area.
And step 13, performing isotropic etching to form an isotropic etching area on the periphery of the anisotropic etching area.
The openings of the anisotropic etching areas are the same as the pattern openings of the hard mask layer, and the isotropic etching areas on two sides of the anisotropic etching areas are covered by the hard mask layer.
And forming the top groove by overlapping the anisotropic etching area and the isotropic etching area.
And 14, forming the gate dielectric layer on the inner side surface of the top groove, forming a first polycrystalline silicon layer to fill the top groove part, and extending the first polycrystalline silicon layer to the surface of the hard mask layer outside the top groove.
And step 15, etching the first polysilicon layer to enable the first polysilicon layer to be only reserved in isotropic etching areas on two sides of the top groove and form the polysilicon gates, wherein the first polysilicon layer between the polysilicon gates and the first polysilicon layer on the surface of the hard mask layer outside the top groove are removed.
And the hard mask layer is reserved in the third step and the fourth step and is reserved or removed in the fifth step and the sixth step.
In a further improvement, the epitaxial layer is formed on a semiconductor substrate.
In a further improvement, the semiconductor substrate comprises a silicon substrate, and the epitaxial layer is a silicon epitaxial layer.
The thermal oxidation layer is a thermal oxidation silicon layer, the deposition oxidation layer is a deposition silicon oxide layer, and the material layer of the side wall is a silicon nitride layer or a superposed layer of silicon oxide and silicon nitride.
In a further improvement, the material of the gate dielectric layer comprises an oxide layer.
The further improvement is that the shielded gate trench power device is a shielded gate trench power MOSFET device, and the method further comprises the following front process steps:
forming a body region doped with a second conductive type on the surface of the epitaxial layer, wherein the top groove penetrates through the body region, and the surface of the body region covered by the side face of the polysilicon gate is used for forming a channel;
forming a source region heavily doped with a first conductive type on the surface of the body region of the device unit region;
the semiconductor substrate is provided with a first conductive type heavily doped structure, and after the front surface process is finished, the method further comprises the following back surface process:
thinning the semiconductor substrate;
forming a drain region by the thinned semiconductor substrate; or carrying out back doping on the thinned semiconductor substrate to form a first conduction type heavily doped drain region.
In a further improvement, the formation of the source region further comprises the following front process:
and forming an interlayer film, and forming a contact hole penetrating through the interlayer film, wherein the contact hole comprises a gate contact hole, a source contact hole and a source polysilicon contact hole.
And forming a front metal layer and patterning to form a grid electrode and a source electrode.
The gate contact hole is formed at the top of the polysilicon gate, and the top of the gate contact hole is connected with the gate.
The source contact hole is formed at the top of the source region, the source contact hole also contacts with the body region through the source region, and the top of the source contact hole is connected with the source electrode.
The source polysilicon contact hole is formed at the top of the source polysilicon, and the top of the source polysilicon contact hole is connected to the source electrode.
The power device of the shielding grid groove is an N-type device, the first conduction type is an N type, and the second conduction type is a P type; or, the shielding grid groove power device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.
The grid structure has a top-down process structure, namely a top groove and a polysilicon gate are formed firstly, and a bottom groove, a shielding dielectric layer and source polysilicon are formed later.
Because the thickness of the thermal oxidation layer of the shielding dielectric layer is not influenced by the width of the polysilicon gate, the thermal oxidation layer can be thickened; meanwhile, the inter-polysilicon dielectric layer is formed by adopting a deposited oxide layer, so that the shielding dielectric layer is a superposed structure of a thermal oxide layer and the deposited oxide layer.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a prior art shielded gate trench power device;
FIG. 2 is a schematic diagram of a shielded gate trench power device according to an embodiment of the present invention;
fig. 3A-3G are schematic device structure diagrams in steps of a method for manufacturing a shielded gate trench power device according to an embodiment of the invention.
Detailed Description
Fig. 2 is a schematic structural diagram of a shielded gate trench power device according to an embodiment of the present invention; the gate structure of the device unit region of the shielded gate trench power device comprises:
a top trench 202 is formed on the first conductive type doped epitaxial layer 1, the top trench 202 is formed by stacking an anisotropic etching region 202a and an isotropic etching region, and the structure of the top trench 202 is shown in fig. 3A.
In the embodiment of the invention, the epitaxial layer 1 is formed on a semiconductor substrate. Preferably, the semiconductor substrate includes a silicon substrate, and the epitaxial layer 1 is a silicon epitaxial layer 1.
And a polysilicon gate 9 is filled in the isotropic etching areas at two sides of the top groove 202, and a gate dielectric layer 8 is arranged between the polysilicon gate 9 and the surface of the top groove 202.
A sidewall 203 is formed on a second side surface of the polysilicon gate 9 close to the middle side of the top trench 202, and the structure of the sidewall 203 is shown in fig. 3C. The material layer of the side wall 203 is a silicon nitride layer or a superimposed layer of silicon oxide and silicon nitride.
A bottom trench 204 is formed at the bottom of the top trench 202 and is self-aligned to the sidewall 203, and the structure of the bottom trench 204 is shown in fig. 3D.
A thermal oxide layer 3a is formed on the inner side surface of the bottom trench 204, and a formation region of the thermal oxide layer 3a is defined by the sidewall 203 in a self-aligned manner to prevent the second side surface of the polysilicon gate 9 from being oxidized.
A deposited oxide layer 3b is formed on the inner side surface of the thermal oxide layer 3a, and the deposited oxide layer 3b is also formed on the second side surface of the polysilicon gate 9; the deposited oxide layer 3b does not completely fill the top trench 202 and the bottom trench 204 and forms a middle trench 205 in the middle area of the top trench 202 and the bottom trench 204; the structure of the middle trench 205 is shown in fig. 3F.
The intermediate trench 205 is filled with source polysilicon 2.
A shielding dielectric layer 3 is formed by overlapping the thermal oxide layer 3a and the deposited oxide layer 3b formed on the inner side surface of the bottom trench 204.
In the embodiment of the present invention, the sidewall spacers 203 are removed, and the inter-polysilicon dielectric layer is composed of the deposited oxide layer 3b between the source polysilicon 2 and the polysilicon gate 9. In other embodiments can also be: the side wall 203 is reserved, and the inter-polysilicon dielectric layer is formed by overlapping the deposited oxide layer 3b between the source polysilicon 2 and the polysilicon gate 9 with the side wall 203;
in the embodiment of the present invention, the thermal oxide layer 3a is a thermal oxide layer, the deposited oxide layer 3b is a deposited oxide layer, and the material layer of the sidewall 203 is silicon nitride or a stacked layer of silicon oxide and silicon nitride.
The material of the gate dielectric layer 8 comprises an oxide layer.
The power device of the shielding grid groove is a power MOSFET device of the shielding grid groove, and the structure of the device unit area further comprises:
a body region 4 doped with the second conductivity type and formed on the surface of the epitaxial layer 1, wherein the top trench 202 penetrates through the body region 4, and the surface of the body region 4 covered by the side face of the polysilicon gate 9 is used for forming a channel.
A source region 5 heavily doped with the first conductivity type is formed on the surface of the body region 4.
The semiconductor substrate is provided with a first conduction type heavily doped structure, and the drain region is formed on the back surface of the thinned semiconductor substrate.
A gate contact hole 10 is formed at the top of the polysilicon gate 9, and the top of the gate contact hole 10 is connected to the gate electrode formed by the front metal layer 7.
A source contact hole 11 is formed at the top of the source region 5, the source contact hole 11 also contacts the body region 4 through the source region 5, and the top of the source contact hole 11 is connected to a source electrode composed of the front metal layer 7.
A source polysilicon contact hole 12 is formed at the top of the source polysilicon 2, and the top of the source polysilicon contact hole 12 is connected to the source electrode.
The drain region has a drain electrode formed on its back surface, which is composed of a back metal layer 13.
In the embodiment of the invention, the shielding gate groove power device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type. In other embodiments can also be: the shielding grid groove power device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.
The gate structure in the embodiment of the invention has a top-down process structure, that is, the top trench 202 and the polysilicon gate 9 are formed first, and the bottom trench 204, the shielding dielectric layer 3 and the source polysilicon 2 are formed later, in the invention, a side wall 203 positioned on the second side surface of the polysilicon gate 9 is added before the bottom trench 204 is formed, so that not only can the self-alignment of the bottom trench 204 and the side wall 203 be realized, but also the forming region of the thermal oxidation layer 3a of the shielding dielectric layer 3 can be defined as the side surface of the bottom trench 204 by self-alignment, and the polysilicon gate 9 can be protected by the side wall 203 in the forming process of the thermal oxidation layer 3a, so that the influence of the thickness of the shielding dielectric layer 3 on the width of the polysilicon gate 9 can be eliminated, and the risk that the gate contact hole 10 can not contact the polysilicon gate 9 can be reduced.
Since the thickness of the thermal oxide layer 3a of the shielding dielectric layer 3 in the embodiment of the invention is not affected by the width of the polysilicon gate 9, the thermal oxide layer 3a can be made thick; meanwhile, the inter-polysilicon dielectric layer is formed by adopting the deposited oxide layer 3b, so that the shielding dielectric layer 3 is a stacked structure of the thermal oxide layer 3a and the deposited oxide layer 3b, and the embodiment of the invention can simultaneously improve the thickness of the shielding dielectric layer 3, thereby improving the withstand voltage of the device, reducing the on-resistance of the device and reducing the Cgs of the device.
Fig. 3A to fig. 3G are schematic diagrams of device structures in steps of a method for manufacturing a shielded gate trench power device according to an embodiment of the present invention; in the manufacturing method of the shielded gate trench power device of the embodiment of the invention, the gate structure of the device unit region is formed by adopting the following steps:
step one, as shown in fig. 3A, a top trench 202 is formed in the epitaxial layer 1 of the first conductivity type, and a gate dielectric layer 8 and a polysilicon gate 9 are formed in the top trench 202.
The top trench 202 is formed by stacking an anisotropic etched region 202a and an isotropic etched region.
The polysilicon gate 9 is formed in the isotropic etching area at both sides of the top trench 202, and the gate dielectric layer 8 is spaced between the polysilicon gate 9 and the surface of the top trench 202.
In the method of the embodiment of the invention, the first step comprises the following sub-steps:
The epitaxial layer 1 is formed on a semiconductor substrate. Preferably, the semiconductor substrate includes a silicon substrate, and the epitaxial layer 1 is a silicon epitaxial layer 1.
The openings of the anisotropic etching region 202a are the same as the pattern openings of the hard mask layer 201, and the isotropic etching regions on both sides of the anisotropic etching region 202a are covered by the hard mask layer 201.
The top trench 202 is formed by overlapping the anisotropic etching region 202a and the isotropic etching region.
Step 14, as shown in fig. 3B, forming the gate dielectric layer 8 on the inner side surface of the top trench 202, forming a first polysilicon layer 9a to partially fill the top trench 202, where the first polysilicon layer 9a further extends to the surface of the hard mask layer 201 outside the top trench 202.
In the method of the embodiment of the invention, the material of the gate dielectric layer 8 includes an oxide layer.
Step 15, as shown in fig. 3C, etching the first polysilicon layer 9a to make the first polysilicon layer 9a only remain in the isotropic etching areas at the two sides of the top trench 202 and constitute the polysilicon gate 9, and removing the first polysilicon layer 9a between the polysilicon gates 9 and the first polysilicon layer 9a on the surface of the hard mask layer 201 outside the top trench 202.
Step two, as shown in fig. 3C, depositing a material layer 203 a; then, as shown in fig. 3D, a sidewall 203 is formed on a second side surface of the polysilicon gate 9 close to the middle of the top trench 202 by performing a full etching process on the material layer 203 a. The material layer 203a of the sidewall spacer 203 is a silicon nitride layer or a stacked layer of silicon oxide and silicon nitride.
Step three, as shown in fig. 3D, the epitaxial layer 1 at the bottom of the top trench 202 is etched by using the sidewall spacers 203 as self-aligned boundaries to form a bottom trench 204.
Step four, as shown in fig. 3E, a thermal oxidation process is performed to form a thermal oxide layer 3a, in the thermal oxidation process, the second side surface of the polysilicon gate 9 is protected by the sidewall 203, so that the thermal oxide layer 3a is formed on the inner side surface of the bottom trench 204 in a self-aligned manner.
In the method of the embodiment of the present invention, the thermal oxide layer 3a is a thermal silicon oxide layer.
Step five, as shown in fig. 3F, removing the side wall 203 and the hard mask layer 201, and then performing CVD deposition to form a deposited oxide layer 3b, where the deposited oxide layer 3b is formed on the inner side surface of the thermal oxide layer 3a and on the second side surface of the polysilicon gate 9; the deposited oxide layer 3b does not completely fill the top trench 202 and the bottom trench 204 and forms a middle trench 205 in the middle area of the top trench 202 and the bottom trench 204. In other embodiments, the method can also be: the side walls 203 are reserved, and the hard mask layer 201 is reserved.
In the method of the embodiment of the invention, the deposited oxide layer 3b is a deposited silicon oxide layer.
The deposited oxide layer 3b also extends onto the surface of the epitaxial layer 1 outside the top trench 202.
Step six, as shown in fig. 3G, the intermediate trench 205 is filled with source polysilicon 2.
In the method of the embodiment of the invention, the source polysilicon 2 is formed by filling the polysilicon first and then etching the polysilicon back. Thereafter, the method further comprises the step of removing the deposited oxide layer 3b outside the top trench 202. In other embodiments, the deposited oxide layer 3b outside the top trench 202 can also remain and be part of the subsequent interlayer film 6. .
A shielding dielectric layer 3 is formed by overlapping the thermal oxide layer 3a and the deposited oxide layer 3b formed on the inner side surface of the bottom trench 204.
In the method of the embodiment of the invention, the inter-polysilicon dielectric layer is composed of the deposited oxide layer 3b between the source polysilicon 2 and the polysilicon gate 9. In other embodiments, when the sidewall spacers 203 are reserved, the inter-polysilicon dielectric layer is formed by overlapping the deposited oxide layer 3b between the source polysilicon 2 and the polysilicon gate 9 with the sidewall spacers 203.
The shielding grid groove power device is a shielding grid groove power MOSFET device, and further comprises the following front process steps:
forming a body region 4 doped with a second conductivity type on the surface of the epitaxial layer 1, wherein the top groove penetrates through the body region 4, and the surface of the body region 4 covered by the side face of the polysilicon gate 9 is used for forming a channel;
forming a source region 5 heavily doped with the first conductivity type on the surface of the body region 4 of the device unit region;
an interlayer film 6 is formed, and contact holes are formed through the interlayer film 6, including a gate contact hole 10, a source contact hole, and a source polysilicon contact hole 12.
A front metal layer 7 is formed and patterned to form a gate electrode and a source electrode.
The gate contact hole 10 is formed at the top of the polysilicon gate 9, and the top of the gate contact hole 10 is connected to the gate.
The source contact hole 11 is formed at the top of the source region 5, the source contact hole 11 also contacts the body region 4 through the source region 5, and the top of the source contact hole 11 is connected to the source electrode.
The source polysilicon contact hole 12 is formed at the top of the source polysilicon 2, and the top of the source polysilicon contact hole 12 is connected to the source electrode.
The semiconductor substrate is provided with a first conductive type heavily doped structure, and after the front surface process is finished, the method further comprises the following back surface process:
thinning the semiconductor substrate;
forming a drain region by the thinned semiconductor substrate; or carrying out back doping on the thinned semiconductor substrate to form a first conduction type heavily doped drain region.
And forming a back metal layer 13 on the back of the drain region and forming a drain electrode by the back metal layer 13.
In the method of the embodiment of the invention, the shielding grid groove power device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type. In other embodiments the method can also be: the shielding grid groove power device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A shielded gate trench power device, wherein the gate structure of the device unit region comprises:
forming a top groove on the epitaxial layer doped with the first conductive type, wherein the top groove is formed by superposing an anisotropic etching area and an isotropic etching area;
filling a polysilicon gate in isotropic etching areas on two sides of the top groove, wherein a gate dielectric layer is arranged between the polysilicon gate and the surface of the top groove;
forming a side wall on a second side surface of the polysilicon gate, which is close to one side of the middle of the top groove;
the bottom groove is formed at the bottom of the top groove and is self-aligned with the side wall;
a thermal oxide layer is formed on the inner side surface of the bottom groove, and a forming area of the thermal oxide layer is defined by the side wall in a self-alignment mode so as to prevent the second side surface of the polysilicon gate from being oxidized;
a deposited oxide layer is formed on the inner side surface of the thermal oxide layer, and the deposited oxide layer is also formed on the second side surface of the polysilicon gate; the deposited oxide layer does not completely fill the top groove and the bottom groove and a middle groove is formed in the middle area of the top groove and the bottom groove; filling active polysilicon in the middle groove;
forming a shielding dielectric layer by overlapping the thermal oxidation layer and the deposition oxidation layer formed on the inner side surface of the bottom groove;
the side wall is reserved or removed, and when the side wall is reserved, the inter-polycrystalline silicon dielectric layer is formed by superposing the deposited oxide layer between the source polycrystalline silicon and the polycrystalline silicon gate and the side wall; and when the side wall is removed, the inter-polysilicon dielectric layer consists of the deposited oxide layer between the source polysilicon and the polysilicon gate.
2. The shielded gate trench power device of claim 1 wherein: the epitaxial layer is formed on a semiconductor substrate.
3. The shielded gate trench power device of claim 2 wherein: the semiconductor substrate comprises a silicon substrate, and the epitaxial layer is a silicon epitaxial layer;
the thermal oxidation layer is a thermal oxidation silicon layer, the deposition oxidation layer is a deposition silicon oxide layer, and the material layer of the side wall is a silicon nitride layer or a superposed layer of silicon oxide and silicon nitride.
4. The shielded gate trench power device of claim 3 wherein: the material of the gate dielectric layer comprises an oxide layer.
5. The shielded gate trench power device of claim 2 wherein: the power device of the shielding grid groove is a power MOSFET device of the shielding grid groove, and the structure of the device unit area further comprises:
the body region is formed on the surface of the epitaxial layer and doped with the second conduction type, the top groove penetrates through the body region, and the surface of the body region covered by the side face of the polysilicon gate is used for forming a channel;
forming a source region heavily doped with a first conductive type on the surface of the body region;
the semiconductor substrate is provided with a first conduction type heavily doped structure, and the drain region is formed on the back surface of the thinned semiconductor substrate.
6. The shielded gate trench power device of claim 5 wherein: a gate contact hole is formed at the top of the polysilicon gate, and the top of the gate contact hole is connected with a gate formed by a front metal layer;
a source contact hole is formed at the top of the source region, the source contact hole also penetrates through the source region to be in contact with the body region, and the top of the source contact hole is connected with a source electrode consisting of a front metal layer;
a source polysilicon contact hole is formed at the top of the source polysilicon, and the top of the source polysilicon contact hole is connected to the source electrode;
and a drain electrode consisting of a back metal layer is formed on the back surface of the drain region.
7. The shielded gate trench power device of any of claims 1-6 wherein: the shielding grid groove power device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type; or, the shielding grid groove power device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.
8. A manufacturing method of a shielded gate trench power device is characterized in that a gate structure of a device unit area is formed by the following steps:
forming a top groove in an epitaxial layer of a first conduction type, and forming a gate dielectric layer and a polysilicon gate in the top groove;
the top groove is formed by superposing an anisotropic etching area and an isotropic etching area;
the polysilicon gate is formed in isotropic etching areas on two sides of the top groove, and the gate dielectric layer is arranged between the polysilicon gate and the surface of the top groove at intervals;
secondly, forming a side wall on a second side face, close to the middle side of the top groove, of the polysilicon gate by adopting a deposition and overall etching process;
etching the epitaxial layer at the bottom of the top groove by taking the side wall as a self-alignment boundary to form a bottom groove;
performing a thermal oxidation process to form a thermal oxide layer, wherein the second side face of the polysilicon gate in the thermal oxidation process is protected by the side wall so that the thermal oxide layer is formed on the inner side surface of the bottom groove in a self-aligned manner;
fifthly, carrying out CVD deposition to form a deposited oxide layer, wherein the deposited oxide layer is formed on the inner side surface of the thermal oxide layer and the second side surface of the polysilicon gate; the deposited oxide layer does not completely fill the top groove and the bottom groove and a middle groove is formed in the middle area of the top groove and the bottom groove; the side wall is reserved or removed before the deposited oxide layer is formed;
sixthly, filling source polycrystalline silicon in the middle groove;
forming a shielding dielectric layer by overlapping the thermal oxidation layer and the deposition oxidation layer formed on the inner side surface of the bottom groove;
when the side wall is reserved, the inter-polysilicon dielectric layer is formed by overlapping the deposited oxide layer between the source polysilicon and the polysilicon gate with the side wall; and when the side wall is removed, the inter-polysilicon dielectric layer consists of the deposited oxide layer between the source polysilicon and the polysilicon gate.
9. The method of manufacturing a shielded gate trench power device of claim 1 wherein step one comprises the sub-steps of:
step 11, forming a hard mask layer on the epitaxial layer and patterning the hard mask layer;
step 12, performing anisotropic etching on the epitaxial layer by taking the hard mask layer as a mask to form an anisotropic etching area;
step 13, performing isotropic etching to form an isotropic etching area on the periphery of the anisotropic etching area;
the openings of the anisotropic etching areas are the same as the pattern openings of the hard mask layer, and the isotropic etching areas positioned on two sides of the anisotropic etching areas are covered by the hard mask layer;
the top groove is formed by overlapping the anisotropic etching area and the isotropic etching area;
step 14, forming the gate dielectric layer on the inner side surface of the top trench, forming a first polysilicon layer to partially fill the top trench, wherein the first polysilicon layer also extends to the surface of the hard mask layer outside the top trench;
step 15, etching the first polysilicon layer to enable the first polysilicon layer to be only reserved in isotropic etching areas on two sides of the top groove and to form the polysilicon gate, wherein the first polysilicon layer between the polysilicon gates and the first polysilicon layer on the surface of the hard mask layer outside the top groove are removed;
and the hard mask layer is reserved in the third step and the fourth step and is reserved or removed in the fifth step and the sixth step.
10. The method of manufacturing a shielded gate trench power device of claim 8 wherein: the epitaxial layer is formed on a semiconductor substrate.
11. The method of manufacturing a shielded gate trench power device of claim 10 wherein: the semiconductor substrate comprises a silicon substrate, and the epitaxial layer is a silicon epitaxial layer;
the thermal oxidation layer is a thermal oxidation silicon layer, the deposition oxidation layer is a deposition silicon oxide layer, and the material layer of the side wall is a silicon nitride layer or a superposed layer of silicon oxide and silicon nitride.
12. The method of manufacturing a shielded gate trench power device of claim 11 wherein: the material of the gate dielectric layer comprises an oxide layer.
13. The method of manufacturing a shielded gate trench power device of claim 11 wherein: the shielding grid groove power device is a shielding grid groove power MOSFET device, and further comprises the following front process steps:
forming a body region doped with a second conductive type on the surface of the epitaxial layer, wherein the top groove penetrates through the body region, and the surface of the body region covered by the side face of the polysilicon gate is used for forming a channel;
forming a source region heavily doped with a first conductive type on the surface of the body region of the device unit region;
the semiconductor substrate is provided with a first conductive type heavily doped structure, and after the front surface process is finished, the method further comprises the following back surface process:
thinning the semiconductor substrate;
forming a drain region by the thinned semiconductor substrate; or carrying out back doping on the thinned semiconductor substrate to form a first conduction type heavily doped drain region.
14. The method of manufacturing a shielded gate trench power device of claim 13 wherein: the method also comprises the following front process after the source region is formed:
forming an interlayer film, and forming a contact hole penetrating through the interlayer film, wherein the contact hole comprises a gate contact hole, a source contact hole and a source polysilicon contact hole;
forming a front metal layer and patterning to form a grid and a source;
the gate contact hole is formed at the top of the polysilicon gate, and the top of the gate contact hole is connected with the gate;
the source contact hole is formed at the top of the source region, the source contact hole is also contacted with the body region through the source region, and the top of the source contact hole is connected with the source electrode;
the source polysilicon contact hole is formed at the top of the source polysilicon, and the top of the source polysilicon contact hole is connected to the source electrode.
15. The method of fabricating a shielded gate trench power device as claimed in any of claims 8-14 wherein: the shielding grid groove power device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type; or, the shielding grid groove power device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.
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