KR20030057940A - Method for manufacturing a selective salicide layer of planar cell - Google Patents
Method for manufacturing a selective salicide layer of planar cell Download PDFInfo
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- KR20030057940A KR20030057940A KR1020010088046A KR20010088046A KR20030057940A KR 20030057940 A KR20030057940 A KR 20030057940A KR 1020010088046 A KR1020010088046 A KR 1020010088046A KR 20010088046 A KR20010088046 A KR 20010088046A KR 20030057940 A KR20030057940 A KR 20030057940A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000003990 capacitor Substances 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 31
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 31
- 239000012535 impurity Substances 0.000 claims description 27
- 239000010410 layer Substances 0.000 claims description 13
- 239000011229 interlayer Substances 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims 1
- 239000012528 membrane Substances 0.000 claims 1
- 239000002019 doping agent Substances 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 3
- 239000012212 insulator Substances 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 4
- 238000000137 annealing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 플래너 셀(planar cell)의 제조 방법에 관한 것으로서, 특히 플래너 셀의 선택적 살리사이드막 제조 방법에 관한 것이다.The present invention relates to a method for producing a planar cell, and more particularly, to a method for producing a selective salicide film of a planar cell.
반도체 메모리장치로서 DRAM(Dynamic Random Access Memory)은 기본적으로 하나의 트랜지스터와 하나의 커패시터로 구성된다.As a semiconductor memory device, a DRAM (Dynamic Random Access Memory) basically consists of one transistor and one capacitor.
그런데 DRAM의 제품에서는, 반도체 기판에 주입된 불순물층을 스토리지 전극으로 사용하고, 그 전극 위에 전극간 절연체막과 도전막을 순차적으로 형성하고 이때의 도전막을 플레이트 전극으로 삼아 플래너 셀 구조의 커패시터를 형성하는 경우가 있다.However, in the DRAM product, an impurity layer injected into a semiconductor substrate is used as a storage electrode, and an inter-electrode insulator film and a conductive film are sequentially formed on the electrode, and a capacitor having a planar cell structure is formed using the conductive film as a plate electrode. There is a case.
도 1a 내지 도 1f는 종래기술에 의한 플래너 셀의 살리사이드막 제조 방법을 설명하기 위한 공정 순서도로서, 이를 참조하여 종래 제조 방법은 다음과 같다.1A to 1F are flowcharts illustrating a method of manufacturing a salicide film of a planar cell according to the prior art, and with reference thereto, the conventional manufacturing method is as follows.
도 1a에 도시된 바와 같이, 반도체 기판(10)상에 소자 분리막(미도시함)을 형성하고 반도체 기판(10) 상부에 전극간 절연체막(12)을 형성한다. 그리고 전극간 절연체막(12) 상부에 도전막으로서 도프트 폴리실리콘을 증착하고 이를 패터닝하여 플래너 셀의 커패시터가 형성될 영역과 플래너 셀의 트랜지스터가 형성될 영역에 각각 플레이트전극(14b) 및 게이트전극(14a)을 형성한다. 이때, 플레이트전극(14b) 및 게이트전극(14a) 하부에 전극간 절연체막(12)도 패터닝된다. 그런 다음, 저농도 불순물 이온주입을 실시하여 게이트전극(14a)에 의해 양쪽으로 분리된 반도체 기판(10) 표면 근방에 저농도 불순물 영역(16)을 형성한다. 이때, 저농도 불순물 이온주입은 p-형 또는 n-형 불순물로 이온주입한다.As shown in FIG. 1A, an isolation layer (not shown) is formed on the semiconductor substrate 10, and an inter-electrode insulator film 12 is formed on the semiconductor substrate 10. Then, a dopant polysilicon is deposited as a conductive layer on the inter-electrode insulator film 12 and patterned to form a plate electrode 14b and a gate electrode in the region where the capacitor of the planar cell is formed and the region where the transistor of the planar cell is to be formed, respectively. (14a) is formed. At this time, the inter-electrode insulator film 12 is also patterned under the plate electrode 14b and the gate electrode 14a. Thereafter, low concentration impurity ion implantation is performed to form the low concentration impurity region 16 near the surface of the semiconductor substrate 10 separated by both sides by the gate electrode 14a. At this time, the low concentration impurity ion implantation is implanted with p-type or n-type impurity.
이어서 도 1b에 도시된 바와 같이, 반도체 기판(10) 전면에 절연막(18)을 형성한다.Subsequently, as shown in FIG. 1B, an insulating film 18 is formed over the entire surface of the semiconductor substrate 10.
그런 다음 도 1c에 도시된 바와 같이, 절연막(18)을 건식 식각해서 플레이트전극(14b) 및 게이트전극(14a)의 양쪽 측벽에 각각 스페이서(18a)를 형성한다.Then, as illustrated in FIG. 1C, the insulating film 18 is dry etched to form spacers 18a on both sidewalls of the plate electrode 14b and the gate electrode 14a, respectively.
계속해서 도 1d에 도시된 바와 같이, 고농도 불순물 이온주입을 실시하여 게이트전극(14a) 및 스페이서(18a)에 의해 양쪽으로 분리된 반도체 기판(10)내에 고농도 불순물 영역(20, 21)을 형성한다. 이때, 고농도 불순물 이온주입은 p+형 또는 n+형 불순물로 이온주입하는데, 여기서는 고농도 불순물 주입 영역인 20은 소오스 접합 영역이며 21은 드레인 접합 영역이 된다.Subsequently, as shown in FIG. 1D, high concentration impurity ion implantation is performed to form high concentration impurity regions 20 and 21 in the semiconductor substrate 10 separated by both the gate electrode 14a and the spacer 18a. . At this time, the high concentration impurity ion implantation is ion implanted with p + or n + type impurity, where 20 is a source junction region and 21 is a drain junction region.
이어서 도 1e에 도시된 바와 같이, 반도체 기판 전면에 실리사이드용 금속을 증착하고 어닐 공정을 실시하여 플레이트전극(14b) 및 게이트전극(14a) 상부면과 드레인/소오스 접합 영역(21, 20) 표면에 각각 실리사이드막(22)을 형성한다. 이때, 플레이트전극(14b) 및 게이트전극(14a)과 드레인/소오스 접합 영역(21, 20)의 표면에 실리사이드막(22)은 서로 분리되어 형성되는데, 그 이유는 스페이서(18a)부분에서 실리사이드막이 생성되지 않기 때문이다. 이렇게 게이트전극(14a)과 드레인/소오스 접합 영역(21, 20)에 실리사이드막(22)을 동시에 형성하는 공정을 살리사이드막(salicide layer) 제조 공정이라 일컫는다.Subsequently, as shown in FIG. 1E, a silicide metal is deposited on the entire surface of the semiconductor substrate, and annealing is performed on the upper surface of the plate electrode 14b and the gate electrode 14a and the drain / source junction regions 21 and 20. The silicide film 22 is formed, respectively. At this time, the silicide film 22 is formed on the surface of the plate electrode 14b and the gate electrode 14a and the drain / source junction regions 21 and 20 separately from each other, because the silicide film is formed at the spacer 18a. Because it is not created. The process of simultaneously forming the silicide film 22 in the gate electrode 14a and the drain / source junction regions 21 and 20 is called a salicide layer manufacturing process.
그리고나서 도 1f에 도시된 바와 같이, 반도체 기판(10)의 전면에 층간 절연막(24)을 형성하고 층간 절연막(24)에 콘택홀을 형성하고 콘택홀에 도전막을 매립하고 이를 패터닝하여 소오스 접합 영역(20)의 실리사이드막(22)에 수직으로 연결된 비트라인(28)을 형성한다. 이때, 도면 부호 26은 콘택홀에 매립된 도전막으로 이루어진 콘택 전극을 나타낸 것이다.Then, as shown in FIG. 1F, an interlayer insulating film 24 is formed on the entire surface of the semiconductor substrate 10, a contact hole is formed in the interlayer insulating film 24, a conductive film is buried in the contact hole, and the source junction region is patterned. The bit line 28 connected to the silicide film 22 of the vertical direction 20 is formed. In this case, reference numeral 26 denotes a contact electrode made of a conductive film embedded in the contact hole.
상술한 바와 같이, 종래기술은 플래너 셀에 있어서 커패시터 및 트랜지스터에 살리사이드 공정을 실시하여 플레이트전극(14b) 및 게이트전극(14a) 상부면과 드레인/소오스 접합 영역(21, 20) 표면에 모두 실리사이드막(22)을 형성하였다. 이로 인해, 트랜지스터의 표면 저항은 낮아져 구동 특성이 빨라지나, 커패시터와 트랜지스터가 연결된 드레인 접합 영역에서는 오히려 표면 저항을 낮춘 실리사이드막으로 인해 전류 누설이 발생하는 문제점이 있었다.As described above, the prior art performs a salicide process on the capacitor and the transistor in the planar cell, so that both the top surface of the plate electrode 14b and the gate electrode 14a and the silicide surfaces of the drain / source junction regions 21 and 20 are formed. The film 22 was formed. As a result, the surface resistance of the transistor is lowered to increase driving characteristics, but current leakage occurs due to the silicide film having a lower surface resistance in the drain junction region where the capacitor and the transistor are connected.
이에 드레인 접합 영역에 블록킹 마스크를 사용하여 이 부분에 실리사이드막이 형성되는 것을 방지하였으나, 반도체 소자의 고집적화에 따라 플래너 셀의 플레이트전극(14b) 및 게이트전극(14a) 사이에 있는 드레인 접합 영역의 크기가 축소되어 포토리소그래피 공정시 블록킹 마스크를 적용하는데 한계가 있었다.As a blocking mask is used in the drain junction region to prevent the silicide film from being formed, the size of the drain junction region between the plate electrode 14b and the gate electrode 14a of the planar cell is increased due to the high integration of semiconductor devices. There was a limitation in applying the blocking mask in the photolithography process.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 커패시터와 트랜지스터가 연결된 드레인 접합 영역에 절연막으로 블록킹하여 이후 살리사이드 공정시 드레인 접합 영역에만 선택적으로 실리사이드막이 형성되지 않도록 함으로써 커패시터 영역의 전류 누설을 방지할 수 있으면서 트랜지스터의 구동 특성은 향상시킬 수 있는 플래너 셀의 선택적 살리사이드막 제조 방법을 제공하는데 있다.An object of the present invention is to solve the problems of the prior art as described above by blocking the insulating film in the drain junction region where the capacitor and the transistor is connected so that the silicide film is not selectively formed only in the drain junction region during the later salicide process current of the capacitor region The present invention provides a method for producing a selective salicide film of a planar cell which can prevent leakage and improve driving characteristics of a transistor.
도 1a 내지 도 1f는 종래기술에 의한 플래너 셀의 살리사이드막 제조 방법을 설명하기 위한 공정 순서도,1A to 1F are process flowcharts for explaining a salicide film production method of a planar cell according to the prior art;
도 2는 본 발명에 따라 선택적 살리사이드막을 갖는 플래너 셀의 레이아웃도,2 is a layout diagram of a planar cell having a selective salicide film according to the present invention;
도 3a 내지 도 3f는 본 발명에 따른 플래너 셀의 선택적 살리사이드막 제조 방법을 설명하기 위한 공정 순서도.3A to 3F are process flowcharts for explaining a method for producing a selective salicide film of a planar cell according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
100 : 반도체 기판 102 : 전극간 절연체막100 semiconductor substrate 102 inter-electrode insulator film
104a : 게이트전극 104b : 플레이트전극104a: gate electrode 104b: plate electrode
106 : 저농도 불순물 영역 108 : 절연막106: low concentration impurity region 108: insulating film
108a : 스페이서 108b : 충진막108a: spacer 108b: filling film
110 : 소오스 접합 영역 112 : 트랜지스터용 실리사이드막110 source junction region 112 silicide film for transistor
114 : 커패시터용 실리사이드막 116 : 층간 절연막114: silicide film for capacitor 116: interlayer insulating film
118 : 콘택 전극 120 : 비트라인118 contact electrode 120 bit line
상기 목적을 달성하기 위하여 본 발명은 플래너 셀 소자의 제조 방법에 있어서, 반도체 기판 상부에서 플래너 셀의 커패시터가 형성될 영역과 플래너 셀의 트랜지스터가 형성될 영역에 각각 플레이트전극 및 게이트전극을 형성하는 단계와, 반도체 기판 전면에 플레이트전극 및 게이트전극 사이를 완전히 덮도록 절연막을 두껍게 증착하고 이를 식각해서 플레이트전극 및 게이트전극의 외곽 측벽에 각각 스페이서를 형성함과 동시에 플레이트전극과 게이트전극 사이 공간에 충진막을 형성하는 단계와, 반도체 기판의 플래너 셀의 트랜지스터가 형성될 영역에 불순물을 이온주입하여 소오스 접합 영역을 형성하는 단계와, 플레이트전극 및 게이트전극 상부면과 소오스 접합 영역 표면에 실리사이드막을 형성하는 단계와, 반도체 기판의 전면에 층간 절연막을 형성하고 층간 절연막의 콘택홀을 통해 소오스 접합 영역의 실리사이드막에 수직으로 연결된 비트라인을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method of manufacturing a planar cell element, the method comprising: forming a plate electrode and a gate electrode in a region where a capacitor of the planar cell is formed and a region where a transistor of the planar cell is formed on the semiconductor substrate And depositing an insulating film thickly covering the entire surface of the semiconductor substrate between the plate electrode and the gate electrode, and etching the same to form spacers on the outer sidewalls of the plate electrode and the gate electrode, and filling a space between the plate electrode and the gate electrode. Forming a source junction region by implanting impurities into a region where a transistor of the planar cell of the semiconductor substrate is to be formed, forming a source junction region, and forming a silicide film on the upper surface of the plate electrode and the gate electrode and on the source junction region; , Interlayer on the front of the semiconductor substrate And forming a film made by using a contact hole of the interlayer insulating film and forming a bit line connected to the normal to the silicide film in the source junction region.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따라 선택적 살리사이드막을 갖는 플래너 셀의 레이아웃도이다. 도 2를 참조하면, 본 발명의 플래너 셀은 게이트전극 라인(1)을 사이에 두고 소오스 접합 영역인 A 부분에는 실리사이드막이 형성되는 반면에, 드레인 접합 영역인 B 부분에는 실리사이드막이 형성되지 않는다. 이때, 도면 부호 2는 커패시터 영역이며 3은 활성 영역이며 4는 비트라인 콘택이다.2 is a layout diagram of a planar cell having a selective salicide film according to the present invention. Referring to FIG. 2, in the planar cell of the present invention, a silicide film is formed in the A portion of the source junction region with the gate electrode line 1 interposed therebetween, while the silicide film is not formed in the B portion of the drain junction region. 2 is a capacitor region, 3 is an active region, and 4 is a bit line contact.
도 3a 내지 도 3f는 본 발명에 따른 플래너 셀의 선택적 살리사이드막 제조 방법을 설명하기 위한 공정 순서도로서, 이를 참조하면 본 발명의 제조 방법은 다음과 같다.3A to 3F are flowcharts illustrating a method for manufacturing a selective salicide film of a planar cell according to the present invention. Referring to this, the manufacturing method of the present invention is as follows.
우선 도 3a에 도시된 바와 같이, 반도체 기판(100)상에 소자 분리막(미도시함)을 형성하고 반도체 기판(100) 상부에 전극간 절연체막(102)을 형성한다. 그리고 전극간 절연체막(102) 상부에 도전막으로서 도프트 폴리실리콘을 증착하고 이를 패터닝하여 플래너 셀의 커패시터가 형성될 영역과 플래너 셀의 트랜지스터가 형성될 영역에 각각 플레이트전극(104b) 및 게이트전극(104a)을 형성한다. 이때, 플레이트전극(104b) 및 게이트전극(104a) 하부에 전극간 절연체막(102)도 패터닝된다. 그런 다음, 저농도 불순물 이온주입을 실시하여 게이트전극(104a)에 의해 양쪽으로 분리된 반도체 기판(10) 표면 근방에 저농도 불순물 영역(106)을 형성한다. 이때, 저농도 불순물 이온주입은 p-형 또는 n-형 불순물로 이온주입한다.First, as shown in FIG. 3A, an isolation layer (not shown) is formed on the semiconductor substrate 100, and an inter-electrode insulator layer 102 is formed on the semiconductor substrate 100. Then, a dopant polysilicon is deposited as a conductive layer on the inter-electrode insulator film 102 and patterned to form a plate electrode 104b and a gate electrode in the region where the capacitor of the planar cell is formed and the region where the transistor of the planar cell is to be formed, respectively. Form 104a. At this time, the inter-electrode insulator film 102 is also patterned under the plate electrode 104b and the gate electrode 104a. Then, low concentration impurity ions are implanted to form the low concentration impurity region 106 near the surface of the semiconductor substrate 10 separated by both of the gate electrodes 104a. At this time, the low concentration impurity ion implantation is implanted with p-type or n-type impurity.
본 발명에서는 플레이트전극(104b) 및 게이트전극(104a) 사이의 반도체 기판 내에 있는 저농도 불순물 영역(106)이 드레인 접합 영역으로 사용된다.In the present invention, the low concentration impurity region 106 in the semiconductor substrate between the plate electrode 104b and the gate electrode 104a is used as the drain junction region.
이어서 도 3b에 도시된 바와 같이, 반도체 기판(100) 전면에 절연막(108)을형성한다. 이때, 절연막(108)은 플레이트전극(104b) 및 게이트전극(104a) 사이를 완전히 덮도록 두껍게 증착해야만 한다.Subsequently, as shown in FIG. 3B, an insulating film 108 is formed on the entire surface of the semiconductor substrate 100. At this time, the insulating film 108 should be thickly deposited so as to completely cover the plate electrode 104b and the gate electrode 104a.
그리고 도 3c에 도시된 바와 같이, 절연막(108)을 건식 식각하여 플레이트전극(104b) 및 게이트전극(104a)의 외곽 측벽에 각각 스페이서(108a)를 형성함과 동시에 플레이트전극(104b) 및 게이트전극(104a)사이 공간에 충진막(108b)을 형성한다. 이때, 충진막(108b)은 이후 드레인 접합 영역에 실리사이드막이 형성되지 않도록 블록킹 역할을 한다.As shown in FIG. 3C, the insulating layer 108 is dry-etched to form spacers 108a on the outer sidewalls of the plate electrode 104b and the gate electrode 104a, and at the same time, the plate electrode 104b and the gate electrode are formed. The filling film 108b is formed in the space between the 104a. At this time, the filling film 108b serves as a blocking function so that the silicide film is not formed in the drain junction region.
그 다음 도 3d에 도시된 바와 같이, 고농도 불순물 이온주입을 실시하여 게이트전극(104a) 및 스페이서(108a)에 의해 오픈된 반도체 기판(10)내에 고농도 불순물 영역(110)을 형성한다. 이때, 고농도 불순물 이온주입은 p+형 또는 n+형 불순물로 이온주입하는데, 본 발명에서 고농도 불순물 주입 영역인 110은 소오스 접합 영역이 된다.3D, high concentration impurity ions are implanted to form a high concentration impurity region 110 in the semiconductor substrate 10 opened by the gate electrode 104a and the spacer 108a. In this case, the high concentration impurity ion implantation is implanted with p + or n + type impurity. In the present invention, the high concentration impurity implantation region 110 becomes a source junction region.
이어서 도 3e에 도시된 바와 같이, 반도체 기판 전면에 실리사이드용 금속을 증착하고 어닐 공정을 실시하여 플레이트전극(104b) 및 게이트전극(104a) 상부면과소오스 접합 영역(110) 표면에 각각 실리사이드막(112)을 형성한다. 이때, 플레이트전극(104b) 및 게이트전극(104a)과 소오스 접합 영역(110)의 표면에는 실리사이드 반응이 일어나지 않는 스페이서(18a)에 의해 각각의 실리사이드막(112)이 서로 분리되어 형성된다. 그러므로, 본 발명은 이렇게 게이트전극(104a)과 소오스 접합 영역(110)에 실리사이드막(112)을 동시에 형성하는 살리사이드 공정시 플레이트전극(104b) 및 게이트전극(104a)사이에 있는 충진막(108b)에 의해 드레인 접합 영역(106)에서는 실리사이드막이 형성되지 않고 플레이트전극(104b) 및 게이트전극 (104a)과 소오스 접합 영역(110)의 표면에만 선택적으로 실리사이드막(112)이 형성된다.Subsequently, as shown in FIG. 3E, a silicide metal is deposited on the entire surface of the semiconductor substrate, and annealing is performed to form a silicide layer on the upper surface of the plate electrode 104b and the gate electrode 104a and the surface of the source junction region 110, respectively. 112). At this time, the silicide film 112 is formed on the surface of the plate electrode 104b and the gate electrode 104a and the source junction region 110 by being separated from each other by a spacer 18a in which no silicide reaction occurs. Therefore, in the salicide process of simultaneously forming the silicide film 112 in the gate electrode 104a and the source junction region 110, the present invention fills the film 108b between the plate electrode 104b and the gate electrode 104a. ), The silicide film 112 is not formed in the drain junction region 106, and the silicide film 112 is selectively formed only on the surface of the plate electrode 104b and the gate electrode 104a and the source junction region 110.
그리고나서 도 3f에 도시된 바와 같이, 반도체 기판(100)의 전면에 층간 절연막(114)을 형성하고 층간 절연막(114)에 콘택홀을 형성하고 콘택홀에 도전막을 매립하고 이를 패터닝하여 소오스 접합 영역(110)의 실리사이드막(112)에 수직으로 연결된 콘택 전극(116) 및 비트라인(118)을 형성한다.3F, an interlayer insulating film 114 is formed on the entire surface of the semiconductor substrate 100, a contact hole is formed in the interlayer insulating film 114, a conductive film is buried in the contact hole, and the source junction region is patterned. The contact electrode 116 and the bit line 118 vertically connected to the silicide layer 112 of (110) are formed.
상기한 바와 같이, 본 발명의 제조 방법에 따르면 커패시터와 트랜지스터가 연결된 드레인 접합 영역에 절연막으로 블록킹하여 이후 살리사이드 공정시 드레인 접합 영역에만 선택적으로 실리사이드막이 형성되지 않고 플레이트전극 및 게이트전극과 소오스 접합 영역의 표면에만 선택적으로 실리사이드막이 형성된다.As described above, according to the manufacturing method of the present invention, the insulating film is blocked in the drain junction region where the capacitor and the transistor are connected to each other so that the silicide layer is not selectively formed only in the drain junction region during the subsequent salicide process. The silicide film is selectively formed only on the surface of the film.
따라서, 본 발명은 트랜지스터의 게이트 전극 및 소오스 접합에는 표면 저항을 낮추는 실리사이드막이 형성되어 구동 특성이 향상되면서 커패시터와 트랜지스터가 서로 연결되는 드레인 접합 영역에는 실리사이드막이 형성되지 않기 때문에 커패시터 영역의 전류 누설을 방지할 수 있다.Accordingly, the present invention prevents current leakage in the capacitor region because a silicide film for lowering the surface resistance is formed at the gate electrode and the source junction of the transistor to improve driving characteristics, and thus no silicide film is formed at the drain junction region where the capacitor and the transistor are connected to each other. can do.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
Claims (5)
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