CN113078066A - Manufacturing method of split gate power MOSFET device - Google Patents

Manufacturing method of split gate power MOSFET device Download PDF

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CN113078066A
CN113078066A CN202110342787.XA CN202110342787A CN113078066A CN 113078066 A CN113078066 A CN 113078066A CN 202110342787 A CN202110342787 A CN 202110342787A CN 113078066 A CN113078066 A CN 113078066A
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etching
groove
oxide layer
silicon nitride
gate
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CN113078066B (en
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乔明
马涛
王正康
张波
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University of Electronic Science and Technology of China
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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention provides a manufacturing method of a split gate power MOSFET device, which comprises the following steps: after a dielectric layer between the control gate and the separation gate is formed, depositing or thermally growing a sacrificial oxide layer, and depositing silicon nitride to fill the whole groove structure, wherein the silicon nitride is separated from the silicon layer in the MESA region through the sacrificial oxide; etching the silicon nitride to make the silicon nitride remained in the groove as a shielding layer for the next oxide layer etching; etching the oxide layer until the interface of the oxide layer is higher than the upper interface of the stepped separation gate, and then etching away the residual silicon nitride; and depositing polysilicon and etching back to form a control gate electrode. The device structure prepared by the invention has the advantages that the lower half part of the control grid is narrower, the grid-source capacitance Cgs can be greatly reduced, meanwhile, the cross-sectional area of the flowing grid current is increased by the upper half part of the control grid, the grid resistance is reduced on the premise of ensuring that the grid-source capacitance Cgs and the grid charge Qg are not degraded, and the aims of high switching speed and low switching loss are fulfilled.

Description

Manufacturing method of split gate power MOSFET device
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a manufacturing method of a split gate power MOSFET device.
Background
With the continuous development of new fields of electronic information industry, power semiconductor devices also meet a new development peak, and meanwhile, higher requirements are put forward on the performance of power MOSFETs, and lower switching loss and higher working efficiency become the development trend of power devices. The advantages of the power VDMOS with high frequency and low power consumption are gradually shown, and the power VDMOS is widely applied to the fields of power management and the like. The structure of the split-gate power MOSFET device developed based on the Trench MOSFET device utilizes the capacitive coupling effect between the split-gate electrode shielding control gate electrode and the epitaxial layer to reduce the gate-drain parasitic capacitance Cgd. Meanwhile, the separated gate electrode is used as an in-vivo field plate to assist in depletion of carriers in the drift region, so that the doping concentration of the drift region of the device can be obviously improved, and the specific on-resistance can be reduced. However, split-gate power MOSFET devices introduce parasitic capacitance associated with the split-gate electrode: the capacitance between the drain and the split gate electrode Cds and the capacitance between the gate and the split gate electrode Cgs, the added parasitic capacitance, to some extent, offsets the advantage of the split gate MOSFET device in reducing the gate-drain capacitance Cgd. Higher input-output capacitance adversely affects the operating efficiency of the system, and it is now becoming more and more important to reduce the capacitance of the drain and gate to the split gate electrode in order to meet the demand for higher operating frequencies.
Therefore, in view of the above problems, it is necessary to reduce the parasitic capacitance associated with the split gate electrode in the conventional split gate MOSFET device, and the manufacturing method of the split gate power MOSFET device according to the present invention is proposed in this context.
Disclosure of Invention
The invention provides a manufacturing method of a split gate power MOSFET device, wherein the preparation process of a control gate electrode comprises the steps of depositing or thermally growing a sacrificial oxide layer after a dielectric layer between a control gate and a split gate is formed, and depositing silicon nitride to fill the whole groove structure, wherein the sacrificial oxide layer is used as an isolation layer between the silicon nitride and a silicon layer in an MESA region; etching the silicon nitride to enable the silicon nitride reserved in the groove to be used as a shielding layer for etching the oxide layer; and etching the oxide layer with a certain thickness, then etching the residual silicon nitride, depositing polysilicon, and etching back to form the control gate electrode. Compared with the preparation of the traditional separation gate power MOSFET device, the manufacturing method is easy to implement, a mask photoetching process is not required to be added, and the parasitic capacitance Cgs and the gate charge Qg between the control gate and the separation gate electrode in the traditional separation gate MOSFET device are obviously reduced by the obtained device structure while the manufacturing cost is not increased. Compared with the power MOSFET device with a separated gate reinforcing structure, which is proposed in Chinese invention patent 201910191166.9 of Qiagming, Wangzhenkang, Zhang wave and the like and U.S. invention patent US16/536333, the lower half part of the control gate electrode of the structure is narrower, so that the gate-source capacitance Cgs of the device can be greatly reduced, the switching speed of the device is improved, the switching loss is reduced, and meanwhile, the cross-sectional area of gate current flowing can be increased to a certain extent by controlling the upper half part of the gate electrode, so that the gate resistance value is reduced on the premise that the gate-source capacitance Cgs and the gate charge Qg are not degraded, and the aims of high switching speed and low switching loss are achieved. By adopting the stepped separated gate electrode structure, the electric field distribution of the drift region of the device can be more uniform, and the improvement of the breakdown voltage BV and the specific on-resistance Ron can be realized.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a manufacturing method of a split gate power MOSFET device comprises the following steps:
1) forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner walls of the groove structures;
2) depositing polycrystalline silicon in the groove structure to enable the polycrystalline silicon to fill the whole groove;
3) etching the polycrystalline silicon deposited in the step 2), and forming the lower half part of a stepped separation gate electrode in a control gate groove of the active region;
4) wet etching the first dielectric layer, and then depositing polycrystalline silicon in the groove structure to fill the whole groove with the polycrystalline silicon;
5) etching the polycrystalline silicon deposited in the step 4), and forming the upper half part of the stepped separation gate electrode in the control gate groove of the active region;
6) depositing and back-etching the upper parts of the stepped separation gates in the grooves of the active region to form a second dielectric layer;
7) thermally growing or depositing an oxide layer, and then depositing silicon nitride in the groove structure to fill the whole groove of the active region;
8) wet etching the silicon nitride deposited in the step 7) to enable the upper interface of the silicon nitride to be lower than the upper surface of the silicon layer in the MESA area of the platform area, and keeping the silicon nitride in the groove as a shielding layer for etching the oxide layer next;
9) etching the oxide layer by a wet method, and then etching the oxide layer by a dry method to enable an etched interface to be higher than an upper interface of the stepped separation gate; etching the residual silicon nitride in the groove by a wet method;
10) thermally growing the upper half part of the control gate groove in the active region to form a gate dielectric covering the side wall; then depositing polysilicon in the active region to fill the whole groove;
11) etching the polysilicon deposited in the step 9), and forming a control gate electrode on the upper half part in the control gate groove of the active region;
12) forming a second conductive type well region on the upper surface of the epitaxial layer, and forming a first conductive type source region in the second conductive type well region;
13) and depositing a dielectric layer, etching a source contact hole in the source region and the separation gate lead-out region, injecting metal and leading out a potential.
Preferably, the first dielectric layer formed in step 1) of the manufacturing method is made of a low-k material with k less than 3.9.
Preferably, the second dielectric layer formed in step 6) of the manufacturing method is made of a low-k material with k less than 3.9.
Preferably, step 7) of the manufacturing method controls the thickness of the thermally grown or deposited oxide layer to finally obtain the required width of the vertical part of the control gate electrode.
Preferably, after wet etching the oxide layer in step 9), the interface of the oxide layer is controlled to be lower than the upper interface of the silicon nitride retained in the trench and higher than the lower interface of the silicon nitride, and then the oxide layer is selectively dry etched.
Preferably, step 9) of the manufacturing method is implemented as follows:
9) dry etching the oxide layer, and controlling the distance between the etched interface and the upper interface of the stepped separation gate; the remaining silicon nitride in the trench is then wet etched away.
Preferably, in the manufacturing method, step 7) to step 9) use polysilicon instead of silicon nitride:
7) thermally growing or depositing an oxide layer, and then depositing polycrystalline silicon in the groove structure to fill the whole groove of the active region;
8) etching the polysilicon deposited in the step 7) to enable the upper interface to be lower than the upper surface of the silicon layer in the MESA area of the platform area, and using the polysilicon reserved in the groove as a shielding layer for the next oxide layer etching;
9) wet etching the oxide layer, and selecting a dry etching oxide layer to enable the etched interface to be higher than the upper interface of the stepped separation gate; the remaining polysilicon in the trench is then etched away.
The invention has the beneficial effects that: in the preparation process of the control gate electrode, silicon nitride or polysilicon is used as an etching shielding layer in the steps 7) to 9), polysilicon is deposited and etched back after an oxide layer is etched, the lower half part of the formed control gate electrode is narrower, the overlapping area of the formed control gate electrode and the stepped separation gate electrode is smaller, and the gate source capacitance Cgs can be greatly reduced. Meanwhile, the upper half part of the control gate electrode is obviously wider, so that the cross-sectional area for flowing of gate current is increased to a certain extent, and the gate resistance is effectively reduced. The manufacturing method is easy to implement, an additional mask photoetching process is not needed, and the obtained device structure has the characteristics of low gate charge and low gate resistance, so that the aims of high switching speed and low switching loss are fulfilled.
Drawings
Fig. 1 is a schematic structural diagram of a conventional split-gate power MOSFET device.
Fig. 2 is a schematic structural diagram of a split-gate power MOSFET device obtained by the manufacturing method of embodiment 1 according to the present invention.
Fig. 3 is a flowchart of a method for manufacturing a split-gate power MOSFET device according to embodiment 1 of the present invention, which is sequentially from left to right and from top to bottom.
FIG. 4 is a partial step diagram of a manufacturing method according to embodiment 2 of the present invention, which is used to replace the processes (j) to (k) in FIG. 3; the differences from the manufacturing method described in example 1 of the present invention are: and 9) directly dry-etching the oxide layer.
Fig. 5 is a schematic structural diagram of a split-gate power MOSFET device obtained by the manufacturing method according to embodiment 3 of the present invention.
Fig. 6 is a schematic structural diagram of a split-gate power MOSFET device obtained by the manufacturing method according to embodiment 4 of the present invention.
10 is a first conductive type substrate, 11 is a first conductive type epitaxial layer, 12 is a trench structure, 131 is a first dielectric layer, 132 is a second dielectric layer, 133 is a gate dielectric layer, 134 is a third dielectric layer, 14 is a sacrificial oxide layer, 15 is a shielding layer (silicon nitride or polysilicon), 16 is a split gate electrode, 17 is a control gate electrode, 18 is a second conductive type well region, 19 is a second conductive type heavily doped region, 20 is a first conductive type heavily doped source region, and 21 is a metal.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
As shown in fig. 3, a method of manufacturing a split gate power MOSFET device includes the steps of:
1) forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner walls of the groove structures;
2) depositing polycrystalline silicon in the groove structure to enable the polycrystalline silicon to fill the whole groove;
3) etching the polycrystalline silicon deposited in the step 2), and forming the lower half part of a stepped separation gate electrode in a control gate groove of the active region;
4) wet etching the first dielectric layer, and then depositing polycrystalline silicon in the groove structure to fill the whole groove with the polycrystalline silicon;
5) etching the polycrystalline silicon deposited in the step 4), and forming the upper half part of the stepped separation gate electrode in the control gate groove of the active region;
6) depositing and back-etching the upper parts of the stepped separation gates in the grooves of the active region to form a second dielectric layer;
7) thermally growing or depositing an oxide layer, and then depositing silicon nitride in the groove structure to fill the whole groove of the active region;
8) wet etching the silicon nitride deposited in the step 7) to enable the upper interface of the silicon nitride to be lower than the upper surface of the silicon layer in the MESA area of the platform area, and keeping the silicon nitride in the groove as a shielding layer for etching the oxide layer next;
9) etching the oxide layer by a wet method, and then etching the oxide layer by a dry method to enable an etched interface to be higher than an upper interface of the stepped separation gate; etching the residual silicon nitride in the groove by a wet method;
10) thermally growing the upper half part of the control gate groove in the active region to form a gate dielectric covering the side wall; then depositing polysilicon in the active region to fill the whole groove;
11) etching the polysilicon deposited in the step 9), and forming a control gate electrode on the upper half part in the control gate groove of the active region;
12) forming a second conductive type well region on the upper surface of the epitaxial layer, and forming a first conductive type source region in the second conductive type well region;
13) and depositing a dielectric layer, etching a source contact hole in the source region and the separation gate lead-out region, injecting metal and leading out a potential.
Preferably, step 7) of the manufacturing method can control the thickness of the thermally grown or deposited oxide layer to finally obtain the desired width of the vertical portion of the control gate electrode.
Preferably, after the wet etching of the oxide layer in step 9) of the manufacturing method, the interface of the oxide layer should be controlled to be lower than the upper interface of the silicon nitride retained in the trench and higher than the lower interface of the silicon nitride, and then the dry etching of the oxide layer with a certain thickness is selected.
Preferably, steps 7) to 9) of the manufacturing method use polysilicon instead of silicon nitride:
7) thermally growing or depositing an oxide layer, and then depositing polycrystalline silicon in the groove structure to fill the whole groove of the active region;
8) etching the polysilicon deposited in the step 7) to enable the upper interface to be lower than the upper surface of the silicon layer in the MESA area of the platform area, and using the polysilicon reserved in the groove as a shielding layer for the next oxide layer etching;
9) wet etching the oxide layer, and selecting a dry etching oxide layer to enable the etched interface to be higher than the upper interface of the stepped separation gate; the remaining polysilicon in the trench is then etched away.
Example 2
As shown in fig. 4, the present embodiment provides a part of steps of a manufacturing method of a split-gate power MOSFET device, which is used to replace the processes (j) - (k) in fig. 3, and the difference between the present embodiment and the manufacturing method described in embodiment 1 is that step 9) can be implemented as follows:
9) dry etching the oxide layer, and controlling to keep a certain distance between the etched interface and the upper interface of the stepped separation gate; etching the residual silicon nitride in the groove by a wet method;
example 3
As shown in fig. 5, the present embodiment is different from the manufacturing method described in embodiment 1 in that: the first dielectric layer surrounding the separation gate electrode formed in the step 1) is made of a low-k material with k less than 3.9 instead of silicon dioxide, so that the source-drain capacitance can be further reduced.
Example 4
As shown in fig. 6, the present embodiment is different from the manufacturing method described in embodiment 1 in that: and the second dielectric layer formed in the step 6) adopts a low-k material with k less than 3.9 to replace silicon dioxide, so that the gate-source capacitance can be further reduced.
While the present invention has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (7)

1. A manufacturing method of a split gate power MOSFET device is characterized by comprising the following steps:
1) forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner walls of the groove structures;
2) depositing polycrystalline silicon in the groove structure to enable the polycrystalline silicon to fill the whole groove;
3) etching the polycrystalline silicon deposited in the step 2), and forming the lower half part of a stepped separation gate electrode in a control gate groove of the active region;
4) wet etching the first dielectric layer, and then depositing polycrystalline silicon in the groove structure to fill the whole groove with the polycrystalline silicon;
5) etching the polycrystalline silicon deposited in the step 4), and forming the upper half part of the stepped separation gate electrode in the control gate groove of the active region;
6) depositing and back-etching the upper parts of the stepped separation gates in the grooves of the active region to form a second dielectric layer;
7) thermally growing or depositing an oxide layer, and then depositing silicon nitride in the groove structure to fill the whole groove of the active region;
8) wet etching the silicon nitride deposited in the step 7) to enable the upper interface of the silicon nitride to be lower than the upper surface of the silicon layer in the MESA area of the platform area, and keeping the silicon nitride in the groove as a shielding layer for etching the oxide layer next;
9) etching the oxide layer by a wet method, and then etching the oxide layer by a dry method to enable an etched interface to be higher than an upper interface of the stepped separation gate; etching the residual silicon nitride in the groove by a wet method;
10) thermally growing the upper half part of the control gate groove in the active region to form a gate dielectric covering the side wall; then depositing polysilicon in the active region to fill the whole groove;
11) etching the polysilicon deposited in the step 9), and forming a control gate electrode on the upper half part in the control gate groove of the active region;
12) forming a second conductive type well region on the upper surface of the epitaxial layer, and forming a first conductive type source region in the second conductive type well region;
13) and depositing a dielectric layer, etching a source contact hole in the source region and the separation gate lead-out region, injecting metal and leading out a potential.
2. The method of claim 1, wherein the step of forming the split-gate power MOSFET comprises: the first dielectric layer formed in the step 1) is made of a low-k material with k less than 3.9.
3. The method of claim 1, wherein the step of forming the split-gate power MOSFET comprises: the second dielectric layer formed in the step 6) is made of a low-k material with k less than 3.9.
4. The method of claim 1, wherein the step of forming the split-gate power MOSFET comprises: and 7) controlling the thickness of the oxide layer thermally grown or deposited in the step 7) to finally obtain the width of the vertical part of the control gate electrode meeting the requirement.
5. The method of claim 1, wherein the step of forming the split-gate power MOSFET comprises: and 9) after wet etching the oxide layer, controlling the interface of the oxide layer to be lower than the upper interface of the silicon nitride reserved in the groove and higher than the lower interface of the silicon nitride, and then selecting a dry etching method to etch the oxide layer.
6. The method of claim 1, wherein step 9) is implemented by:
9) dry etching the oxide layer, and controlling the distance between the etched interface and the upper interface of the stepped separation gate; the remaining silicon nitride in the trench is then wet etched away.
7. The method of claim 1, wherein polysilicon is used in place of silicon nitride in steps 7) to 9):
7) thermally growing or depositing an oxide layer, and then depositing polycrystalline silicon in the groove structure to fill the whole groove of the active region;
8) etching the polysilicon deposited in the step 7) to enable the upper interface to be lower than the upper surface of the silicon layer in the MESA area of the platform area, and using the polysilicon reserved in the groove as a shielding layer for the next oxide layer etching;
9) wet etching the oxide layer, and selecting a dry etching oxide layer to enable the etched interface to be higher than the upper interface of the stepped separation gate; the remaining polysilicon in the trench is then etched away.
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