CN116995093A - Charge self-balancing bipolar power semiconductor device and manufacturing method thereof - Google Patents
Charge self-balancing bipolar power semiconductor device and manufacturing method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 106
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 77
- 229920005591 polysilicon Polymers 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 28
- 230000003071 parasitic effect Effects 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims description 23
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- 238000000034 method Methods 0.000 claims description 20
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- 239000012535 impurity Substances 0.000 claims description 9
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- 238000007254 oxidation reaction Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
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- 238000001727 in vivo Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 2
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- 150000002500 ions Chemical class 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention provides a bipolar power semiconductor device with self-balancing charges and a manufacturing method thereof, comprising the following steps: the semiconductor device comprises a first conductive type semiconductor substrate, a first conductive type well region, a first conductive type heavily doped semiconductor contact region, a second conductive type drift region, a second conductive type well region, a second conductive type heavily doped semiconductor contact region, a dielectric oxide layer, a polysilicon electrode, a control gate polysilicon electrode, source metal, anode metal, a through hole and a metal strip; the first dielectric oxide layer and the polysilicon electrode form a longitudinal floating field plate to form continuous depletion cells, so that the depletion capability of the device is improved. According to the invention, a floating longitudinal field plate is introduced below the drain region of the control transistor and the controlled power transistor grid to control a current path, so that high current is avoided, meanwhile, the longitudinal floating field plate array in the drift region can keep charge balance, the potential of the base region is reduced, the parasitic thyristor is difficult to conduct, the latch-up effect is avoided, and the grid control capability of the bipolar power semiconductor device is improved.
Description
Technical Field
The invention belongs to the field of power semiconductors, and mainly provides a bipolar power semiconductor device with self-balancing charges and a manufacturing method thereof.
Background
The bipolar power semiconductor device improves the conduction voltage drop of the device through the conductivity modulation effect, and the source electrode, the drain electrode and the grid electrode of the transverse device are distributed on the surface of the chip, so that the bipolar power semiconductor device has the characteristic of easy integration. Therefore, the lateral bipolar power semiconductor device is widely used in high-voltage integrated circuits and high-voltage power circuits. Because of the characteristics of high input impedance, low on-resistance, low power consumption and easy integration, the method is applied to various aspects of consumer electronics, automobile electronics, smart grids, motor driving and the like. For the traditional high-voltage bipolar power semiconductor device, when the starting current increases to a certain extent, the potential of the base region rises, when the potential exceeds the starting voltage of the parasitic tube, the parasitic NPN tube can be started, so that the starting current continues to increase, the parasitic PNP tube is started, the parasitic NPNP thyristor is turned on, the device cannot be turned off by itself, and the latch-up occurs. The latch-up effect can cause the on-current of the device to be rapidly increased, large power consumption is generated, and the turn-off cannot be controlled, so how to avoid the latch-up of the parasitic thyristor by controlling the turn-on current becomes an important problem faced by the bipolar power semiconductor device. The on-current of the device can be controlled by the channel current of the control transistor by integrating the control transistor and the lateral bipolar power semiconductor device, and the on-current of the control transistor and the lateral bipolar power semiconductor device can be kept the same. Meanwhile, the charge balance can be kept by adding a longitudinal field plate array in a drift region of the controlled power tube, the potential of a base region is reduced, and a current channel is changed by adding the longitudinal field plate, so that the starting current is easier to control, the parasitic thyristor is difficult to conduct, and the latch-up effect is effectively avoided. The invention provides a charge self-balancing bipolar power semiconductor device and a manufacturing method thereof, which effectively improves the grid control capability of the bipolar power semiconductor device and has simpler manufacturing method
Disclosure of Invention
The invention integrates the control transistor and the transverse bipolar power semiconductor device through a compatible process, provides the bipolar power semiconductor device with self-balancing charges, solves the problem of conducting parasitic thyristors of the bipolar transistor, effectively improves the gate control capability of the bipolar power semiconductor device, and optimizes the safe working area of the bipolar power semiconductor device.
In order to achieve the above object, the present invention has the following technical scheme:
a charge self-balancing bipolar power semiconductor device comprising a control transistor portion and a controlled power transistor portion:
the control transistor portion includes: a sixth dielectric oxide layer 36 over the first conductivity type semiconductor substrate 11, a second conductivity type well region 22A over the sixth dielectric oxide layer 36, the first conductivity type well region a12 being located on the left side of the second conductivity type well region a22, the first conductivity type heavily doped semiconductor contact region 14 and the second conductivity type heavily doped semiconductor contact region 24 being located in the first conductivity type well region a 12; the source metal 51 is located on the upper surfaces of the first conductivity type heavily doped semiconductor contact region 14 and the second conductivity type heavily doped semiconductor contact region 24; the second dielectric oxide layer 32 is located above the first conductivity type well region a12, and has a left end in contact with the second conductivity type heavily doped semiconductor contact region 24 and a right end in contact with the second conductivity type well region a22; the control gate polysilicon electrode A42 covers the upper surface of the second dielectric oxide layer 32;
the controlled power tube section includes: a second conductive-type drift region 21, a first conductive-type well region B13 being located at a left end of the second conductive-type drift region 21 and at a right end of a second conductive-type well region a22 of the control transistor portion, a second conductive-type well region B23 being located at a right side of the second conductive-type drift region 21, a first conductive-type heavily doped semiconductor contact region 14 being located above the second conductive-type well region B23, an anode metal 52 being located at an upper surface of the first conductive-type heavily doped semiconductor contact region 14; the third dielectric oxide layer 33 is located above the first conductivity type well region B13, and has a left end in contact with the second conductivity type well region a22 and a right end in contact with the second conductivity type drift region 21; the fourth dielectric oxide layer 34 is located on the upper surface of the second conductivity type drift region 21 between the third dielectric oxide layer 33 and the first conductivity type heavily doped semiconductor contact region 14; the control gate polysilicon electrode B43 covers the upper surface of the third dielectric oxide layer 33 and extends partially to the upper surface of the fourth dielectric oxide layer 34;
the first dielectric oxide layer 31 and the polysilicon electrode 41 form a longitudinal field plate, and the first dielectric oxide layer 31 surrounds the polysilicon electrode 41, and the longitudinal field plates are respectively positioned in the second conductivity type well region A22 of the control transistor part and the second conductivity type drift region 21 of the control power tube part to form a longitudinal field plate array; forming an isolation longitudinal field plate at the source end of the control transistor by the same process as the longitudinal field plate, wherein the isolation longitudinal field plate penetrates through the first conductive type well region A12 to the sixth dielectric oxide layer 36, the isolation longitudinal field plate is continuously and continuously maintained in the z direction at the same time, and is distributed at the source end of the control transistor as a dielectric isolation groove, and the isolation groove is grounded through the polysilicon electrode 41; the longitudinal field plates distributed in the second conductivity type well region a22 of the control transistor portion are continuous in the z direction or are discretely arranged in the z direction; longitudinal field plates distributed in the second conductivity type drift region 21 of the controlled power tube part are distributed at equal intervals in the x direction and are connected with the metal strips 63 through the through holes 53 to form an in-vivo equipotential ring; a column of longitudinal field plates are distributed below the control gate polysilicon electrode B43 and are arranged in a floating manner; the floating longitudinal field plates distributed under the controlled power tube control gate polysilicon electrode B43 are of a z-direction discrete type or a z-direction continuous type, or of an X-direction discrete type or an X-direction continuous type.
Preferably, the depth of the isolation longitudinal field plate is deeper than the control transistor second conductivity type well region a22 and the longitudinal field plate positioned in the controlled power tube second conductivity type drift region 21, and is connected with the sixth dielectric oxide layer 36 and is grounded through a metal strip; and forming an all-dielectric oxidation isolation groove in the subsequent groove wall oxidation process by reducing the etching width of the longitudinal field plate for isolation.
Preferably, the longitudinal and lateral pitches of the longitudinal field plates distributed in the controlled power tube second conductivity type drift region 21 are equal and alternately arranged in the x-direction and in the z-direction;
and/or the floating vertical field plates distributed under the controlled transistor control gate polysilicon electrode B43 are discrete or continuous in the z-direction.
As a preferred mode, the longitudinal field plate in the second conductivity type well region a22 of the control transistor plays a role in controlling a current path and stabilizing an opening current, so that parasitic transistor opening caused by overlarge opening current is avoided; the longitudinal field plates located in the controlled power tube second conductivity type drift region 21 act to maintain charge balance in the drift region and reduce the first conductivity type well region potential, avoiding turn on of parasitic transistors.
Preferably, all of the longitudinal field plates are contiguous with the sixth dielectric oxide layer 36 by increasing the longitudinal width of the longitudinal field plates.
Preferably, a doped layer of the first conductivity type is implanted in the drift region 21 of the second conductivity type of the controlled power transistor, the doped layer being located at the surface or in the body.
Preferably, after the control gate polysilicon electrode B43 located on the control transistor second conductive type well region a22 is formed, the first conductive type heavily doped semiconductor contact region 14 is simultaneously formed on both sides thereof by a self-alignment process.
Preferably, the control polysilicon electrode in the control transistor region is etched to form a vertical gate;
and the first conductive-type well region located in the control transistor region is formed through a deep well process or through an additional well process.
Preferably, the control gate polysilicon a42 located in the control transistor region and the control gate polysilicon B43 located in the controlled power transistor region are continuous or discrete in the z-direction.
The invention also provides a manufacturing method of the charge self-balancing bipolar power semiconductor device, which comprises the following steps:
step 1: selecting an SOI material comprising a silicon-based first conductivity type semiconductor substrate 11, a sixth dielectric oxide layer 36;
step 2: ion implantation of first conductivity type impurities and junction pushing to form a first conductivity type well region A12 and a first conductivity type well region B13, ion implantation of second conductivity type impurities and junction pushing to form a second conductivity type drift region 21 and a second conductivity type well region A22;
step 3: forming a groove by photoetching and etching;
step 4: forming a first dielectric oxide layer 31 in the trench;
step 5: depositing polycrystalline silicon and etching the polycrystalline silicon to a silicon plane to form a polycrystalline silicon electrode 41;
step 6: growing to form a fourth dielectric oxide layer 34;
step 7: implanting second conductivity type impurities into the silicon substrate and performing high-temperature junction pushing to form a second conductivity type well region B23;
step 8: growing gate oxide by thermal oxidation, and forming a second dielectric oxide layer 32 and a third dielectric oxide layer 33 by etching;
step 9: depositing and etching polysilicon to form a control gate polysilicon electrode A42 and a control gate polysilicon electrode B43;
step 10: forming the first conductivity type heavily doped semiconductor contact region 14 and the second conductivity type heavily doped semiconductor contact region 24 by implantation;
step 11: silicon oxide is deposited and the surface planarized to form the fifth dielectric oxide layer 35, and contact holes are formed by etching, and then metal strips 63 are deposited and etched to form surface metal strips and metal electrodes.
The beneficial effects of the invention are as follows: the longitudinal field plates introduce charge self-balance in a controlled power tube drift region, deplete the drift region in an off state, and carry out capacitive coupling through an equipotential ring to regulate potential, so that an electric field inside the device is uniformly distributed, and the off-state withstand voltage of the device is improved. The main innovation point is that the control transistor and the transverse bipolar power semiconductor device are integrated through a compatible process, so that the starting current of the device is controlled by the channel current of the control transistor, and the starting current of the control transistor and the transverse bipolar power semiconductor device is kept the same. Meanwhile, the charge balance is kept by adding the longitudinal field plate array in the drift region of the controlled power tube, the base region potential is reduced, and the current channel is changed by adding the longitudinal field plate, so that the starting current is easier to control, the problem of conducting the parasitic thyristor of the bipolar transistor is solved, the gate control capability of the bipolar power semiconductor device is effectively improved, and the safe working range of the bipolar power semiconductor device is optimized.
Drawings
Fig. 1 is a charge self-balancing bipolar power semiconductor device of example 1;
FIG. 2 is a top view of a charge self-balancing bipolar power semiconductor device structure of example 1;
FIG. 3 is a top view of a charge self-balancing bipolar power semiconductor device structure of example 2;
FIG. 4 is a top view of a charge self-balancing bipolar power semiconductor device structure of example 3;
fig. 5 (a) -5 (f) are top cross-sectional views of the vertical field plates in the second conductivity type well region a22 and the floating vertical field plates under the controlled transistor control gate polysilicon electrode B43 of embodiment 4 to show that the vertical field plates in the second conductivity type well region a22 distributed in the controlled transistor portion are continuously or discretely arranged in the z-direction, the floating vertical field plates distributed under the controlled transistor control gate polysilicon electrode B43 are discrete in the z-direction or continuous in the z-direction, or are different combinations of discrete in the X-direction or continuous in the X-direction; wherein:
fig. 5 (a) shows that the vertical field plates in the second conductivity type well region a22 of the control transistor portion are separated in the z direction, and the floating vertical field plates under the control gate polysilicon electrode B43 of the control transistor are separated in the z direction;
fig. 5 (b) is a schematic structural diagram showing that the longitudinal field plates in the second conductivity type well region a22 of the control transistor portion are separated in the z direction, and the longitudinal field plates under the controlled power transistor control gate polysilicon 43 are continuous in the z direction;
fig. 5 (c) is a schematic structural diagram showing the vertical field plate in the x-direction continuous under the control gate polysilicon 43 of the control transistor with discrete z-direction vertical field plate in the second conductivity type well region 22;
fig. 5 (d) is a schematic structural diagram showing the z-direction discrete type longitudinal field plate under the control gate polysilicon 43 of the control transistor, which is continuous in the z-direction of the longitudinal field plate of the second conductivity type well region 22;
fig. 5 (e) is a schematic structural diagram of the vertical field plate z-direction continuity of the vertical field plate z-direction of the second conductivity type well region 22 of the control transistor under the control gate polysilicon 43 of the controlled power transistor;
fig. 5 (f) is a schematic structural diagram of the vertical field plate of the second conductivity type well region 22 of the control transistor in the z-direction continuous mode, and the vertical field plate of the controlled power transistor under the control gate polysilicon 43 in the x-direction discrete mode;
fig. 6 is a front view of a charge self-balancing bipolar power semiconductor device structure of embodiment 1;
fig. 7 is a front view of a charge self-balancing bipolar power semiconductor device structure of embodiment 5;
fig. 8 is a front view of a charge self-balancing bipolar power semiconductor device structure of example 6;
fig. 9 is a front view of a charge self-balancing bipolar power semiconductor device structure of embodiment 7;
fig. 10 is a front view of a charge self-balancing bipolar power semiconductor device structure of example 8;
FIG. 11 is a front view of a charge self-balancing bipolar power semiconductor device according to example 9;
fig. 12 is a front view of a charge self-balancing bipolar power semiconductor device structure according to embodiment 10;
FIGS. 13 (a) - (m) are schematic process flow diagrams of a charge self-balancing bipolar power semiconductor device of example 1;
11 is a first conductivity type semiconductor substrate, 12 is a first conductivity type well region a,13 is a first conductivity type well region B,14 is a first conductivity type heavily doped semiconductor contact region, 21 is a second conductivity type drift region, 22 is a second conductivity type well region a,23 is a second conductivity type well region B,24 is a second conductivity type heavily doped semiconductor contact region, 31 is a first dielectric oxide layer, 32 is a second dielectric oxide layer, 33 is a third dielectric oxide layer, 34 is a fourth dielectric oxide layer, 35 is a fifth dielectric oxide layer, 36 is a sixth dielectric oxide layer, 41 is a polysilicon electrode, 42 is a control gate polysilicon electrode a,43 is a control gate polysilicon electrode B,51 is a source metal, 52 is an anode metal, 53 is a via hole, and 63 is a metal bar.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Example 1
A charge self-balancing bipolar power semiconductor device according to embodiment 1, as shown in fig. 1, 2, and 6, includes a control transistor portion and a controlled power transistor portion:
the control transistor portion includes: a sixth dielectric oxide layer 36 over the first conductivity type semiconductor substrate 11, a second conductivity type well region 22A over the sixth dielectric oxide layer 36, the first conductivity type well region a12 being located on the left side of the second conductivity type well region a22, the first conductivity type heavily doped semiconductor contact region 14 and the second conductivity type heavily doped semiconductor contact region 24 being located in the first conductivity type well region a 12; the source metal 51 is located on the upper surfaces of the first conductivity type heavily doped semiconductor contact region 14 and the second conductivity type heavily doped semiconductor contact region 24; the second dielectric oxide layer 32 is located above the first conductivity type well region a12, and has a left end in contact with the second conductivity type heavily doped semiconductor contact region 24 and a right end in contact with the second conductivity type well region a22; the control gate polysilicon electrode A42 covers the upper surface of the second dielectric oxide layer 32;
the controlled power tube section includes: a second conductive-type drift region 21, a first conductive-type well region B13 being located at a left end of the second conductive-type drift region 21 and at a right end of a second conductive-type well region a22 of the control transistor portion, a second conductive-type well region B23 being located at a right side of the second conductive-type drift region 21, a first conductive-type heavily doped semiconductor contact region 14 being located above the second conductive-type well region B23, an anode metal 52 being located at an upper surface of the first conductive-type heavily doped semiconductor contact region 14; the third dielectric oxide layer 33 is located above the first conductivity type well region B13, and has a left end in contact with the second conductivity type well region a22 and a right end in contact with the second conductivity type drift region 21; the fourth dielectric oxide layer 34 is located on the upper surface of the second conductivity type drift region 21 between the third dielectric oxide layer 33 and the first conductivity type heavily doped semiconductor contact region 14; the control gate polysilicon electrode B43 covers the upper surface of the third dielectric oxide layer 33 and extends partially to the upper surface of the fourth dielectric oxide layer 34;
the first dielectric oxide layer 31 and the polysilicon electrode 41 form a longitudinal field plate, and the first dielectric oxide layer 31 surrounds the polysilicon electrode 41, and the longitudinal field plates are respectively positioned in the second conductivity type well region A22 of the control transistor part and the second conductivity type drift region 21 of the control power tube part to form a longitudinal field plate array; forming an isolation longitudinal field plate at the source end of the control transistor by the same process as the longitudinal field plate, wherein the isolation longitudinal field plate penetrates through the first conductive type well region A12 to the sixth dielectric oxide layer 36, the isolation longitudinal field plate is communicated in a z direction at the same time, is distributed at the source end of the control transistor as a dielectric isolation groove, and is grounded through the polysilicon electrode 41; the longitudinal field plates distributed in the second conductivity type well region a22 of the control transistor portion are arranged separately in the z direction; longitudinal field plates distributed in the second conductivity type drift region 21 of the controlled power tube part are distributed at equal intervals in the x direction and are connected with the metal strips 63 through the through holes 53 to form an in-vivo equipotential ring; a column of longitudinal field plates are distributed below the control gate polysilicon electrode B43 and are arranged in a floating manner; the horizontal direction from the control transistor part to the controlled power transistor part of the device is x direction, the downward direction of the longitudinal field plate depth is y direction, and the inward direction perpendicular to the xy plane is z direction.
The depth of the longitudinal field plate for isolation is deeper than that of the well region A22 of the second conductivity type of the control transistor and the longitudinal field plate positioned in the drift region 21 of the second conductivity type of the controlled power tube, and the longitudinal field plate is connected with the sixth dielectric oxide layer 36 and grounded through a metal strip; and forming an all-dielectric oxidation isolation groove in the subsequent groove wall oxidation process by reducing the etching width of the longitudinal field plate for isolation.
As shown in fig. 2, the longitudinal pitch and the lateral pitch of the longitudinal field plates distributed in the controlled power tube second conductivity type drift region 21 are equal and alternately arranged in the x-direction and in the z-direction; the control gate polysilicon a42 located in the control transistor region and the control gate polysilicon B43 located in the controlled power transistor region are continuous in the z direction;
the longitudinal field plate positioned in the second conduction type well region A22 of the control transistor plays a role in controlling a current path and stabilizing an opening current, so that parasitic transistors are prevented from being opened due to overlarge opening current; the longitudinal field plates located in the controlled power tube second conductivity type drift region 21 act to maintain charge balance in the drift region and reduce the first conductivity type well region potential, avoiding turn on of parasitic transistors.
Forming a longitudinal grid electrode by etching a control polysilicon electrode positioned in the control transistor region;
the basic working principle is as follows:
taking a first conductive type semiconductor material as a P-type for example, when the grid bias voltage is 0, a longitudinal field plate in a drift region introduces a global MIS depletion mechanism, and is connected through a metal strip 63 to form an in-vivo equipotential ring modulation electric field, so that the electric field distribution in the power tube device is uniform. The longitudinal field plate positioned in the N-type well region of the control transistor plays a role in controlling a current path and stabilizing starting current, and the starting of a parasitic N-p-N-p thyristor caused by overlarge starting current is avoided. The longitudinal field plates positioned in the N-type drift region of the controlled power tube play a role in keeping charge balance in the drift region, and the potential of the P-type well region of the controlled power tube can be reduced, so that the potential difference between the P-type well region of the controlled power tube and the N-type well region of the control transistor is reduced, and the parasitic transistor is prevented from being started. In summary, the bipolar power semiconductor device with self-balancing charge solves the problem of conducting parasitic thyristors of bipolar transistors, effectively improves the gate control capability of the bipolar power semiconductor device, and optimizes the safe working range of the bipolar power semiconductor device.
As shown in fig. 13, a schematic process flow chart of embodiment 1 of the present invention specifically includes the following steps:
step 1: selecting an SOI material comprising a silicon-based first conductivity type semiconductor substrate 11, a sixth dielectric oxide layer 36, as shown in FIG. 13 (a);
step 2: ion implanting first conductivity type impurities and pushing a junction to form a first conductivity type well region a12 and a first conductivity type well region B13, ion implanting second conductivity type impurities and pushing a junction to form a second conductivity type drift region 21 and a second conductivity type well region a22, as shown in fig. 13 (B);
step 3: forming a groove by photolithography and etching, as shown in fig. 13 (c);
step 4: forming a first dielectric oxide layer 31 in the trench as shown in fig. 13 (d);
step 5: polysilicon is deposited and etched to the silicon plane to form polysilicon electrode 41, as shown in fig. 13 (e) and 13 (f);
step 6: growing to form a fourth dielectric oxide layer 34, as shown in fig. 13 (g);
step 7: ion implanting second conductivity type impurities and performing high temperature junction pushing to form a second conductivity type well region B23, as shown in FIG. 13 (h);
step 8: forming a second dielectric oxide layer 32 and a third dielectric oxide layer 33 by thermal oxidation growth and then etching, as shown in fig. 13 (i);
step 9: depositing and etching polysilicon to form a control gate polysilicon electrode A42 and a control gate polysilicon electrode B43, as shown in FIG. 13 (j);
step 10: forming the first conductivity type heavily doped semiconductor contact region 14 and the second conductivity type heavily doped semiconductor contact region 24 by implantation, as shown in fig. 13 (k);
step 11: depositing silicon oxide and surface planarization to form a fifth dielectric oxide layer 35, as shown in fig. 13 (l); and forming contact holes by etching, and then depositing and etching the metal strips 63 to form surface metal strips and metal electrodes, as shown in fig. 13 (m);
example 2
As shown in fig. 3, which is a top view of a charge self-balancing bipolar power semiconductor device structure of embodiment 2, the difference between the structure of this embodiment and that of embodiment 1 is that the device control gate polysilicon electrode 43 is discrete in the z-axis direction, which is beneficial to reducing the turn-on current of the device and avoiding the turn-on of the parasitic thyristor, and the working principle is basically the same as that of embodiment 1.
Example 3
As shown in fig. 4, a top view of a bipolar power semiconductor device structure with charge self-balancing in embodiment 3 is shown, which is different from the structure in embodiment 1 in that the control gate polysilicon a42 in the control transistor region and the control gate polysilicon B43 in the controlled power transistor region of the device are discrete in the z-axis direction, and this structure is beneficial to reducing the on-current of the device and avoiding the on of the parasitic thyristor, and its working principle is basically the same as that of embodiment 1.
Example 4
Fig. 5 (a) -5 (f) are top cross-sectional views of the vertical field plates in the second conductivity type well region a22 and the floating vertical field plates under the controlled transistor control gate polysilicon electrode B43 of embodiment 4 to show that the vertical field plates in the second conductivity type well region a22 distributed in the controlled transistor portion are continuously or discretely arranged in the z-direction, the floating vertical field plates distributed under the controlled transistor control gate polysilicon electrode B43 are discrete in the z-direction or continuous in the z-direction, or are different combinations of discrete in the X-direction or continuous in the X-direction; the structure can adjust the starting current of the device by adjusting the distribution of the longitudinal field plates, so as to avoid the starting of the parasitic thyristor, and the working principle is basically the same as that of the embodiment 1.
Wherein:
fig. 5 (a) shows that the vertical field plates in the second conductivity type well region a22 of the control transistor portion are separated in the z direction, and the floating vertical field plates under the control gate polysilicon electrode B43 of the control transistor are separated in the z direction;
fig. 5 (b) is a schematic structural diagram showing that the longitudinal field plates in the second conductivity type well region a22 of the control transistor portion are separated in the z direction, and the longitudinal field plates under the controlled power transistor control gate polysilicon 43 are continuous in the z direction;
fig. 5 (c) is a schematic structural diagram showing the vertical field plate in the x-direction continuous under the control gate polysilicon 43 of the control transistor with discrete z-direction vertical field plate in the second conductivity type well region 22;
fig. 5 (d) is a schematic structural diagram showing the z-direction discrete type longitudinal field plate under the control gate polysilicon 43 of the control transistor, which is continuous in the z-direction of the longitudinal field plate of the second conductivity type well region 22;
fig. 5 (e) is a schematic structural diagram of the vertical field plate z-direction continuity of the vertical field plate z-direction of the second conductivity type well region 22 of the control transistor under the control gate polysilicon 43 of the controlled power transistor;
fig. 5 (f) is a schematic structural diagram of the vertical field plate of the second conductivity type well region 22 of the control transistor in the z-direction continuous mode, and the vertical field plate of the controlled power transistor under the control gate polysilicon 43 in the x-direction discrete mode;
example 5
Fig. 7 is a front view showing a structure of a charge self-balancing bipolar power semiconductor device in embodiment 5, which is different from that of embodiment 1 in that the device is formed on the control gate polysilicon electrode 43 on the control transistor second conductivity type well region 22, and then the first conductivity type heavily doped semiconductor contact regions 14 can be formed on both sides thereof by a self-alignment process, and the operation principle is basically the same as that of embodiment 1.
Example 6
Fig. 8 is a front view of a charge self-balancing bipolar power semiconductor device structure in embodiment 6, which is different from embodiment 1 in that the control gate polysilicon electrode of the device located in the control transistor is a vertical polysilicon electrode, and the structure can adjust the turn-on current of the device to avoid the turn-on of the parasitic thyristor, and its working principle is basically the same as that of embodiment 1.
Example 7
Fig. 9 is a front view of a charge self-balancing bipolar power semiconductor device structure in embodiment 7, which is different from embodiment 6 in that a first conductivity type well region of a control transistor of the device is formed by a second well process, and the structure can adjust the gate length of the device by controlling the depth of the first conductivity type well, so as to adjust the on-current of the device, avoid the on of a parasitic thyristor, and basically have the same working principle as embodiment 1.
Example 8
Fig. 10 is a front view of a charge self-balancing bipolar power semiconductor device according to embodiment 8, which is different from the structure according to embodiment 1 in that a first conductivity type doped layer is injected into a second conductivity type drift region 21 of a controlled power transistor of the device, and the doped layer is located on the surface, and the structure can assist in depletion of the drift region and provide holes, so as to enhance the conductivity modulation effect of the device, and its operation principle is substantially the same as that of embodiment 1.
Example 9
Fig. 11 is a front view of a charge self-balancing bipolar power semiconductor device according to embodiment 9, which is different from the structure according to embodiment 1 in that a doped layer of a first conductivity type is injected into a drift region 21 of a controlled power transistor of the device, and the doped layer is located in the body, and the structure can assist in depletion of the drift region and provide holes at the same time, so as to enhance the conductivity modulation effect of the device, and its operation principle is substantially the same as that of embodiment 1.
Example 10
Fig. 12 is a front view showing a structure of a charge self-balancing bipolar power semiconductor device of embodiment 10, which is different from that of embodiment 1 in that the device is formed by widening the longitudinal width of the longitudinal field plates so that all the longitudinal field plates are connected to the sixth dielectric oxide layer 36, the longitudinal field plates can introduce electric potential into the substrate while depleting the substrate and the drift region of the second conductivity type, and the withstand voltage of the device is improved, and the operation principle thereof is substantially the same as that of embodiment 1.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims of this invention, which are within the skill of those skilled in the art, can be made without departing from the spirit and scope of the invention disclosed herein.
Claims (10)
1. A charge self-balancing bipolar power semiconductor device, characterized by: comprising a control transistor portion and a controlled power transistor portion:
the control transistor portion includes: a sixth dielectric oxide layer (36) over the first conductivity type semiconductor substrate (11), a second conductivity type well region (22) a over the sixth dielectric oxide layer (36), the first conductivity type well region a (12) being located to the left of the second conductivity type well region a (22), the first conductivity type heavily doped semiconductor contact region (14) and the second conductivity type heavily doped semiconductor contact region (24) being located in the first conductivity type well region a (12); the source metal (51) is positioned on the upper surfaces of the first conductive type heavily doped semiconductor contact region (14) and the second conductive type heavily doped semiconductor contact region (24); the second dielectric oxide layer (32) is positioned above the first conductive type well region A (12), the left end of the second dielectric oxide layer is contacted with the second conductive type heavily doped semiconductor contact region (24), and the right end of the second dielectric oxide layer is contacted with the second conductive type well region A (22); the control gate polysilicon electrode A (42) covers the upper surface of the second dielectric oxide layer (32);
the controlled power tube section includes: a second conductivity type drift region (21), a first conductivity type well region B (13) being located at a left end of the second conductivity type drift region (21) and at a right end of a second conductivity type well region a (22) of the control transistor portion, a second conductivity type well region B (23) being located at a right side of the second conductivity type drift region (21), a first conductivity type heavily doped semiconductor contact region (14) being located above the second conductivity type well region B (23), an anode metal (52) being located at an upper surface of the first conductivity type heavily doped semiconductor contact region (14); the third dielectric oxide layer (33) is positioned above the first conductive type well region B (13), the left end of the third dielectric oxide layer is contacted with the second conductive type well region A (22), and the right end of the third dielectric oxide layer is contacted with the second conductive type drift region (21); the fourth dielectric oxide layer (34) is positioned on the upper surface of the second conductivity type drift region (21) between the third dielectric oxide layer (33) and the first conductivity type heavily doped semiconductor contact region (14); the control gate polysilicon electrode B (43) covers the upper surface of the third dielectric oxide layer (33) and extends to the upper surface of the fourth dielectric oxide layer (34) partially;
the first dielectric oxide layer (31) and the polysilicon electrode (41) form a longitudinal field plate, and the first dielectric oxide layer (31) surrounds the polysilicon electrode (41), and the longitudinal field plates are respectively positioned in the second conductive type well region A (22) of the control transistor part and the second conductive type drift region (21) of the control power tube part to form a longitudinal field plate array; forming an isolation longitudinal field plate at the source end of the control transistor by the same process as the longitudinal field plate, wherein the isolation longitudinal field plate penetrates through the first conductive type well region A (12) to the sixth dielectric oxide layer (36), the isolation longitudinal field plate is continuously kept in the z direction at the same time, and is distributed at the source end of the control transistor as a dielectric isolation groove, and the isolation groove is grounded through a polycrystalline silicon electrode (41); the longitudinal field plates distributed in the second conductivity type well region a (22) of the control transistor portion are continuous in the z direction or are discretely arranged in the z direction; longitudinal field plates distributed in a second conductivity type drift region (21) of the controlled power tube part are distributed at equal intervals in the x direction and are connected with a metal strip (63) through a through hole (53) to form an in-vivo equipotential ring; a column of longitudinal field plates are distributed below the control gate polysilicon electrode B (43) and are arranged in a floating manner; the floating longitudinal field plates distributed under the controlled power tube control gate polysilicon electrode B (43) are discrete or continuous in the z direction, or discrete or continuous in the X direction;
the horizontal direction from the control transistor part to the controlled power transistor part of the device is x direction, the downward direction of the longitudinal field plate depth is y direction, and the inward direction perpendicular to the xy plane is z direction.
2. A charge self-balancing bipolar power semiconductor device as in claim 1, wherein: the method comprises the steps of carrying out a first treatment on the surface of the The depth of the longitudinal field plate for isolation is deeper than that of the well region A (22) of the second conductivity type of the control transistor and the longitudinal field plate positioned in the drift region (21) of the second conductivity type of the controlled power tube, and the longitudinal field plate is connected with the sixth dielectric oxide layer (36) and grounded through a metal strip; and forming an all-dielectric oxidation isolation groove in the subsequent groove wall oxidation process by reducing the etching width of the longitudinal field plate for isolation.
3. A charge self-balancing bipolar power semiconductor device as in claim 1, wherein: longitudinal and lateral pitches of the longitudinal field plates distributed in the controlled power tube second conductivity type drift region (21) are equal and alternately arranged in the x-direction and in the z-direction.
4. A charge self-balancing bipolar power semiconductor device as in claim 1, wherein: the longitudinal field plate positioned in the second conductive type well region A (22) of the control transistor plays a role in controlling a current path and stabilizing an opening current, so that parasitic transistor opening caused by overlarge opening current is avoided; the longitudinal field plates in the second conductivity type drift region (21) of the controlled power transistor act to maintain charge balance in the drift region and reduce the first conductivity type well region potential, avoiding turn-on of parasitic transistors.
5. A charge self-balancing bipolar power semiconductor device as in claim 1, wherein: all of the longitudinal field plates are interfaced with a sixth dielectric oxide layer (36) by increasing the longitudinal width of the longitudinal field plates.
6. A charge self-balancing bipolar power semiconductor device as in claim 1, wherein: a doped layer of the first conductivity type is implanted in a drift region (21) of the second conductivity type of the controlled power tube, the doped layer being located at the surface or in the body.
7. A charge self-balancing bipolar power semiconductor device as in claim 1, wherein: after the formation of the control gate polysilicon electrode B (43) on the control transistor second conductivity type well region a (22), the first conductivity type heavily doped semiconductor contact regions (14) are simultaneously formed on both sides thereof by a self-alignment process.
8. A charge self-balancing bipolar power semiconductor device as in claim 1, wherein: forming a longitudinal grid electrode by etching a control polysilicon electrode positioned in the control transistor region;
and the first conductive-type well region located in the control transistor region is formed through a deep well process or through an additional well process.
9. A charge self-balancing bipolar power semiconductor device as in claim 1, wherein: the control gate polysilicon a (42) in the control transistor region and the control gate polysilicon B (43) in the controlled power transistor region are either continuous or discrete in the z-direction.
10. A method of manufacturing a charge self-balancing bipolar power semiconductor device as claimed in any one of claims 1 to 5, comprising the steps of:
step 1: selecting an SOI material, wherein the SOI material comprises a silicon-based first-type conductive semiconductor substrate (11) and a sixth dielectric oxide layer (36);
step 2: ion implantation of first conductivity type impurities and junction pushing to form a first conductivity type well region A (12) and a first conductivity type well region B (13), ion implantation of second conductivity type impurities and junction pushing to form a second conductivity type drift region (21) and a second conductivity type well region A (22);
step 3: forming a groove by photoetching and etching;
step 4: forming a first dielectric oxide layer (31) in the trench;
step 5: depositing polycrystalline silicon and etching the polycrystalline silicon to a silicon plane to form a polycrystalline silicon electrode (41);
step 6: growing a fourth dielectric oxide layer (34);
step 7: implanting impurities of the second conductivity type into the second conductive type and performing high-temperature junction pushing to form a well region B (23) of the second conductivity type;
step 8: forming a second dielectric oxide layer (32) and a third dielectric oxide layer (33) by thermal oxidation growth of gate oxide and etching;
step 9: depositing and etching polysilicon to form a control gate polysilicon electrode A (42) and a control gate polysilicon electrode B (43);
step 10: implanting to form a first conductivity type heavily doped semiconductor contact region (14) and a second conductivity type heavily doped semiconductor contact region (24);
step 11: and depositing silicon oxide, flattening the surface to form a fifth dielectric oxide layer (35), forming a contact hole by etching, and then depositing and etching a metal strip (63) to form a surface metal strip and a metal electrode.
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