CN115224112A - Tandem type double-gate LIGBT device and manufacturing method thereof - Google Patents
Tandem type double-gate LIGBT device and manufacturing method thereof Download PDFInfo
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- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
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- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
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- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
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- 230000007246 mechanism Effects 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
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- 230000002457 bidirectional effect Effects 0.000 description 1
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Abstract
The invention provides a tandem double-gate LIGBT device and a manufacturing method thereof. The first dielectric oxide layer and the polysilicon electrode form a longitudinal field plate, and the longitudinal field plate is distributed in the whole second conduction type drift region to form a shimming IGBT device with a longitudinal field plate array. Meanwhile, a low-voltage control voltage circuit such as an MOS is formed at the cathode end of the IGBT by a compatible process. And manufacturing longitudinal field plate structures on two sides of the low-voltage control voltage circuit by a compatible process, and performing high-voltage and low-voltage isolation by using the longitudinal field plates as medium isolation grooves. Taking MOS as an example, the drain terminal of the low-voltage MOS is in short circuit with the cathode of the IGBT to form two devices connected in series, the grid is in short circuit, and the two devices are controlled by the same grid voltage. Because the two are connected in series, the current of the MOS is the current of the IGBT, so that the current of the whole device can be limited by changing the grid voltage of the low-voltage MOS, and the parasitic p-n-p-n latch is inhibited from being opened.
Description
Technical Field
The invention belongs to the field of power semiconductors, and mainly provides a tandem type double-gate structured LIGBT device and a manufacturing method thereof.
Background
The lateral insulated gate bipolar transistor is a composite power semiconductor device combining the high input impedance of MOSFET and the modulation characteristics of BJT conductance. The high-voltage LED driving circuit has the advantages of low on-state voltage, low driving power consumption, strong current capability, high voltage resistance, good thermal stability, good integration and the like, and is widely applied to intelligent ICs (integrated circuits) such as automobile electronics, intelligent power grids, motor driving and the like. However, for conventional LIGBT, when the collector current increases to a certain extent, the forward voltage is large enough to turn on the NPN transistor, which in turn saturates the parasitic NPN and PNP transistors. At this time, the parasitic thyristor is turned on, and the gate loses its original control function, thereby forming a self-locking phenomenon, which is the latch-up effect of the IGBT. The latch-up resistance of the IGBT is also an important parameter for measuring the operating characteristics of the IGBT, which limits the operating range of the IGBT. When the IGBT latches, the current at the anode rapidly increases, which causes excessive power consumption and device failure, and therefore parasitic effects must be suppressed to ensure the control of the gate in order to control the anode current. SOI materials are favored by researchers due to their advantages of low parasitic capacitance, low power consumption, low leakage current, latch-up suppression, and good process compatibility, and are now widely used in power ICs and LIGBT research.
In order to inhibit the latch-up effect of the shimming IGBT and improve the gate control capability of the device, a low-voltage control circuit such as an MOS is manufactured at the cathode end of the IGBT by a compatible process, and high-voltage and low-voltage isolation is carried out by taking a longitudinal field plate structure as a dielectric isolation groove. Taking MOS as an example, the MOS drain is in short circuit with the IGBT cathode, and the grid is connected, finally forming a low-voltage MOS and a high-voltage IGBT which are connected in series. Through the series structure, after the MOS with the grid voltage is started, the drain current of the MOS is the same as the anode current of the IGBT, so that the current of the whole device can be limited by changing the current through changing the grid voltage of the low-voltage MOS, and the parasitic p-n-p-n latch is controlled not to be started. The invention provides a series double-gate LIGBT device and a manufacturing method thereof, which solve the problem of gate runaway caused by latch-up effect of an IGBT, have stronger gate control capability and have simpler manufacturing method.
Disclosure of Invention
The invention provides a series-connection double-gate LIGBT device by utilizing a compatible process to form a low-voltage control circuit at the cathode end of a shimming IGBT and connecting the low-voltage control circuit with the IGBT in series, thereby solving the problem of gate runaway of the IGBT caused by latch-up effect of the IGBT and improving the working characteristics of the IGBT.
In order to achieve the purpose, the technical scheme of the series double-gate LIGBT device is as follows:
a series double-gate LIGBT device is divided into a low-voltage part and a high-voltage part:
the high-voltage part comprises: a fourth dielectric buried oxide layer 34 located above the first conductivity type semiconductor substrate 11, a second conductivity type drift region 21 located above the fourth dielectric oxide layer 34, a first conductivity type well region 12 located on the left side of the second conductivity type drift region 21, a second conductivity type well region 22 located on the right side of the second conductivity type drift region 21, a first conductivity type heavily doped cathode region 15 and a second conductivity type heavily doped cathode region 25 located in the first conductivity type well region 12; a cathode region metal 54 is located on the upper surfaces of the first conductivity type heavily doped cathode region 15 and the second conductivity type heavily doped cathode region 25, and an anode region metal 55 is located on the upper surface of the first conductivity type heavily doped anode region 16; the first conductive type heavily doped anode region 16 is located in the first conductive type well region 22; the second dielectric oxide layer 32 is located above the first conductivity type well region 12, and the left end contacts the second conductivity type heavily doped cathode region 25, and the right end contacts the second conductivity type drift region 21; the third dielectric oxide layer 33 is located on the upper surface of the second conductive type drift region 21 between the second dielectric oxide layer 32 and the first conductive type heavily doped anode region 16; the control gate polysilicon electrode 42 covers the upper surface of the second dielectric oxide layer 32 and partially extends to the upper surface of the third dielectric oxide layer 33;
the low-pressure part includes: a first conductivity type well region 12, a first conductivity type heavily doped source region 13, a second conductivity type heavily doped source region 23, and a second conductivity type heavily doped drain region 24 located in the first conductivity type well region 12; the second dielectric oxide layer 32 is located above the first conductive type well region 12, and the left end is contacted with the second conductive type heavily doped source region 23, and the right end is contacted with the second conductive type heavily doped drain region 24; the control gate polysilicon electrode 42 covers the upper surface of the second dielectric oxide layer 32, and the third dielectric oxide layer 33 is located above the polysilicon electrode 41; the drain metal 53 is located on the upper surface of the second conductive type drain heavily doped region 24, and the source metal 52 is located on the upper surfaces of the first conductive type heavily doped source region 13 and the second conductive type source heavily doped region 24;
the first dielectric oxide layer 31 and the polysilicon electrode 41 form a longitudinal field plate, the first dielectric oxide layer 31 surrounds the polysilicon electrode 41, and the longitudinal field plate is distributed in the whole second conduction type drift region 21 to form a longitudinal field plate array; and forming longitudinal field plates at the cathode end and the source end simultaneously by the same process as the longitudinal field plates in the drift region, wherein the longitudinal field plates penetrate through the second conductive type well region 22 and the second conductive type drift region 21 to the fourth dielectric oxide layer 34, penetrate through in the z direction simultaneously and are distributed on two sides of the low-voltage region as dielectric isolation grooves, and polysilicon electrodes 41 on the two sides of the low-voltage region are grounded; the longitudinal field plates distributed in the entire second conductivity type drift region 21 are equally spaced in the x direction and connected to the metal strip 51 through vias to form an intra-body equipotential ring; the horizontal direction from the cathode region to the anode region of the device is the x direction, the downward direction of the depth of the longitudinal field plate is the y direction, and the inward direction vertical to the xy plane is the z direction.
Preferably, the longitudinal field plate is formed simultaneously with the longitudinal field plates at the cathode end and the source end by the same process, the depth of the field plates is deeper than that of the second conductivity type drift region 21, and the longitudinal field plate is connected with the fourth dielectric buried oxide layer 34; and/or reducing the width of the etched dielectric isolation groove to enable an oxidation layer to completely fill the groove in the later groove wall oxidation process, and the longitudinal field plate of the cathode region becomes a full-dielectric groove.
Preferably, the longitudinal field plates adjacent to the heavily doped source region 13 of the first conductivity type and between the heavily doped drain region 24 of the second conductivity type and the heavily doped cathode region 15 of the first conductivity type are both grounded through a metal strip 51.
Preferably, the longitudinal and lateral spacings of adjacent longitudinal field plates distributed throughout the second conductivity type drift region 21 are equal; and/or the cross-sectional shape of the longitudinal field plate is rectangular, or circular, or oval, or hexagonal.
Preferably, the longitudinal field plates adjacent to the heavily doped source region 13 of the first conductivity type and between the heavily doped drain region 24 of the second conductivity type and the heavily doped cathode region 15 of the first conductivity type are both grounded by a metal strip 51.
Preferably, the vertical field plates for isolation are distributed on both sides of the low-voltage MOS and connected to the fourth dielectric buried oxide layer 34, and the vertical field plates simultaneously deplete the first conductivity type semiconductor substrate 11 and the second conductivity type drift region 21, and the vertical field plates connected to the fourth dielectric buried oxide layer 34 perform the isolation between high voltage and low voltage.
Preferably, the device is an SOI structure or a bulk silicon device, and the dielectric oxide layer of the device is silicon dioxide or a high-K or low-K material; besides silicon-based devices, the device structure is also applied to SiC and GaN semiconductor materials;
and/or the low voltage control circuit is a MOS, or a CMOS or other control loop; the high-voltage end lateral insulated gate bipolar transistor LIGBT is an N-type lateral insulated gate bipolar transistor N-LIGBT, or a P-type lateral insulated gate bipolar transistor P-LIGBT formed by compatible processes, or forms a CMOS circuit; the device is either an enhancement mode structure or an accumulation mode structure.
Preferably, a first conductive type doping layer is injected into the drift region, and the doping layer is positioned on the surface, or below the third dielectric oxide layer 33, or is in a discontinuous structure in the z direction;
or N-type injection is added in a channel region below the second dielectric oxide layer 32 of the high-voltage region LIGBT, so that the IGBT is in a normally-on state, namely the whole device is controlled by the gate voltage of the low-voltage region;
or a channel region below the second dielectric oxide layer 32 is formed without diffusion, namely the device has no channel and is an accumulation-type device;
or said heavy dopingHas a doping concentration of more than 1e18cm -3 。
The invention also provides a manufacturing method of the series double-gate LIGBT device, which comprises the following steps:
step 1: selecting an SOI material comprising a Si first conductivity type semiconductor substrate 11, a fourth dielectric buried oxide layer 34 and a second conductivity type drift region 21;
step 2: forming a groove by photolithography and etching;
and step 3: forming a first dielectric oxide layer 31 in the groove;
and 4, step 4: depositing polycrystal and etching to a silicon plane to form a polysilicon electrode 41;
and 5: ion-implanting first conductivity type impurities and pushing the junction to form a first conductivity type well region 12, ion-implanting second conductivity type impurities and pushing the junction to form a second conductivity type well region 22;
step 6: growing to form a third dielectric oxide layer 33, and then forming a second dielectric oxide layer 32 by etching;
and 7: depositing and etching polysilicon to form a control gate polysilicon electrode 42;
and 8: injecting to form a first conductive type heavily doped source region 13, a first conductive type heavily doped cathode region 15, a first conductive type heavily doped anode region 16, a second conductive type heavily doped region source region 23, a second conductive type heavily doped drain region 24 and a second conductive type heavily doped region cathode region 25;
and step 9: the third dielectric oxide layer 33 is etched to form a contact hole, and then the metal strip 51 is deposited and etched to form a surface metal strip and a metal electrode.
Preferably, the N-type doping in step 1 is a second conductivity type drift region 21 formed by implantation and junction push-off; and/or the first conductivity type well region 12 and the second conductivity type well region 22 obtained by implanting and pulling the junction in step 5 are formed by implanting and activating a plurality of times with different energies.
Preferably, when the first conductivity type heavily doped anode region 16 is formed, the second conductivity type heavily doped region anode region 26 is formed at the same time, that is, a reverse conducting IGBT structure is formed, and/or a longitudinal field plate closest to a cathode of the IGBT in the drift region of the device penetrates in the z direction to block holes injected from the collector to the emitter.
The beneficial effects of the invention are as follows: the vertical field plate introduces a global MIS depletion mechanism in the off state of the device to deplete the second conductivity type drift region 21. The field plates in the second conductivity type drift region 21 are connected by the metal strips 51 to form an in-body equipotential ring to modulate the electric field, so that the electric field distribution inside the device is uniform. The main innovation point is that a low-voltage control circuit MOS is formed at the cathode end of the IGBT by a compatible process, meanwhile, longitudinal field plate structures are manufactured on two sides of the low-voltage control circuit by the compatible process, the grids are connected, the same grid voltage controls two devices, and the longitudinal field plate is used as a medium isolation groove to carry out high-voltage and low-voltage isolation. And the MOS drain electrode is in short circuit with the IGBT cathode to form two devices which are connected in series and are respectively a low-voltage NMOS and a high-voltage IGBT. Because the two are connected in series, the total current of the device is the same, and the current of the MOS is the current of the IGBT, the current of the whole device can be limited by changing the current by changing the grid voltage of the low-voltage MOS, so that the parasitic p-n-p-n latch is controlled to be opened, the latch effect of the IGBT device can be well avoided, and the working characteristic of the IGBT is improved.
Drawings
Fig. 1 is a schematic diagram of a cell region structure of a tandem double-gate SOI LIGBT device in embodiment 1;
fig. 2 is a top view of a cell structure of a tandem double-gate SOI LIGBT device of embodiment 1;
fig. 3 is a schematic diagram of a cell region structure of a tandem double-gate silicon LIGBT device in embodiment 2;
fig. 4 is a schematic diagram of a cell region structure of a tandem double-gate SOI LIGBT device of embodiment 3;
fig. 5 is a schematic diagram of a cell region structure of a tandem double-gate silicon LIGBT device in embodiment 4;
FIG. 6 is a schematic diagram of a cell region structure of a tandem double-gate SOI LIGBT device in embodiment 5;
FIG. 7 is the top view of the cell structure of the tandem double gate SOI LIGBT device of embodiment 5;
FIG. 8 is a schematic diagram of a cell region structure of a tandem double-gate SOI LIGBT device in embodiment 6;
FIG. 9 is a top view of the cell region structure of the tandem double-gate SOI LIGBT device of embodiment 6;
fig. 10 is a schematic diagram of a cell region structure of a tandem double-gate SOI LIGBT device of embodiment 7;
fig. 11 is a schematic diagram of a cell region structure of a tandem double-gate SOI LIGBT device of embodiment 8;
fig. 12 is a schematic diagram of a cell region structure of a tandem double-gate SOI LIGBT device of embodiment 9;
FIGS. 13 (a) -13 (j) are schematic process flow diagrams of the device of example 1;
11 is a first conductive type semiconductor substrate, 12 is a first conductive type well region, 13 is a first conductive type heavily doped source region, 14 is a first conductive type heavily doped drain region, 15 is a first conductive type heavily doped cathode region, and 16 is a first conductive type heavily doped anode region; 21 is a drift region of the second conductivity type, 22 is a well region of the second conductivity type, 23 is a source region of a heavily doped region of the second conductivity type, 24 is a heavily doped drain region of the second conductivity type, 25 is a heavily doped cathode region of the second conductivity type, and 26 is a heavily doped anode region of the second conductivity type; 31 is a first dielectric oxide layer, 32 is a second dielectric oxide layer, 33 is a third dielectric oxide layer, and 34 is a fourth dielectric buried oxide layer; 41 is a polysilicon electrode, and 42 is a control gate polysilicon electrode; 51 is a metal strip, 52 is a source terminal metal, 53 is a drain terminal metal, 54 is a cathode region metal, and 55 is an anode region metal.
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
A tandem double-gate SOI LIGBT device described in embodiment 1, as shown in fig. 1-2, is divided into a low voltage part and a high voltage part:
the high-voltage part comprises: a fourth dielectric buried oxide layer 34 located above the first conductivity type semiconductor substrate 11, a second conductivity type drift region 21 located above the fourth dielectric oxide layer 34, a first conductivity type well region 12 located on the left side of the second conductivity type drift region 21, a second conductivity type well region 22 located on the right side of the second conductivity type drift region 21, a first conductivity type heavily doped cathode region 15 and a second conductivity type heavily doped cathode region 25 located in the first conductivity type well region 12; a cathode region metal 54 is located on the upper surfaces of the first conductivity type heavily doped cathode region 15 and the second conductivity type heavily doped cathode region 25, and an anode region metal 55 is located on the upper surface of the first conductivity type heavily doped anode region 16; the first conductive type heavily doped anode region 16 is located in the first conductive type well region 22; the second dielectric oxide layer 32 is located above the first conductive type well region 12, and the left end is in contact with the second conductive type heavily doped cathode region 25, and the right end is in contact with the second conductive type drift region 21; the third dielectric oxide layer 33 is located on the upper surface of the second conductive type drift region 21 between the second dielectric oxide layer 32 and the first conductive type heavily doped anode region 16; the control gate polysilicon electrode 42 covers the upper surface of the second dielectric oxide layer 32 and partially extends to the upper surface of the third dielectric oxide layer 33;
the low-pressure part includes: a first conductivity type well region 12, a first conductivity type heavily doped source region 13, a second conductivity type heavily doped source region 23, and a second conductivity type heavily doped drain region 24 located in the first conductivity type well region 12; the second dielectric oxide layer 32 is located above the first conductive type well region 12, and the left end is contacted with the second conductive type heavily doped source region 23, and the right end is contacted with the second conductive type heavily doped drain region 24; the control gate polysilicon electrode 42 covers the upper surface of the second dielectric oxide layer 32, the third dielectric oxide layer 33 is positioned above the polysilicon electrode 41, the drain metal 53 is positioned on the upper surface of the second conductive type drain heavily doped region 24, and the source metal 52 is positioned on the upper surfaces of the first conductive type heavily doped source region 13 and the second conductive type source heavily doped region 24;
the first dielectric oxide layer 31 and the polysilicon electrode 41 form a longitudinal field plate, the first dielectric oxide layer 31 surrounds the polysilicon electrode 41, and the longitudinal field plate is distributed in the whole second conduction type drift region 21 to form a longitudinal field plate array; and forming a longitudinal field plate at the cathode end and the source end at the same time by the same process as the longitudinal field plate in the drift region, wherein the longitudinal field plate penetrates through the second conductive type well region 22 and the second conductive type drift region 21 to the fourth dielectric oxide layer 34, the longitudinal field plate simultaneously penetrates in the z direction and is distributed at two sides of the low-voltage region as dielectric isolation grooves, and the polysilicon electrodes 41 at two sides of the low-voltage region are grounded; the longitudinal field plates distributed in the entire second conductivity type drift region 21 are equally spaced in the x direction and connected to the metal strip 51 through vias to form an intra-body equipotential ring; the horizontal direction from the cathode region to the anode region of the device is the x direction, the downward direction of the depth of the longitudinal field plate is the y direction, and the inward direction vertical to the xy plane is the z direction.
Heavily doped with a doping concentration greater than 1e18cm -3 。
The longitudinal field plate, the cathode end longitudinal field plate and the source end longitudinal field plate are formed simultaneously by the same process, the depth of the field plates is deeper than that of the second conduction type drift region 21, and the longitudinal field plate is connected with the fourth dielectric buried oxide layer 34;
the longitudinal and lateral spacings of adjacent longitudinal field plates distributed throughout the second conductivity type drift region 21 are equal; and/or the cross-sectional shape of the longitudinal field plate is rectangular, or circular, or oval, or hexagonal.
The medium isolation groove is arranged on two sides of the low-voltage MOS and penetrates through the low-voltage MOS in the z direction to play an isolation role.
The longitudinal field plates adjacent to the heavily doped source region 13 of the first conductivity type and between the heavily doped drain region 24 of the second conductivity type and the heavily doped cathode region 15 of the first conductivity type are both grounded by metal strips 51.
In this embodiment, the cross-sectional shape of the longitudinal field plates is square, and two adjacent rows of longitudinal field plates are staggered. The cross section shapes of the cathode end field plate and the source end field plate are rectangular, and the two rows of longitudinal field plates are arranged in parallel in the z direction.
The basic working principle is as follows:
taking the first conductive type semiconductor material as P type as an example, at the gate bias voltage V g When the value is 0, the vertical field plate introduces a global MIS depletion mechanism, and the metal strips 51 are connected to form an in-body equipotential ring to modulate the electric field, so that the electric field distribution in the device is uniform. A low-voltage control circuit MOS is manufactured at the cathode end of the IGBT by a compatible process, isolation is carried out by a medium isolation groove, the drain electrode of the MOS is in short circuit with the cathode of the IGBT, and the grid electrode of the MOS is connected to form a low-voltage MOS and a high-voltage IGBT which are connected in series. After the grid voltage is added, the MOS device is started and the IGBT is started, the drain current of the MOS is the same as the anode current of the IGBT, therefore, the current of the IGBT device can be limited by changing the grid voltage so as to inhibit the parasitic p-n-p-n latch of the IGBT from being started. In conclusion, the series double-gate LIGBT device provided by the invention solves the problem of gate runaway caused by latch opening of an IGBT due to too large anode current, and improves the gate control capability of the device.
As shown in fig. 13, is a schematic process flow diagram of embodiment 1 of the present invention, and specifically includes the following steps:
step 1: selecting an SOI material comprising a Si first conductivity type semiconductor substrate 11, a fourth dielectric buried oxide layer 34 and a second conductivity type drift region 21; as shown in fig. 13 (a);
step 2: forming a groove by photolithography and etching, as shown in fig. 13 (b);
and step 3: forming a first dielectric oxide layer 31 in the trench, as shown in fig. 13 (c);
and 4, step 4: depositing polycrystal and etching to a silicon plane to form a polysilicon electrode 41, as shown in fig. 13 (d) and 13 (e);
and 5: ion-implanting a first conductivity type impurity and pushing the junction to form a first conductivity type well region 12, and ion-implanting a second conductivity type impurity and pushing the junction to form a second conductivity type well region 22, as shown in fig. 13 (f);
step 6: growing to form a third dielectric oxide layer 33, and then forming a second dielectric oxide layer 32 by etching, as shown in fig. 13 (g);
and 7: depositing polysilicon and etching to form a control gate polysilicon electrode 42, as shown in fig. 13 (h);
and 8: and (e) implanting to form a first conductivity type heavily doped source region 13, a first conductivity type heavily doped cathode region 15, a first conductivity type heavily doped anode region 16, a second conductivity type heavily doped region source region 23, a second conductivity type heavily doped drain region 24 and a second conductivity type heavily doped region cathode region 25, as shown in fig. 13 (i).
And step 9: the third dielectric oxide layer 33 is etched to form contact holes, and then metal strips 51 are deposited and etched to form surface metal strips and metal electrodes, as shown in fig. 13 (j).
It should be noted that:
in the manufacturing method, in the step 1, the N-type silicon on insulator can be subjected to high-energy injection and then pushed to form the second conductive type drift region 21 through the undoped silicon wafer;
in the manufacturing method, the first conductive type well 12 and the second conductive type well 22 obtained by high-energy implantation and junction pushing in the step 5 can also be formed by multiple high-energy implantation and activation with different energies;
according to the manufacturing method, all the dielectric oxide layers can be formed through thermal growth or deposition and etching;
in the manufacturing method, the depth of the longitudinal field plate array of the dielectric isolation groove and the drift region can be above the buried oxide layer, can be on the surface of the buried oxide layer, and can also be in the buried oxide layer.
Example 2
As shown in fig. 3, this embodiment is a schematic diagram of a tandem double-gate SOI LIGBT device structure of embodiment 2, and the structure of this embodiment is different from that of embodiment 1 in that the device is a bulk silicon device instead of an SOI device, and the drift region is formed by high energy injection push well, the field plates are uniformly distributed in the drift region 21 of the second conductivity type, and the dielectric isolation trenches are on both sides of the MOS and inserted into the substrate, which basically has the same operation principle as that of embodiment 1.
Example 3
As shown in fig. 4, this embodiment is a schematic structural diagram of a tandem double-gate SOI LIGBT device in embodiment 3, and the difference between this embodiment and the structure in embodiment 1 is that a first conductivity-type doped layer is implanted into the drift region, and the doped layer may be on the surface, below the third dielectric oxide layer 33, or discontinuous in the z direction, and the x, y, and z directions are as shown in the attached drawing. The structure can assist in depletion of the drift region, provide holes and enhance the conductance modulation effect of the device, and the working principle is basically the same as that of embodiment 1.
Example 4
As shown in fig. 5, this example is a schematic diagram of a tandem double-gate silicon LIGBT device structure of example 4, which is different from the structure of example 1 in that, except for using bulk silicon material, the drift region field plate and the dielectric isolation trench of the cathode are inserted into the substrate, and the vertical field plate can simultaneously deplete the first conductivity type semiconductor substrate 11 and the second conductivity type drift region 21, and its operation principle is basically the same as that of example 1.
Example 5
As shown in fig. 6 and 7, which are schematic structural diagrams of a tandem double-gate SOI LIGBT device in embodiment 5, this example is different from the structure in embodiment 1 in that a longitudinal field plate closest to the IGBT cathode in the drift region of the device penetrates in the z direction, which blocks holes injected from the collector to the emitter, and a large number of holes are accumulated on one side of the longitudinal field plate closest to the IGBT cathode in the drift region, which further enhances the conductance modulation effect of the device, and reduces the on-resistance and on-voltage drop of the device, and the operating principle is substantially the same as that in embodiment 1, and meanwhile, the longitudinal field plate closest to the IGBT cathode in the drift region is compatible with the isolation trench process, i.e., the depth is the same.
Example 6
As shown in fig. 8 and 9, a schematic diagram and a top view of a cell region structure of a tandem double-gate SOI LIGBT device in embodiment 6 are shown, and the structure difference between this example and embodiment 1 is that the drain terminal also forms a longitudinal field plate through a compatible process, and simultaneously forms a second conductivity type heavily doped region anode region 26 when forming the first conductivity type heavily doped anode region 16, that is, a Reverse conductivity type IGBT structure RC-IGBT (Reverse Conducting IGBT) structure is formed, which has a bidirectional conduction capability, can enhance a conductance modulation effect of the device and shorten a turn-off time of the IGBT, and can control a z-direction pitch to control a snapback effect thereof, and the operating principle of the present example is substantially the same as that of embodiment 1.
Example 7
As shown in fig. 10, a schematic diagram of a tandem double-gate SOI LIGBT device structure in embodiment 7 is shown, and this example is different from the structure in embodiment 1 in that the trench is completely filled with an oxide layer in the late trench wall oxidation process by reducing the width of the etched dielectric isolation trench, and the longitudinal field plate in the cathode region becomes a full dielectric trench. The working principle is basically the same as that of embodiment 1.
Example 8
As shown in fig. 11, a schematic diagram of a tandem double-gate SOI LIGBT device structure in embodiment 8 is shown, and this example is different from the structure in embodiment 1 in that an N-type implant is added in a channel region under the second dielectric oxide layer 32 of the LIGBT in the high voltage region, so that the IGBT is in a normally-on state, that is, the whole device is controlled by the gate voltage in the low voltage region. The working principle is basically the same as that of embodiment 1.
Example 9
As shown in fig. 12, this embodiment is a schematic structural diagram of a tandem double-gate SOI LIGBT device in embodiment 9, and the structure of this embodiment is different from that in embodiment 1 in that LIGBT does not form a channel region by diffusion, that is, the device is an accumulation-type device without an inversion channel, and the whole device is controlled by a low-voltage gate voltage. The working principle is basically the same as that of embodiment 1.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes be made by those skilled in the art without departing from the spirit and technical spirit of the present invention, and be covered by the appended claims.
Claims (10)
1. A series double-gate LIGBT device is characterized in that the device is divided into a low-voltage part and a high-voltage part:
the high voltage part includes: a fourth dielectric buried oxide layer (34) positioned above the first conductive type semiconductor substrate (11), a second conductive type drift region (21) positioned above the fourth dielectric oxide layer (34), a first conductive type well region (12) positioned on the left side of the second conductive type drift region (21), a second conductive type well region (22) positioned on the right side of the second conductive type drift region (21), and a first conductive type heavily doped cathode region (15) and a second conductive type heavily doped cathode region (25) positioned in the first conductive type well region (12); the cathode region metal (54) is positioned on the upper surfaces of the first conduction type heavily doped cathode region (15) and the second conduction type heavily doped cathode region (25), and the anode region metal (55) is positioned on the upper surface of the first conduction type heavily doped anode region (16); a first conductivity type heavily doped anode region (16) is located in the first conductivity type well region (22); the second dielectric oxide layer (32) is positioned above the first conduction type well region (12), the left end of the second dielectric oxide layer is contacted with the second conduction type heavily doped cathode region (25), and the right end of the second dielectric oxide layer is contacted with the second conduction type drift region (21); the third dielectric oxide layer (33) is positioned on the upper surface of the second conduction type drift region (21) between the second dielectric oxide layer (32) and the first conduction type heavily doped anode region (16); the control gate polysilicon electrode (42) covers the upper surface of the second dielectric oxide layer (32) and partially extends to the upper surface of the third dielectric oxide layer (33);
the low pressure part includes: the semiconductor device comprises a first conduction type well region (12), a first conduction type heavily doped source region (13), a second conduction type heavily doped source region (23) and a second conduction type heavily doped drain region (24) which are positioned in the first conduction type well region (12); the second dielectric oxide layer (32) is positioned above the first conduction type well region (12), the left end of the second dielectric oxide layer is contacted with the second conduction type heavily doped source region (23), and the right end of the second dielectric oxide layer is contacted with the second conduction type heavily doped drain region (24); the control gate polysilicon electrode (42) covers the upper surface of the second dielectric oxide layer (32), and the third dielectric oxide layer (33) is positioned above the polysilicon electrode (41); drain end metal (53) is positioned on the upper surface of the second conduction type drain end heavily doped region (24), and source end metal (52) is positioned on the upper surfaces of the first conduction type source end heavily doped region (13) and the second conduction type source end heavily doped region (24);
the first dielectric oxide layer (31) and the polysilicon electrode (41) form a longitudinal field plate, the first dielectric oxide layer (31) surrounds the polysilicon electrode (41), and the longitudinal field plate is distributed in the whole second conduction type drift region (21) to form a longitudinal field plate array; and forming a longitudinal field plate on the cathode end and the source end at the same time by the same process as the longitudinal field plate in the drift region, wherein the longitudinal field plate penetrates through the second conduction type well region (22) and the second conduction type drift region (21) to the fourth dielectric oxide layer (34), penetrates through the longitudinal field plate in the z direction at the same time, is distributed on two sides of the low-voltage region as dielectric isolation grooves, and polysilicon electrodes (41) on two sides of the low-voltage region are grounded; longitudinal field plates distributed in the whole second conduction type drift region (21) are distributed at equal intervals in the x direction and are connected with the metal strips (51) through holes to form in-vivo equipotential rings; the horizontal direction from the cathode region to the anode region of the device is the x direction, the downward direction of the depth of the longitudinal field plate is the y direction, and the inward direction vertical to the xy plane is the z direction.
2. The tandem double-gate LIGBT device as claimed in claim 1, wherein: the longitudinal field plate, the cathode end and the source end are formed simultaneously by the same process, the depth of the field plate is deeper than that of the second conduction type drift region (21), and the longitudinal field plate is connected with a fourth medium buried oxide layer (34); and/or reducing the width of the etched dielectric isolation groove to enable an oxidation layer to completely fill the groove in the later groove wall oxidation process, and the longitudinal field plate of the cathode region becomes a full-dielectric groove.
3. The tandem double-gate LIGBT device as claimed in claim 1, wherein: the longitudinal and lateral spacings of adjacent longitudinal field plates distributed throughout the second conductivity type drift region (21) are equal; and/or the cross-sectional shape of the longitudinal field plate is rectangular, or circular, or oval, or hexagonal.
4. The tandem double-gate LIGBT device of claim 1, wherein: the longitudinal field plate close to the first conductivity type heavily doped source region (13) and the longitudinal field plate between the second conductivity type heavily doped drain region (24) and the first conductivity type heavily doped cathode region (15) are both grounded through a metal strip (51).
5. The tandem double-gate LIGBT device as claimed in claim 1, wherein: the longitudinal field plates with the isolation function are distributed on two sides of the low-voltage MOS and are connected with the fourth medium buried oxide layer (34), the longitudinal field plates simultaneously deplete the first conduction type semiconductor substrate (11) and the second conduction type drift region (21), and the longitudinal field plates connected with the fourth medium buried oxide layer (34) have the high-voltage and low-voltage isolation function.
6. The tandem double-gate LIGBT device as claimed in claim 1, wherein: the device is an SOI structure or a bulk silicon device, and a dielectric oxidation layer of the device is silicon dioxide or a high-K or low-K material; besides silicon-based devices, the device structure is also applied to SiC and GaN semiconductor materials;
and/or the low voltage control circuit is MOS, or CMOS or other control loop; the high-voltage end transverse insulated gate bipolar transistor LIGBT is an N-type transverse insulated gate bipolar transistor N-LIGBT, or a P-type transverse insulated gate bipolar transistor P-LIGBT formed by compatible processes, or forms a CMOS circuit; the device is either an enhancement mode structure or an accumulation mode structure.
7. The tandem double-gate LIGBT device as claimed in claim 1, wherein:
a first conductive type doping layer is injected into the drift region, and the doping layer is positioned on the surface, or below a third medium oxidation layer (33), or is in a discontinuous structure in the z direction;
or N-type injection is added in a channel region below a second dielectric oxide layer (32) of the high-voltage region LIGBT, so that the IGBT is in a normally-on state, namely the whole device is controlled by the gate voltage of the low-voltage region;
or a channel region below the second medium oxidation layer (32) is formed without diffusion, namely the device has no channel and is an accumulation type device;
or the weightDoping concentration of the doping is more than 1e18cm -3 。
8. A method for manufacturing a tandem double gate LIGBT device as claimed in any one of claims 1 to 5, comprising the steps of:
step 1: selecting an SOI material comprising a Si first conductivity type semiconductor substrate (11), a fourth dielectric buried oxide layer (34) and a second conductivity type drift region (21);
and 2, step: forming a groove by photolithography and etching;
and 3, step 3: forming a first dielectric oxide layer (31) in the groove;
and 4, step 4: depositing polycrystal and etching to a silicon plane to form a polysilicon electrode (41);
and 5: ion-implanting first conductivity type impurities and pushing the junction to form a first conductivity type well region (12), and ion-implanting second conductivity type impurities and pushing the junction to form a second conductivity type well region (22);
step 6: growing to form a third dielectric oxide layer (33), and then forming a second dielectric oxide layer (32) by etching;
and 7: depositing polysilicon and etching to form a control gate polysilicon electrode (42);
and 8: implanting to form a first conductive type heavily doped source region (13), a first conductive type heavily doped cathode region (15), a first conductive type heavily doped anode region (16), a second conductive type heavily doped region source region (23), a second conductive type heavily doped drain region (24) and a second conductive type heavily doped region cathode region (25);
and step 9: the third dielectric oxide layer (33) is etched to form contact holes, and then metal strips (51) are deposited and etched to form surface metal strips and metal electrodes.
9. The method of claim 8, wherein the method further comprises: the N-type doping in the step 1 is a second conductive type drift region (21) formed by implantation and junction pushing; and/or the first conductivity type well region (12) and the second conductivity type well region (22) obtained by implanting and pushing the junction in step 5 are formed by implanting and activating a plurality of times with different energies.
10. The method of claim 8, wherein the method further comprises: when the first conductive type heavily doped anode region (16) is formed, the second conductive type heavily doped region anode region (26) is formed at the same time, namely, a reverse conducting IGBT structure is formed;
and/or penetrating a longitudinal field plate closest to an IGBT cathode in the drift region of the device in the z direction to block holes injected from a collector to an emitter.
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