CN111403292B - Manufacturing method of self-aligned contact hole shielding gate power MOSFET device and formed device - Google Patents
Manufacturing method of self-aligned contact hole shielding gate power MOSFET device and formed device Download PDFInfo
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- CN111403292B CN111403292B CN202010342072.XA CN202010342072A CN111403292B CN 111403292 B CN111403292 B CN 111403292B CN 202010342072 A CN202010342072 A CN 202010342072A CN 111403292 B CN111403292 B CN 111403292B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 87
- 229920005591 polysilicon Polymers 0.000 claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention relates to a manufacturing method of a self-aligned contact hole shielding grid power MOSFET device, which comprises the steps of forming a well region on the surface of a substrate, forming a groove in the substrate, forming a shielding grid dielectric layer at the bottom and the side surface of the groove, filling gaps among shielding grid dielectric layers by first polysilicon, forming a third dielectric layer covering the first polysilicon and the shielding grid dielectric layer, forming a second grid dielectric layer on the exposed silicon surface in the groove, forming second polysilicon filling gaps among the grooves, carrying out back etching on the first dielectric layer in the horizontal direction to form a source region, forming a fourth dielectric layer, forming a first contact hole of which the bottom is exposed by the second polysilicon, forming a second contact hole of which the bottom is exposed by the first dielectric layer positioned at one side of the groove, removing the exposed first dielectric layer, forming a contact region at the bottom of the second contact hole, carrying out back etching on the fourth dielectric layer in the horizontal direction, forming an enlarged first contact hole and an enlarged second contact hole, and forming a metal contact to form a source electrode and a grid electrode.
Description
Technical Field
The invention relates to a semiconductor manufacturing process, in particular to a manufacturing method of a self-aligned contact hole shielding gate power MOSFET device.
Background
The shielded gate power moset device is a common device for semiconductor integrated circuits. In the fabrication of semiconductor integrated circuits, device size reduction is desired as technology nodes for semiconductor fabrication continue to advance.
For a common shielded gate power MOSTET device, a contact hole is often drilled at the top of a polysilicon and a source region to lead the polysilicon and the source region out to form a gate and a source, but the photolithography technique has the minimum photolithographic line width and the registration deviation, so that the photolithographic etching of the polysilicon and the source region contact hole needs to consider the registration deviation, and when the widths of the polysilicon and the source region do not meet the registration deviation, the risk of causing the connection deviation and even short circuit between the contact hole and the polysilicon and the source region exists, thereby influencing the performance of the device. In addition, a certain margin must be reserved for the device size to compensate for the alignment deviation in the photoetching process and meet the requirements of the device channel and performance.
Disclosure of Invention
The invention provides a manufacturing method of a self-aligned contact hole shielding gate power MOSFET device, which comprises the following steps: s1: providing a semiconductor substrate, forming a first conductive type epitaxial layer on the surface of the semiconductor substrate, and performing ion implantation to form a well region of a second conductive type on the surface of the semiconductor substrate; s2: sequentially forming a first gate dielectric layer, a first dielectric layer and a second dielectric layer, photoetching to form a groove pattern, removing the first gate dielectric layer, the first dielectric layer and the second dielectric layer on the silicon surface of the groove pattern area, and performing a groove silicon etching process by taking the first dielectric layer and the second dielectric layer as hard mask layers to form a groove in the semiconductor substrate; s3: forming a shielding gate dielectric layer on the bottom surface and the side surface of the groove, wherein the shielding gate dielectric layer does not completely fill the groove and forms a gap region in the central region of the groove; s4: depositing polysilicon in the groove to form first polysilicon so as to completely fill a gap area in the groove, and carrying out first polysilicon back etching to etch away part of the first polysilicon in the groove; s5: forming a third dielectric layer, enabling the third dielectric layer to cover the side wall of the groove and the upper parts of the first polysilicon and the shielding gate dielectric layer, removing the third dielectric layer covering the side wall of the groove, only remaining the third dielectric layer covering the upper parts of the first polysilicon and the shielding gate dielectric layer, and removing the second dielectric layer on the first dielectric layer; s6: forming a second gate dielectric layer on the exposed silicon surface in the groove, depositing polysilicon in the groove to form second polysilicon, completely filling gaps in the groove, and carrying out second polysilicon back etching; s7: carrying out back etching on the first dielectric layer in the horizontal direction to form a source region injection region, and carrying out source region injection to respectively form source regions in the well regions at the two sides of the groove; s8: forming a fourth dielectric layer, and enabling the fourth dielectric layer to cover the surfaces of the first dielectric layer, the first gate dielectric layer, the second gate dielectric layer and the second polysilicon; s9: performing photoetching to form a first contact hole and a second contact hole, wherein the bottom of the first contact hole exposes the second polysilicon, and the bottom of the second contact hole exposes the first dielectric layer positioned on at least one side of the groove; s10: removing the exposed first dielectric layer, injecting a contact hole to form a well region contact region heavily doped with the second conductivity type at the bottom of the second contact hole, carrying out back etching on the fourth dielectric layer in the horizontal direction, further expanding the first contact hole to form an expanded first contact hole, further expanding the second contact hole to expose the source region to form an expanded second contact hole, and removing the first gate dielectric layer at the bottom of the expanded second contact hole; s11: forming a front metal layer, wherein the front metal layer covers the fourth dielectric layer, fills the enlarged first contact hole and the enlarged second contact hole, and performs photoetching on the front metal layer to form a source electrode and a grid electrode, wherein the source electrode is contacted with the source region through the enlarged second contact hole, and the grid electrode is contacted with the second polysilicon through the enlarged first contact hole.
Further, a thickness of the third dielectric layer spaces the first polysilicon and the second polysilicon apart from each other.
Furthermore, the shielded gate trench power MOSTET device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, and the semiconductor substrate is N-type doped.
Furthermore, the shielded gate trench power MOSTET device is a P-type device, the first conductive type is P-type, the second conductive type is N-type, and the semiconductor substrate is P-type doped.
Further, in step S4, the remaining first polysilicon is located in the semiconductor substrate under the well region.
Further, the first dielectric layer is a silicon nitride layer.
Further, the second dielectric layer, the first gate dielectric layer, the shielding gate dielectric layer, the third dielectric layer, the second gate dielectric layer and the fourth dielectric layer are oxide layers.
Further, in step S6, the second polysilicon is etched back to remove the second polysilicon outside the trench.
Further, the thickness of the third dielectric layer enables no electric leakage to occur between the first polysilicon and the second polysilicon.
The invention also provides a self-aligned contact hole shielding grid power MOSFET device, which is manufactured according to the manufacturing method of the self-aligned contact hole shielding grid power MOSFET device.
The method for manufacturing the self-aligned contact hole shielding grid power MOSFET device comprises the steps of forming a well region on the surface of a substrate, forming a groove in the substrate, forming a shielding grid dielectric layer at the bottom and the side face of the groove, filling gaps among shielding grid dielectric layers by first polycrystalline silicon, forming a third dielectric layer covering the upper parts of the first polycrystalline silicon and the shielding grid dielectric layer, forming a second grid dielectric layer on the exposed silicon surface in the groove, forming second polycrystalline silicon filling gaps among the grooves, performing back etching on the first dielectric layer in the horizontal direction to form a source region, forming a fourth dielectric layer, forming a first contact hole of the bottom exposing the second polycrystalline silicon, forming a second contact hole of the bottom exposing the first dielectric layer at one side of the groove, removing the exposed first dielectric layer, forming a contact region at the bottom of the second contact hole, performing back etching on the fourth dielectric layer in the horizontal direction, forming an enlarged first contact hole and an enlarged second contact hole, forming a metal contact to form a source electrode and a grid electrode, and enabling the device to be high in reliability and small in size.
Drawings
Fig. 1-12 are schematic views of devices during the fabrication of a self-aligned contact-hole shielded gate power MOSFET according to an embodiment of the invention.
The main element reference numerals in the drawings are explained as follows:
110. a semiconductor substrate; 130. a groove; 124. a shielding gate dielectric layer; 131. a first polysilicon; 125. a third dielectric layer; 132. a second polysilicon; 111. a well region; 126. a second gate dielectric layer; 140. a source region; 160. a well region contact region; 121. a first gate dielectric layer; 122. a first dielectric layer; 127. a fourth dielectric layer; 172. a gate; 171. a source electrode; 151a, enlarged first contact holes; 152a, enlarged second contact holes.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In one embodiment of the present invention, a method for manufacturing a self-aligned contact hole shielding gate power MOSFET device is provided, including: s1: providing a semiconductor substrate, forming a first conductive type epitaxial layer on the surface of the semiconductor substrate, and performing ion implantation to form a well region of a second conductive type on the surface of the semiconductor substrate; s2: sequentially forming a first gate dielectric layer, a first dielectric layer and a second dielectric layer, photoetching to form a groove pattern, removing the first gate dielectric layer, the first dielectric layer and the second dielectric layer on the silicon surface of the groove pattern area, and performing a groove silicon etching process by taking the first dielectric layer and the second dielectric layer as hard mask layers to form a groove in the semiconductor substrate; s3: forming a shielding gate dielectric layer on the bottom surface and the side surface of the groove, wherein the shielding gate dielectric layer does not completely fill the groove and forms a gap region in the central region of the groove; s4: depositing polysilicon in the groove to form first polysilicon so as to completely fill a gap area in the groove, and carrying out first polysilicon back etching to etch away part of the first polysilicon in the groove; s5: forming a third dielectric layer, enabling the third dielectric layer to cover the side wall of the groove and the upper parts of the first polysilicon and the shielding gate dielectric layer, removing the third dielectric layer covering the side wall of the groove, only remaining the third dielectric layer covering the upper parts of the first polysilicon and the shielding gate dielectric layer, and removing the second dielectric layer on the first dielectric layer; s6: forming a second gate dielectric layer on the exposed silicon surface in the groove, depositing polysilicon in the groove to form second polysilicon, completely filling gaps in the groove, and carrying out second polysilicon back etching; s7: carrying out back etching on the first dielectric layer in the horizontal direction to form a source region injection region, and carrying out source region injection to respectively form source regions in the well regions at the two sides of the groove; s8: forming a fourth dielectric layer, and enabling the fourth dielectric layer to cover the surfaces of the first dielectric layer, the first gate dielectric layer, the second gate dielectric layer and the second polysilicon; s9: performing photoetching to form a first contact hole and a second contact hole, wherein the bottom of the first contact hole exposes the second polysilicon, and the bottom of the second contact hole exposes the first dielectric layer positioned on at least one side of the groove; s10: removing the exposed first dielectric layer, injecting a contact hole to form a well region contact region heavily doped with the second conductivity type at the bottom of the second contact hole, carrying out back etching on the fourth dielectric layer in the horizontal direction, further expanding the first contact hole to form an expanded first contact hole, further expanding the second contact hole to expose the source region to form an expanded second contact hole, and removing the first gate dielectric layer at the bottom of the expanded second contact hole; s11: forming a front metal layer, wherein the front metal layer covers the fourth dielectric layer, fills the enlarged first contact hole and the enlarged second contact hole, and performs photoetching on the front metal layer to form a source electrode and a grid electrode, wherein the source electrode is contacted with the source region through the enlarged second contact hole, and the grid electrode is contacted with the second polysilicon through the enlarged first contact hole.
More particularly, referring to fig. 1 to 12, fig. 1 to 12 are schematic views of devices in a manufacturing process of a self-aligned contact hole shielding gate power MOSFET according to an embodiment of the invention. The manufacturing method of the self-aligned contact hole shielding gate power MOSFET device comprises the following steps:
s1: as shown in fig. 1, a semiconductor substrate 110 is provided, an epitaxial layer of a first conductivity type is formed on the surface of the semiconductor substrate 110, and ion implantation is performed to form a well region 111 of a second conductivity type on the surface of the semiconductor substrate 110.
In one embodiment, the semiconductor substrate 110 is a silicon substrate.
S2: as shown in fig. 2, a first gate dielectric layer 121, a first dielectric layer 122 and a second dielectric layer 123 are sequentially formed, a trench pattern is formed by photolithography, the first gate dielectric layer 121, the first dielectric layer 122 and the second dielectric layer 123 on the silicon surface of the trench pattern region are removed, and a trench silicon etching process is performed by using the first dielectric layer 122 and the second dielectric layer 123 as hard mask layers, so as to form a trench 130 in the semiconductor substrate 110.
In one embodiment, the first dielectric layer 122 is a silicon nitride layer, and the second dielectric layer 123 is an oxide layer, such as a silicon oxide layer.
In one embodiment, the first gate dielectric layer 121 is an oxide layer, such as a silicon oxide layer.
S3: as shown in fig. 3, a shield gate dielectric layer 124 is formed on the bottom surface and the side surfaces of the trench 130, and the shield gate dielectric layer 124 does not completely fill the trench 130 but forms a gap region in the central region of the trench 130.
In one embodiment, the shield gate dielectric layer 124 is an oxide layer, such as a silicon oxide layer.
S4: as shown in fig. 4, polysilicon is deposited in the trench 130 to form a first polysilicon 131, so that the gap region in the trench 130 is completely filled, as shown in fig. 5, and the first polysilicon 131 is etched back to etch away a portion of the first polysilicon 131 in the trench 130.
In one embodiment, the remaining first polysilicon 131 is located within the semiconductor substrate 110 below the well region 111.
S5: as shown in fig. 6, the third dielectric layer 125 is formed such that the third dielectric layer 125 covers the sidewalls of the trench 130 and the upper sides of the first polysilicon 131 and the shield gate dielectric layer 124, and the third dielectric layer 125 covering the sidewalls of the trench 130 is removed, and only the third dielectric layer 125 covering the upper sides of the first polysilicon 131 and the shield gate dielectric layer 124 remains, and the second dielectric layer 123 on the first dielectric layer 122 is removed.
In one embodiment, the third dielectric layer 125 is an oxide layer, such as a silicon oxide layer. In an embodiment, the third dielectric layer 125 is made of the same material as the shielding gate dielectric layer 124.
S6: as shown in fig. 7, a second gate dielectric layer 126 is formed on the exposed silicon surface in the trench 130, polysilicon is deposited in the trench 130 to form a second polysilicon 132, so that the gap in the trench 130 is completely filled, and the second polysilicon 132 is etched back.
In one embodiment, the second polysilicon 132 is etched back to etch away the second polysilicon 132 outside the trench 130.
In one embodiment, the second gate dielectric layer 126 is an oxide layer, such as a silicon oxide layer.
S7: as shown in fig. 8, the first dielectric layer 122 is etched back in the horizontal direction to form source region implantation regions, and source region implantation is performed to form source regions 140 in the well regions 111 on both sides of the trench 130, respectively.
In one embodiment, the source region 140 is a heavily doped region of the first conductivity type.
S8: as shown in fig. 9, a fourth dielectric layer 127 is formed such that the fourth dielectric layer 127 covers the surfaces of the first dielectric layer 122, the first gate dielectric layer 121, the second gate dielectric layer 126, and the second polysilicon 132.
In one embodiment, the fourth dielectric layer 127 is an oxide layer, such as a silicon oxide layer. In one embodiment, the fourth dielectric layer 127 is made of the same material as the shielding gate dielectric layer 124.
S9: as shown in fig. 10, a first contact hole 151 and a second contact hole 152 are formed by photolithography, wherein the bottom of the first contact hole 151 exposes the second polysilicon 132, and the bottom of the second contact hole 152 exposes the first dielectric layer 122 located on at least one side of the trench 130.
S10: as shown in fig. 11, the exposed first dielectric layer 122 is removed, a contact hole is implanted to form a well region contact region 160 heavily doped with the second conductivity type at the bottom of the second contact hole 152, the fourth dielectric layer 127 is etched back in the horizontal direction, the first contact hole 151 is further enlarged to form an enlarged first contact hole 151a, the second contact hole 152 is further enlarged to expose the source region 140 to form an enlarged second contact hole 152a, and the first gate dielectric layer 121 at the bottom of the enlarged second contact hole 152a is removed.
At this time, the enlarged second contact hole 152a can be simultaneously contacted with the source region 140 and the well region contact region 160 without etching the surface of the semiconductor substrate 110.
S11: as shown in fig. 12, a front metal layer is formed, the front metal layer covers the fourth dielectric layer 127 and fills the enlarged first contact hole 151a and the enlarged second contact hole 152a, and the front metal layer is subjected to photolithography etching to form a source electrode 171 and a gate electrode 172, wherein the source electrode 171 is in contact with the source region 140 through the enlarged second contact hole 152a, and the gate electrode 172 is in contact with the second polysilicon 132 through the enlarged first contact hole 151 a.
In one embodiment of the present invention, the thickness of the third dielectric layer 125 is such that the first polysilicon 131 and the second polysilicon 132 are spaced apart from each other. Further, the thickness of the third dielectric layer 125 is such that no leakage occurs between the first polysilicon 131 and the second polysilicon 132.
In an embodiment of the present invention, there is no need to consider the photolithographic and etching registration deviation of the polysilicon and the source region contact hole, and as described above, even if there is a registration deviation, the source electrode can be fully contacted with the source region and the well region contact region, and the gate electrode can be fully contacted with the second polysilicon without causing the problem of connection deviation of the contact hole with the polysilicon and the source region. In addition, the device size does not need to be allowance for the alignment deviation, so that the device size can be reduced. The contact hole corresponding to the source electrode does not need to penetrate through the source region to form connection, namely the enlarged second contact hole is connected with the source region and the well region contact region through surface contact, so that the process of the invention is simpler.
In one embodiment, the gate trench power mosfet device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, and the semiconductor substrate 110 is N-doped. In one embodiment, the shielded gate trench power mosfet device is a P-type device, the first conductivity type is P-type, the second conductivity type is N-type, and the semiconductor substrate 110 is P-type doped.
In an embodiment of the present invention, a self-aligned contact-hole shielded gate power MOSFET device is provided, which is formed by the above-mentioned method for manufacturing a self-aligned contact-hole shielded gate power MOSFET device.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. A method of fabricating a self-aligned contact shield gate power MOSFET device comprising:
s1: providing a semiconductor substrate, forming a first conductive type epitaxial layer on the surface of the semiconductor substrate, and performing ion implantation to form a well region of a second conductive type on the surface of the semiconductor substrate;
s2: sequentially forming a first gate dielectric layer, a first dielectric layer and a second dielectric layer, photoetching to form a groove pattern, removing the first gate dielectric layer, the first dielectric layer and the second dielectric layer on the silicon surface of the groove pattern area, and performing a groove silicon etching process by taking the first dielectric layer and the second dielectric layer as hard mask layers to form a groove in the semiconductor substrate;
s3: forming a shielding gate dielectric layer on the bottom surface and the side surface of the groove, wherein the shielding gate dielectric layer does not completely fill the groove and forms a gap region in the central region of the groove;
s4: depositing polysilicon in the groove to form first polysilicon so as to completely fill a gap area in the groove, and carrying out first polysilicon back etching to etch away part of the first polysilicon in the groove;
s5: forming a third dielectric layer, enabling the third dielectric layer to cover the side wall of the groove and the upper parts of the first polysilicon and the shielding gate dielectric layer, removing the third dielectric layer covering the side wall of the groove, only remaining the third dielectric layer covering the upper parts of the first polysilicon and the shielding gate dielectric layer, and removing the second dielectric layer on the first dielectric layer;
s6: forming a second gate dielectric layer on the exposed silicon surface in the groove, depositing polysilicon in the groove to form second polysilicon, completely filling gaps in the groove, and carrying out second polysilicon back etching;
s7: carrying out back etching on the first dielectric layer in the horizontal direction to form a source region injection region, and carrying out source region injection to respectively form source regions in the well regions at the two sides of the groove;
s8: forming a fourth dielectric layer, and enabling the fourth dielectric layer to cover the surfaces of the first dielectric layer, the first gate dielectric layer, the second gate dielectric layer and the second polysilicon;
s9: performing photoetching to form a first contact hole and a second contact hole, wherein the bottom of the first contact hole exposes the second polysilicon, and the bottom of the second contact hole exposes the first dielectric layer positioned on at least one side of the groove;
s10: removing the exposed first dielectric layer, injecting a contact hole to form a well region contact region heavily doped with the second conductivity type at the bottom of the second contact hole, carrying out back etching on the fourth dielectric layer in the horizontal direction, further expanding the first contact hole to form an expanded first contact hole, further expanding the second contact hole to expose the source region to form an expanded second contact hole, and removing the first gate dielectric layer at the bottom of the expanded second contact hole; and
s11: forming a front metal layer, wherein the front metal layer covers the fourth dielectric layer, fills the enlarged first contact hole and the enlarged second contact hole, and performs photoetching on the front metal layer to form a source electrode and a grid electrode, wherein the source electrode is contacted with the source region through the enlarged second contact hole, and the grid electrode is contacted with the second polysilicon through the enlarged first contact hole.
2. The method of manufacturing a self-aligned contact shield gate power MOSFET device of claim 1, wherein a thickness of the third dielectric layer spaces the first polysilicon and the second polysilicon apart from each other.
3. The method of claim 1, wherein the shielded gate trench power MOSFET device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, and the semiconductor substrate is N-doped.
4. The method of claim 1, wherein the shielded gate trench power MOSFET device is a P-type device, the first conductivity type is P-type, the second conductivity type is N-type, and the semiconductor substrate is P-doped.
5. The method of fabricating a self-aligned contact shielded gate power MOSFET device of claim 1, wherein in step S4, the remaining first polysilicon is located within the semiconductor substrate below the well region.
6. The method of fabricating a self-aligned contact shielded gate power MOSFET device of claim 1, wherein the first dielectric layer is a silicon nitride layer.
7. The method of manufacturing a self-aligned contact hole shielded gate power MOSFET device of claim 1, wherein the second dielectric layer, the first gate dielectric layer, the shielded gate dielectric layer, the third dielectric layer, the second gate dielectric layer, and the fourth dielectric layer are oxide layers.
8. The method of claim 1, wherein in step S6, the second polysilicon is etched back to remove the second polysilicon outside the trench.
9. The method of claim 1, wherein the thickness of the third dielectric layer is such that no leakage occurs between the first polysilicon and the second polysilicon.
10. A self-aligned contact-hole shielded gate power MOSFET device, characterized in that it is manufactured according to the manufacturing method of the self-aligned contact-hole shielded gate power MOSFET device according to any one of claims 1 to 9.
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| CN112201583B (en) * | 2020-10-27 | 2024-02-27 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing MOSFET device containing SGT structure |
| CN113241372B (en) * | 2021-05-19 | 2022-09-06 | 深圳真茂佳半导体有限公司 | Preparation method and structure of self-aligned power field effect transistor |
| CN114093767A (en) * | 2021-07-28 | 2022-02-25 | 上海晶岳电子有限公司 | Manufacturing method of SGT MOS device with self-aligned contact structure |
| CN113782585B (en) * | 2021-08-05 | 2024-01-23 | 上海华虹宏力半导体制造有限公司 | MOSFET device with shielding gate structure and manufacturing method thereof |
| CN113782432A (en) * | 2021-08-05 | 2021-12-10 | 上海华虹宏力半导体制造有限公司 | Semiconductor device with trench type shielding structure and method of manufacturing the same |
| CN114023811B (en) * | 2021-10-20 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | Shielded gate trench type MOSFET device and manufacturing method thereof |
| CN114023812B (en) * | 2021-10-20 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | Shielded gate trench type MOSFET device and manufacturing method thereof |
| CN115148739A (en) * | 2022-06-27 | 2022-10-04 | 上海华力集成电路制造有限公司 | Method for forming static random access memory |
| CN115148670B (en) * | 2022-07-05 | 2023-06-13 | 上海功成半导体科技有限公司 | Shielded gate trench MOSFET structure and preparation method thereof |
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