CN109119477B - Trench gate MOSFET and manufacturing method thereof - Google Patents

Trench gate MOSFET and manufacturing method thereof Download PDF

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Publication number
CN109119477B
CN109119477B CN201810984537.4A CN201810984537A CN109119477B CN 109119477 B CN109119477 B CN 109119477B CN 201810984537 A CN201810984537 A CN 201810984537A CN 109119477 B CN109119477 B CN 109119477B
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opening
trench
region
gate
dielectric layer
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CN109119477A (en
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石磊
缪进征
范让萱
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Abstract

The invention discloses a trench gate MOSFET.A plurality of trenches penetrating through a well region are formed in a semiconductor substrate; the width of the groove is defined by a first opening, and the first opening is formed by photoetching and etching a hard mask layer; filling a polysilicon gate consisting of polysilicon in the groove; filling a first dielectric layer in the first opening at the top of the polysilicon gate, and removing the hard mask layer between the first openings under the self-alignment definition of the first dielectric layer to form a second opening; a first inner side wall is formed on the inner side surface of the second opening in a self-aligning mode, and the second opening is reduced into a third opening by the first inner side wall; the bottom of the third opening also penetrates through the source region and extends into the well region, and the third opening is filled with a metal layer so as to form a source contact hole in a self-alignment mode at the top of the source region. The invention discloses a manufacturing method of a trench gate MOSFET. The invention reduces the step size among all unit structures of the device, thereby improving the integration level of the trench gate MOSFET.

Description

Trench gate MOSFET and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench gate MOSFET; the invention also relates to a manufacturing method of the trench gate MOSFET.
Background
Fig. 1A to 1L are schematic views of device structures in steps of a conventional trench gate MOSFET manufacturing method; the manufacturing method of the existing trench gate MOSFET comprises the following steps:
step one, as shown in fig. 1A, providing a semiconductor substrate such as a silicon substrate 101; the hard mask layer 102 is formed on the surface of the semiconductor substrate 101, and the hard mask layer 102 can be an oxide layer or an oxide layer plus a nitride layer.
Step two, as shown in fig. 1B, the hard mask layer 102 is etched by a photolithography process to define a gate formation region, and then the semiconductor substrate 101 is etched by using the hard mask layer 102 as a mask to form a trench 103.
The trench gate MOSFET comprises a current flowing area and a gate lead-out area, wherein the gate lead-out area is positioned at the outer side of the current flowing area, a trench in the gate lead-out area is separately indicated by a mark 103a, and the trench 103a in the gate lead-out area is communicated with the trench 103 in the current flowing area.
The hard mask layer 102 is removed, as shown in fig. 1C.
And step three, as shown in fig. 1D, forming a gate dielectric layer such as a gate oxide layer 104 on the side surface and the bottom surface of the trench 103.
Step four, as shown in fig. 1E, filling polysilicon in the trenches 103 and 103a to form a polysilicon gate 105. The polysilicon gate 105 in the gate lead-out region is connected to the polysilicon gate 105 in the current flow region.
Step five, as shown in fig. 1F, the polysilicon gate 105 is etched back.
Sixthly, as shown in fig. 1F, a well region 106 of the first conductivity type is formed on the surface of the semiconductor substrate 101 in the current flowing region, and a source region 107 composed of a heavily doped region of the second conductivity type is formed on the surface of the well region. For an N-type trench gate MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type; for a P-type trench gate MOSFET, the first conductivity type is N-type and the second conductivity type is P-type.
Step seven, as shown in fig. 1G, an interlayer film 108 is formed.
Step eight, forming contact holes 109a and 109b penetrating through the interlayer film 108, wherein the contact hole 109a is a source contact hole, and the contact hole 109b is a gate contact hole; the contact holes 109a and 109b shown in fig. 1H are in a state after the interlayer film 108 is etched and before metal filling; the contact holes 109a and 109b shown in fig. 1I are in a metal-filled state.
Step nine, as shown in fig. 1J, a front metal layer 110 is formed. As shown in fig. 1K, the front metal layer 110 is etched by photolithography to form a source and a gate, the top of the contact hole 109b is connected to the gate, and the top of the contact hole 109a is connected to the source.
Step ten, as shown in fig. 1L, a drain region composed of a heavily doped region of the second conductivity type is formed on the back surface of the semiconductor substrate 101, a back metal layer 111 is formed on the back surface of the drain region, and the back metal layer 111 is used as a drain.
The current flowing area of the trench gate MOSFET is an area which forms a well region 106 and a source region 107, generates a channel on the surface of the well region 106 covered by the side surface of the polysilicon gate 105 and forms source and drain currents when the polysilicon gate 105 has a working voltage greater than a threshold voltage, and the current flowing area includes a plurality of cell structures of the trench gate MOSFET which are formed in parallel. Typically, the trenches 103 in the current flow region are arranged in parallel at equal intervals, and the sum of the width and the interval of the trenches 103 is the step (pitch) of the cell structure of the trench gate MOSFET, i.e. the step of the polysilicon gate 105. The trench gate MOSFET has the advantage of low on-resistance by increasing the number of channels of the trench gate MOSFET by reducing the step of the polysilicon 105. However, as the Pitch size of the trench MOSFET is further reduced, the difficulty in forming the source contact hole 109a is increased because the source contact hole 109a needs to be defined by a photolithography process in the conventional method, and when the Pitch size is reduced, the leakage between the gate and the source is difficult to suppress, that is, the leakage between the gate and the source is increased, which limits the further reduction of the Pitch size of the trench MOSFET.
Disclosure of Invention
The invention aims to provide a trench gate MOSFET, which reduces the step size among unit structures in a current flowing area of the trench gate MOSFET so as to improve the integration level and the performance of the trench gate MOSFET. Therefore, the invention also provides a manufacturing method of the trench gate MOSFET.
In order to solve the above technical problem, a well region of a first conductivity type is formed on a surface of a semiconductor substrate in a current flowing region of a trench gate MOSFET provided in the present invention, and a source region composed of a heavily doped region of a second conductivity type is formed on a surface of the well region.
A plurality of trenches formed in the semiconductor substrate, each of the trenches penetrating the well region in a longitudinal direction; the width of each groove in the transverse direction is defined by a first opening, and the first opening is formed by photoetching and etching of a hard mask layer.
And gate dielectric layers are formed on the side surfaces and the bottom surfaces of the grooves, and polycrystalline silicon gates made of polycrystalline silicon are filled in the grooves.
And filling a first dielectric layer in the first opening at the top of the polysilicon gate, wherein the material of the first dielectric layer is different from that of the hard mask layer, and removing the hard mask layer between the first openings under the self-alignment definition of the first dielectric layer to form a second opening.
And a first inner side wall composed of a second dielectric layer is formed on the inner side surface of the second opening in a self-aligning manner, and the second opening is reduced into a third opening by the first inner side wall.
And removing the material of the semiconductor substrate at the bottom of the third opening in a self-alignment manner to enable the bottom of the third opening to penetrate through the source region and extend into the well region, filling a metal layer in the extended third opening to form a source contact hole at the top of the source region in a self-alignment manner, wherein the self-alignment structure of the source contact hole enables the step size between each unit structure in the current flowing region of the trench gate MOSFET to be reduced, and therefore the integration level of the trench gate MOSFET is improved.
The further improvement is that a grid leading-out area is formed on the outer side of a current flowing area of the trench grid MOSFET, a trench in the grid leading-out area is communicated with a trench in the current flowing area, and a polysilicon grid in the grid leading-out area is connected with the polysilicon grid in the current flowing area.
The well region extends into the grid electrode lead-out region, and a source region is not formed on the surface of the well region in the grid electrode lead-out region.
The first dielectric layer is completely filled in the first opening at the top of the polysilicon gate of the gate leading-out region, a fourth opening is formed, the fourth opening is defined through photoetching, the fourth opening penetrates through the first dielectric layer of the gate leading-out region, the bottom of the fourth opening also extends into the polysilicon gate, and a metal layer is filled in the extended fourth opening to form a gate contact hole.
In a further improvement, a source electrode formed by patterning the front metal layer is formed on the top of the source contact hole, and a gate electrode formed by patterning the front metal layer is formed on the top of the gate contact hole.
In a further improvement, a well contact region heavily doped with the first conductivity type is formed in the well region at the bottom of the source contact hole, and the well contact region is in contact with the bottom of the source contact hole.
In a further improvement, a drain region composed of a heavily doped region of the second conductivity type is formed on the back surface of the semiconductor substrate, and a drain composed of a back metal layer is formed on the back surface of the drain region.
In a further improvement, the semiconductor substrate is a silicon substrate.
The further improvement is that the hard mask layer is formed by overlapping a first oxide layer, a second nitride layer and a third oxide layer.
The first dielectric layer is composed of a fourth oxide layer.
The second dielectric layer is composed of a fifth oxide layer.
The further improvement is that the gate dielectric layer is a gate oxide layer.
In order to solve the above technical problem, the method for manufacturing a trench gate MOSFET provided by the present invention comprises the following steps:
step one, providing a semiconductor substrate, and forming a well region of a first conduction type in the semiconductor substrate.
And secondly, forming a hard mask layer on the surface of the semiconductor substrate on which the well region is formed.
Defining a forming area of a groove by adopting a photoetching process, and etching the hard mask layer to form a first opening; etching the semiconductor substrate at the bottom of the first opening under the definition of the first opening to form the groove; the trench includes a plurality of trenches and each trench passes through the well region in a longitudinal direction.
Forming gate dielectric layers on the side surfaces and the bottom surfaces of the grooves, and filling polycrystalline silicon gates made of polycrystalline silicon in the grooves; the etched back surface of the polysilicon gate is flush with the surface of the semiconductor substrate and completely opens the first opening.
And fifthly, filling a first dielectric layer in the first opening at the top of the polysilicon gate by adopting a deposition and etch-back process, wherein the material of the first dielectric layer is different from that of the hard mask layer.
And sixthly, removing the hard mask layer between the first openings under the self-alignment definition of the first dielectric layer and forming second openings.
And seventhly, heavily doped ions of the second conduction type are implanted into the surface of the well region in the current flowing area of the trench gate MOSFET to form a source region.
And step eight, depositing a second dielectric layer and carrying out overall etching on the second dielectric layer so as to form a first inner side wall composed of the second dielectric layer on the inner side surface of the second opening in a self-alignment manner, wherein the second opening is reduced into a third opening by the first inner side wall.
And ninthly, performing self-aligned etching on the semiconductor substrate at the bottom of the third opening so as to enable the bottom of the third opening to penetrate through the source region and extend into the well region.
Step ten, filling a metal layer in the third opening to form a source contact hole in a self-alignment mode at the top of the source region, wherein the self-alignment structure of the source contact hole enables the step size between each unit structure in the current flowing region of the trench gate MOSFET to be reduced, and therefore the integration level of the trench gate MOSFET is improved.
The further improvement is that a grid leading-out area is formed on the outer side of a current flowing area of the trench grid MOSFET, a trench in the grid leading-out area and a trench in the current flowing area are formed and communicated at the same time, a grid dielectric layer in the trench of the grid leading-out area and a grid dielectric layer in the trench of the current flowing area are formed at the same time, and a polysilicon grid in the trench of the grid leading-out area and a polysilicon grid in the trench of the current flowing area are formed at the same time.
And seventhly, not forming a source region on the surface of the well region of the grid lead-out region.
And step eight, after the second dielectric layer is deposited, photoetching is carried out to form a fourth opening at the top of the polysilicon gate of the grid lead-out region, and the fourth opening penetrates through the second dielectric layer and the first dielectric layer positioned in the first opening at the bottom of the second dielectric layer.
And then, removing the second medium layer at the top of the first opening of the grid electrode lead-out area while performing overall etching on the second medium layer to form the first inner side wall, so that the fourth opening only penetrates through the first medium layer.
And ninthly, performing self-aligned etching on the semiconductor substrate at the bottom of the third opening and the polysilicon gate at the bottom of the fourth opening at the same time, so that the bottom of the fourth opening also extends into the polysilicon gate.
And step ten, filling a metal layer in the fourth opening to form a gate contact hole.
The further improvement is that the method also comprises the following steps:
step eleven, forming a front metal layer and patterning the front metal layer by adopting a photoetching process to form a source electrode and a grid electrode, wherein the top of the source contact hole is contacted with the source electrode, and the top of the grid contact hole is contacted with the grid electrode.
Step twelve, forming a drain region consisting of a heavily doped region of the second conductivity type on the back surface of the semiconductor substrate, forming a back metal layer on the back surface of the drain region and forming a drain electrode consisting of the back metal layer.
In a further improvement, after the ninth step, a step of performing a heavily doped implantation of the first conductivity type to form a well contact region in the well region at the bottom of the source contact hole, wherein the well contact region is in contact with the bottom of the source contact hole.
In a further improvement, the semiconductor substrate is a silicon substrate.
The further improvement is that the hard mask layer is formed by overlapping a first oxide layer, a second nitride layer and a third oxide layer.
The first dielectric layer is composed of a fourth oxide layer.
The second dielectric layer is composed of a fifth oxide layer.
The further improvement is that the gate dielectric layer is a gate oxide layer.
The invention combines and defines the hard mask layer of the groove, through filling the first dielectric layer different from hard mask layer material in the first opening of the top of the polysilicon gate filled in the groove, the hard mask layer can be removed in a self-aligned way and a second opening is formed, and the inner side surface of the second opening can be formed in a self-aligned way and a first inner side wall can be formed, the second opening can be reduced into a third opening by the first inner side wall, the third opening can be self-aligned and defined in the forming area of the source contact hole, and a source contact hole is formed by filling a metal layer in the third opening, so the transverse position of the source contact hole is completed by a self-aligned process, a photoetching process definition is not needed, and the self-aligned process can not generate registration error caused by the photoetching process, therefore, the invention can shorten the space between the grooves of the current flow area to the minimum, thereby reducing the step size between each unit structure in the current flow area of the groove gate MOSFET, thereby improving the integration level of the trench gate MOSFET; the step reduction of each unit structure in the current flowing area of the trench gate MOSFET can improve the density of a channel, thereby reducing the on-resistance of a device and improving the performance of the device; in addition, the invention can save a photomask for defining the source contact hole and save the cost.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1L are schematic views of a device structure in steps of a conventional trench-gate MOSFET manufacturing method;
FIG. 2 is a schematic structural diagram of a trench-gate MOSFET in accordance with an embodiment of the present invention;
fig. 3A-3T are schematic views of device structures in steps of a method for manufacturing a trench-gate MOSFET according to an embodiment of the invention.
Detailed Description
Fig. 2 is a schematic structural diagram of a trench gate MOSFET according to an embodiment of the present invention; in the embodiment of the invention, a well region 2 of a first conduction type is formed on the surface of a semiconductor substrate 1 in a current flowing region of a trench gate MOSFET, and a source region 6 consisting of a heavily doped region of a second conduction type is formed on the surface of the well region 2.
A plurality of trenches 302 formed in the semiconductor substrate 1, each of the trenches 302 passing through the well region 2 in a longitudinal direction; the width of each trench 302 in the lateral direction is defined by a first opening 301, and the first opening 301 is formed by photolithographic etching of the hard mask layer 202. The first opening 301 is shown in fig. 3D.
A gate dielectric layer 3 is formed on the side surface and the bottom surface of the trench 302, and a polysilicon gate 4 made of polysilicon is filled in the trench 302.
First dielectric layers 5 are filled in the first openings 301 on the top of the polysilicon gate 4, the material of the first dielectric layers 5 is different from that of the hard mask layers 202, and the hard mask layers 202 between the first openings 301 are removed under the self-alignment definition of the first dielectric layers 5 to form second openings 303. The second opening 303 is shown in fig. 3L.
A first inner sidewall 7 composed of a second dielectric layer 7 is formed on the inner side surface of the second opening 303 in a self-aligned manner, and the second opening 303 is reduced into a third opening 305 by the first inner sidewall 7. The third opening 305 is shown in fig. 3P.
The material of the semiconductor substrate 1 at the bottom of the third opening 305 is removed by self-alignment so that the bottom of the third opening 305 passes through the source region 6 and extends into the well region 2, a metal layer 9 is filled in the extended third opening 305 so as to form a source contact hole at the top of the source region 6 by self-alignment, and the self-alignment structure of the source contact hole reduces the step size between each cell structure in the current flowing region of the trench gate MOSFET, thereby improving the integration level of the trench gate MOSFET. In the embodiment of the present invention, a gate lead-out region is formed outside a current flowing region of a trench gate MOSFET, a trench in the gate lead-out region is separately denoted by reference numeral 302a, the trench 302a in the gate lead-out region is communicated with the trench 302 in the current flowing region, and a polysilicon gate 4 in the gate lead-out region is connected with the polysilicon gate 4 in the current flowing region.
The well region 2 extends into the gate lead-out region, and a source region 6 is not formed on the surface of the well region 2 in the gate lead-out region.
The first dielectric layer 5 is completely filled in the first opening 301 at the top of the polysilicon gate 4 in the gate lead-out region, and a fourth opening 304 is formed, the fourth opening 304 is defined by photolithography, the fourth opening 304 penetrates through the first dielectric layer 5 in the gate lead-out region, the bottom of the fourth opening 304 further extends into the polysilicon gate 4, and a metal layer 9 is filled in the extended fourth opening 304, so that a gate contact hole is formed. The fourth opening 304 is shown with reference to fig. 3N. In the source contact hole and the gate contact hole, a metal layer 9 is usually made of tungsten metal, and a barrier layer and an adhesion layer 9a are also formed between the tungsten metal and the semiconductor substrate 1.
And a source electrode formed by patterning the front metal layer 10 is formed at the top of the source contact hole, and a gate electrode formed by patterning the front metal layer 10 is formed at the top of the gate contact hole.
A well contact region 8 heavily doped with the first conductivity type is formed in the well region 2 at the bottom of the source contact hole, and the well contact region 8 is in contact with the bottom of the source contact hole.
A drain region composed of a heavily doped region of the second conductivity type is formed on the back surface of the semiconductor substrate 1, and a drain composed of a back metal layer is formed on the back surface of the drain region.
In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate.
The hard mask layer 202 is formed by stacking a first oxide layer 202a, a second nitride layer 202b, and a third oxide layer 202 c.
The first dielectric layer 5 is composed of a fourth oxide layer.
The second dielectric layer 7 is composed of a fifth oxide layer.
The further improvement is that the gate dielectric layer 3 is a gate oxide layer.
In the embodiment of the invention, the trench gate MOSFET is an N-type device, the first conduction type is a P type, and the second conduction type is an N type. In other embodiments can also be: the trench gate MOSFET is a P-type device, the first conductivity type is N-type, and the second conductivity type is P-type.
In the embodiment of the present invention, the hard mask layer 202 of the trench 302 is defined, the first dielectric layer 5, which is different from the hard mask layer 202, is filled in the first opening 301 at the top of the polysilicon gate 4 filled in the trench 302, so that the hard mask layer 202 can be removed and the second opening 303 is formed in a self-aligned manner, the inner side surface of the second opening 303 can be formed in a self-aligned manner to form the first inner sidewall 7, the first inner sidewall 7 can reduce the second opening 303 to the third opening 305, the third opening 305 can be formed in a self-aligned manner to define the formation region of the source contact hole, and the metal layer is filled in the third opening 305 to form the source contact hole, so that the lateral position of the source contact hole in the embodiment of the present invention is completed by the self-aligned process, the definition by the photolithography process is not required, and the self-aligned process does not generate the registration error caused by the photolithography process, so the embodiment of the present invention can shorten the distance between the trenches 302 in the current flowing region to the minimum, therefore, the step size among all unit structures in the current flowing area of the trench gate MOSFET can be reduced, and the integration level of the trench gate MOSFET is improved; the step reduction of each unit structure in the current flowing area of the trench gate MOSFET can improve the density of a channel, thereby reducing the on-resistance of a device and improving the performance of the device; in addition, the embodiment of the invention can save a photomask for defining the source contact hole and can save the cost.
As shown in fig. 3A to fig. 3T, which are schematic device structure diagrams in each step of the manufacturing method of the trench gate MOSFET according to the embodiment of the present invention, the manufacturing method of the trench gate MOSFET according to the embodiment of the present invention includes the following steps:
step one, providing a semiconductor substrate 1, and forming a well region 2 of a first conduction type in the semiconductor substrate 1. As shown in fig. 3A, the well region 2 is formed by ion implantation and annealing, and before the ion implantation of the well region 2, a step of forming a Screen oxide layer (Screen oxide)201 on the surface of the semiconductor substrate 1 is further included; as shown in fig. 3B, ion implantation and annealing advancement of the well region 2 are then performed.
After that, the masking oxide layer 201 is removed. The thickness of the masking oxide layer 201 is about
Figure BDA0001779377840000081
Step two, as shown in fig. 3C, a hard mask layer 202 is formed on the surface of the semiconductor substrate 1 where the well region 2 is formed.
Step three, as shown in fig. 3D, a photoresist pattern 203 is formed by using a photolithography process, and the photoresist pattern 203 defines a formation region of the trench 302.
The hard mask layer 202 is etched to form a first opening 301. As shown in fig. 3E, the photoresist pattern 203 is then removed.
As shown in fig. 3F, the trench 302 is formed by etching the semiconductor substrate 1 at the bottom of the first opening 301 under the definition of the first opening 301; the trenches 302 include a plurality of trenches 302, and each trench 302 passes through the well region 2 in the longitudinal direction.
In the method of the embodiment of the invention, a gate lead-out region is formed at the outer side of the current flowing region of the trench gate MOSFET, and the trench 302a in the gate lead-out region and the trench 302 in the current flowing region are formed and communicated at the same time.
Step four, as shown in fig. 3G, a gate dielectric layer 3 is formed on the side surface and the bottom surface of the trench 302.
As shown in fig. 3H, the trench 302 is filled with a polysilicon gate 4 made of polysilicon; the polysilicon corresponding to the polysilicon gate 4 is formed by adopting a deposition process; then, polysilicon etching back is performed as shown in fig. 3I, and the etched back surface of the polysilicon gate 4 is flush with the surface of the semiconductor substrate 1 and completely opens the first opening 301.
In the method of the embodiment of the present invention, the gate dielectric layer 3 in the trench 302a of the gate lead-out region and the gate dielectric layer 3 in the trench 302 of the current flowing region are simultaneously formed, and the polysilicon gate 4 in the trench 302a of the gate lead-out region and the polysilicon gate 4 in the trench 302 of the current flowing region are simultaneously formed.
Step five, as shown in fig. 3J, filling a first dielectric layer 5 in the first opening 301 at the top of the polysilicon gate 4 by using a deposition and etch-back process, where the material of the first dielectric layer 5 is different from the material of the hard mask layer 202. Fig. 3J is a schematic diagram corresponding to the deposited first dielectric layer 5, and fig. 3K is a schematic diagram after the etching back of the first dielectric layer 5, where the etching back of the first dielectric layer 5 includes etching and Chemical Mechanical Polishing (CMP).
Sixthly, as shown in fig. 3L, the hard mask layer 202 between the first openings 301 is removed under the self-aligned definition of the first dielectric layer 5, and second openings 303 are formed.
Seventhly, as shown in fig. 3L, heavily doped ions of the second conductivity type are implanted to form a source region 6 on the surface of the well region 2 in the current flowing region of the trench gate MOSFET.
In the method of the embodiment of the invention, no source region 6 is formed on the surface of the well region 2 of the gate lead-out region.
Step eight, as shown in fig. 3M, depositing a second dielectric layer 7 and performing overall etching on the second dielectric layer 7, so as to form a first inner sidewall 7 composed of the second dielectric layer 7 in a self-aligned manner on the inner side surface of the second opening 303, where the first inner sidewall 7 reduces the second opening 303 into a third opening 305.
In the method of the embodiment of the present invention, after depositing the second dielectric layer 7, the method further includes the following steps:
as shown in fig. 3N, performing photolithography to form a photoresist pattern 204; etching under the definition of the photoresist pattern 204 to form a fourth opening 304 at the top of the polysilicon gate 4 in the gate lead-out region; the fourth opening 304 penetrates through the second dielectric layer 7 and the first dielectric layer 5 at the bottom of the second dielectric layer 7 and located in the first opening 301. The photoresist pattern 204 is then removed, as shown in fig. 3O.
As shown in fig. 3P, the second dielectric layer 7 on the top of the first opening 301 in the gate lead-out region is removed while the second dielectric layer 7 is etched on the whole to form the first inner sidewall spacers 7, so that the fourth opening 304 only penetrates through the first dielectric layer 5.
Ninthly, as shown in fig. 3Q, a self-aligned etching is performed on the semiconductor substrate 1 at the bottom of the third opening 305 so as to extend the bottom of the third opening 305 through the source region 6 and into the well region 2.
In the method of the embodiment of the present invention, the semiconductor substrate 1 at the bottom of the third opening 305 is self-aligned etched, and simultaneously, the polysilicon gate 4 at the bottom of the fourth opening 304 is self-aligned etched, so that the bottom of the fourth opening 304 also extends into the polysilicon gate 4.
In the method according to the embodiment of the present invention, as shown in fig. 3R, after the third opening 305 is formed, a step of performing a heavily doped implantation of the first conductivity type to form a well contact region 8 in the well region 2 at the bottom of the source contact hole is further included, and the well contact region 8 is in contact with the bottom of the source contact hole.
Step ten, as shown in fig. 3S, filling the metal layer 9 in the third opening 305 to form a source contact hole in a self-aligned manner at the top of the source region 6, where the self-aligned structure of the source contact hole reduces the step size between the cell structures in the current flowing region of the trench gate MOSFET, thereby improving the integration level of the trench gate MOSFET. In the method according to the embodiment of the present invention, in the source contact hole, the metal layer 9 is usually made of tungsten metal, and before filling the tungsten metal, the method further includes a step of forming a barrier layer and an adhesion layer 9 a.
In the method of the embodiment of the present invention, the fourth opening 304 is filled with the metal layer 9 at the same time to form a gate contact hole.
Further comprising:
step eleven, forming a front metal layer 10 and patterning the front metal layer 10 by adopting a photoetching process to form a source electrode and a grid electrode, wherein the top of the source contact hole is contacted with the source electrode, and the top of the grid contact hole is contacted with the grid electrode.
Step twelve, forming a drain region composed of a heavily doped region of the second conductivity type on the back surface of the semiconductor substrate 1, forming a back metal layer on the back surface of the drain region and forming a drain electrode by the back metal layer.
In the method of the embodiment of the invention, the semiconductor substrate 1 is a silicon substrate.
The hard mask layer 202 is formed by stacking a first oxide layer 202a, a second nitride layer 202b, and a third oxide layer 202 c.
The first dielectric layer 5 is composed of a fourth oxide layer.
The second dielectric layer 7 is composed of a fifth oxide layer.
The gate dielectric layer 3 is a gate oxide layer.
In the method of the embodiment of the invention, the trench gate MOSFET is an N-type device, the first conductive type is a P type, and the second conductive type is an N type. In other embodiments the method can also be: the trench gate MOSFET is a P-type device, the first conductivity type is N-type, and the second conductivity type is P-type.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A trench-gate MOSFET, comprising:
a well region of a first conduction type is formed on the surface of the semiconductor substrate in the current flowing region of the trench gate MOSFET, and a source region consisting of a heavily doped region of a second conduction type is formed on the surface of the well region;
a plurality of trenches formed in the semiconductor substrate, each of the trenches penetrating the well region in a longitudinal direction; the width of each groove in the transverse direction is defined by a first opening, and the first opening is formed by photoetching and etching a hard mask layer;
forming gate dielectric layers on the side surfaces and the bottom surfaces of the grooves, filling the grooves with polysilicon gates composed of polysilicon, wherein the top surfaces of the polysilicon gates are level with the top surfaces of the semiconductor substrates;
filling a first dielectric layer in the first opening at the top of the polysilicon gate, wherein the material of the first dielectric layer is different from that of the hard mask layer, and removing the hard mask layer between the first openings under the self-alignment definition of the first dielectric layer to form a second opening;
a first inner side wall composed of a second medium layer is formed on the inner side surface of the second opening in a self-aligning mode, and the second opening is reduced into a third opening through the first inner side wall;
and removing the material of the semiconductor substrate at the bottom of the third opening in a self-alignment manner to enable the bottom of the third opening to penetrate through the source region and extend into the well region, filling a metal layer in the extended third opening to form a source contact hole at the top of the source region in a self-alignment manner, wherein the self-alignment structure of the source contact hole enables the step size between each unit structure in the current flowing region of the trench gate MOSFET to be reduced, and therefore the integration level of the trench gate MOSFET is improved.
2. The trench-gate MOSFET of claim 1 wherein: a grid electrode leading-out area is formed on the outer side of a current flowing area of the trench grid MOSFET, a trench in the grid electrode leading-out area is communicated with a trench in the current flowing area, and a polysilicon gate in the grid electrode leading-out area is connected with a polysilicon gate in the current flowing area;
the well region extends into the grid electrode lead-out region, and a source region is not formed on the surface of the well region in the grid electrode lead-out region;
the first dielectric layer is completely filled in the first opening at the top of the polysilicon gate of the gate leading-out region, a fourth opening is formed, the fourth opening is defined through photoetching, the fourth opening penetrates through the first dielectric layer of the gate leading-out region, the bottom of the fourth opening also extends into the polysilicon gate, and a metal layer is filled in the extended fourth opening to form a gate contact hole.
3. The trench-gate MOSFET of claim 2 wherein: and a source electrode formed by patterning the front metal layer is formed at the top of the source contact hole, and a grid electrode formed by patterning the front metal layer is formed at the top of the grid contact hole.
4. The trench-gate MOSFET of claim 1 wherein: and a well contact region heavily doped with the first conductivity type is formed in the well region at the bottom of the source contact hole, and the well contact region is in contact with the bottom of the source contact hole.
5. The trench-gate MOSFET of claim 1 wherein: and a drain region composed of a heavily doped region of the second conductivity type is formed on the back surface of the semiconductor substrate, and a drain composed of a back metal layer is formed on the back surface of the drain region.
6. The trench-gate MOSFET of claim 1 wherein: the semiconductor substrate is a silicon substrate.
7. The trench-gate MOSFET of claim 6 wherein: the hard mask layer is formed by overlapping a first oxide layer, a second nitride layer and a third oxide layer;
the first dielectric layer is composed of a fourth oxide layer;
the second dielectric layer is composed of a fifth oxide layer.
8. The trench-gate MOSFET of claim 6 wherein: the gate dielectric layer is a gate oxide layer.
9. A method for manufacturing a trench-gate MOSFET, comprising the steps of:
providing a semiconductor substrate, and forming a well region of a first conduction type in the semiconductor substrate;
secondly, forming a hard mask layer on the surface of the semiconductor substrate on which the well region is formed;
defining a forming area of a groove by adopting a photoetching process, and etching the hard mask layer to form a first opening; etching the semiconductor substrate at the bottom of the first opening under the definition of the first opening to form the groove; the grooves comprise a plurality of grooves, and each groove penetrates through the well region in the longitudinal direction;
forming gate dielectric layers on the side surfaces and the bottom surfaces of the grooves, and filling polycrystalline silicon gates made of polycrystalline silicon in the grooves; the etched back surface of the polysilicon gate is flush with the surface of the semiconductor substrate and completely opens the first opening;
filling a first dielectric layer in the first opening at the top of the polysilicon gate by adopting a deposition and etch-back process, wherein the material of the first dielectric layer is different from that of the hard mask layer;
sixthly, removing the hard mask layer between the first openings under the self-alignment definition of the first dielectric layer and forming second openings;
seventhly, heavily doped ions of the second conduction type are injected into the surface of the well region in the current flowing area of the trench gate MOSFET to form a source region;
depositing a second dielectric layer and carrying out overall etching on the second dielectric layer so as to form a first inner side wall composed of the second dielectric layer on the inner side surface of the second opening in a self-alignment manner, wherein the second opening is reduced into a third opening by the first inner side wall;
ninthly, performing self-aligned etching on the semiconductor substrate at the bottom of the third opening so as to enable the bottom of the third opening to penetrate through the source region and extend into the well region;
step ten, filling a metal layer in the third opening to form a source contact hole in a self-alignment mode at the top of the source region, wherein the self-alignment structure of the source contact hole enables the step size between each unit structure in the current flowing region of the trench gate MOSFET to be reduced, and therefore the integration level of the trench gate MOSFET is improved.
10. The method of manufacturing a trench-gate MOSFET of claim 9, wherein: a grid electrode leading-out area is formed on the outer side of a current flowing area of the trench grid MOSFET, a trench in the grid electrode leading-out area and a trench in the current flowing area are formed at the same time and are communicated, a grid dielectric layer in the trench of the grid electrode leading-out area and a grid dielectric layer in the trench of the current flowing area are formed at the same time, and a polysilicon gate in the trench of the grid electrode leading-out area and a polysilicon gate in the trench of the current flowing area are formed at the same time;
seventhly, a source region is not formed on the surface of the well region of the grid electrode lead-out region;
step eight, after depositing the second dielectric layer, performing photoetching to form a fourth opening at the top of the polysilicon gate of the gate lead-out region, wherein the fourth opening penetrates through the second dielectric layer and the first dielectric layer at the bottom of the second dielectric layer and positioned in the first opening;
then, the second dielectric layer on the top of the first opening of the grid electrode lead-out area is removed while the second dielectric layer is etched comprehensively to form the first inner side wall, so that the fourth opening only penetrates through the first dielectric layer;
in the ninth step, the semiconductor substrate at the bottom of the third opening is subjected to self-aligned etching, and simultaneously the polysilicon gate at the bottom of the fourth opening is subjected to self-aligned etching, so that the bottom of the fourth opening also extends into the polysilicon gate;
and step ten, filling a metal layer in the fourth opening to form a gate contact hole.
11. The method of manufacturing a trench-gate MOSFET of claim 10, wherein: further comprising:
step eleven, forming a front metal layer and patterning the front metal layer by adopting a photoetching process to form a source electrode and a grid electrode, wherein the top of the source contact hole is contacted with the source electrode, and the top of the grid contact hole is contacted with the grid electrode;
step twelve, forming a drain region consisting of a heavily doped region of the second conductivity type on the back surface of the semiconductor substrate, forming a back metal layer on the back surface of the drain region and forming a drain electrode consisting of the back metal layer.
12. The method of manufacturing a trench-gate MOSFET of claim 9, wherein: and after the step nine is completed, a step of performing heavily doped implantation of the first conductivity type to form a well contact region in the well region at the bottom of the source contact hole, wherein the well contact region is in contact with the bottom of the source contact hole.
13. The method of manufacturing a trench-gate MOSFET of claim 9, wherein: the semiconductor substrate is a silicon substrate.
14. The method of manufacturing a trench-gate MOSFET of claim 13, wherein: the hard mask layer is formed by overlapping a first oxide layer, a second nitride layer and a third oxide layer;
the first dielectric layer is composed of a fourth oxide layer;
the second dielectric layer is composed of a fifth oxide layer.
15. The method of manufacturing a trench-gate MOSFET of claim 13, wherein: the gate dielectric layer is a gate oxide layer.
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