CN111370305A - Deep groove type super junction device and manufacturing method thereof - Google Patents
Deep groove type super junction device and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 22
- 150000002500 ions Chemical class 0.000 claims description 15
- 238000001259 photo etching Methods 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 5
- -1 boron ions Chemical class 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000000407 epitaxy Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000009987 spinning Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The application discloses a deep groove type super junction device and a manufacturing method thereof, and relates to the field of semiconductor manufacturing. The manufacturing method of the deep groove type super junction device comprises the steps of forming an epitaxial layer on the surface of a substrate; defining a P-type area pattern, and etching the epitaxial layer according to the P-type area pattern to form a deep groove; performing P-type ion implantation on the bottom of the deep groove; filling the deep trench; the problem that the breakdown voltage of the existing deep groove type device is limited by the concentration matching degree of a P-type region and an N-type region is solved; the effect of adjusting the concentration matching degree of the bottoms of the P-type region and the N-type region and improving the breakdown voltage of the device is achieved.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a deep groove type super junction device and a manufacturing method thereof.
Background
Power semiconductor devices are widely used in mobile communications, automotive electronics, control circuits, and the like. The conventional power semiconductor device has the contradiction between the breakdown voltage and the on-resistance, namely the on-resistance of the power semiconductor device has a limit due to the limitation of the breakdown voltage, and in order to break the limit, the super junction device is provided.
A series of P-type regions and N-type regions which are alternately arranged are used as drift layers in the super junction device, and the principle of charge mutual compensation is realized by utilizing depletion of the P-type regions and the N-type regions, so that high breakdown voltage is obtained.
At present, when a deep trench super junction device is manufactured, a deep trench is dug out in a semiconductor substrate through an etching process, and then a P-type epitaxy is filled into the deep trench to form a P-type region. The breakdown voltage of the deep trench super junction device is related to the thickness of the drift region and the depletion degree of the P-type region and the N-type region, but the depth of the deep trench and the concentration matching degree of the P-type region and the N-type region are often limited by etching and epitaxial technology, process equipment and the like.
Disclosure of Invention
In order to solve the problems in the related art, the application provides a deep trench type super junction device and a manufacturing method thereof. The technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a method for manufacturing a deep trench type super junction device, where the method includes:
forming an epitaxial layer on the surface of the substrate;
defining a P-type area pattern, and etching the epitaxial layer according to the P-type area pattern to form a deep groove;
performing P-type ion implantation on the bottom of the deep groove;
filling the deep trench.
Optionally, the performing P-type ion implantation on the bottom of the deep trench includes:
and implanting boron ions into the bottom of the deep groove.
Optionally, the forming an epitaxial layer on the substrate surface includes:
and growing an N-type epitaxial layer on the surface of the N-type substrate.
Optionally, the defining a P-type region pattern, and etching the epitaxial layer according to the P-type region pattern to form a deep trench includes:
forming a hard mask layer above the epitaxial layer;
defining the P-type area pattern through a photoetching process, and etching the hard mask layer according to the P-type area pattern;
and etching the epitaxial layer by using the etched hard mask layer as a mask to form the deep groove.
Optionally, the defining a P-type region pattern, and etching the epitaxial layer according to the P-type region pattern to form a deep trench includes:
defining the P-type area pattern on the surface of the epitaxial layer through a photoetching process;
and etching the epitaxial layer according to the P-type region pattern to form the deep trench.
Optionally, the filling the deep trench includes:
and filling the deep trench with a P-type epitaxial layer.
In a second aspect, an embodiment of the present application provides a deep trench type super junction device, which at least includes a substrate, and an epitaxial layer located above the substrate, wherein a series of N-type regions and P-type regions are formed in the epitaxial layer and are alternately arranged;
the bottom of the P-type region is in a water drop shape after P-type ion implantation.
Optionally, the substrate is N-type, and the epitaxial layer is N-type.
The technical scheme at least comprises the following advantages:
the deep groove is formed in the epitaxial layer, the P-type ions are injected into the bottom of the deep groove, the P-type concentration of the bottom of the deep groove is increased, the ion concentrations of the bottoms of the P-type region and the N-type region are adjusted, and the problem that the breakdown voltage of the existing deep groove type device is limited by the concentration matching degree of the P-type region and the N-type region is solved; the effect of adjusting the concentration matching degree of the bottoms of the P-type region and the N-type region and improving the breakdown voltage of the device is achieved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a deep trench type super junction device according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a super junction provided in an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a method for fabricating a deep trench super junction device according to an embodiment of the present application is shown, the method at least includes the following steps:
Optionally, the substrate is an N-type substrate, and an N-type epitaxial layer is grown on the surface of the N-type substrate.
And 102, defining a P-type area pattern, and etching the epitaxial layer according to the P-type area pattern to form a deep groove.
And 103, performing P-type ion implantation on the bottom of the deep trench.
The P-type ions are injected into the bottom of the deep groove, the P-type concentration of the bottom of the deep groove is increased, the concentrations of the bottom of the P-type region and the bottom of the N-type region are adjusted to be in a balanced state, when the device is started, the P-type region and the N-type region are completely exhausted, and the breakdown voltage of the device is improved.
After P-type ions are injected into the bottom of the deep groove, the bottom of the deep groove is in a water droplet state. As shown in fig. 2, deep trenches 22 are formed in the epitaxial layer 21, and after P-type ion implantation, the bottoms of the deep trenches 22 are shaped like drops.
Optionally, P-type ions are vertically implanted into the bottom of the deep trench.
Under the condition that the side wall of the deep groove is not completely vertical, the vertical injection can inject P-type ions into the bottom of the deep groove; the injected P-type ions enable the proportion of holes and electrons at the bottom of the deep groove to reach 1: 1, the holes and the electrons of the P-type region and the N-type region at the bottom of the deep trench are more completely exhausted when the device is opened.
Optionally, the deep trench is filled with a P-type epitaxy.
The P-type epitaxy filled in the deep grooves forms a P-type region, the N-type epitaxy between the deep grooves forms an N-type region, and the P-type region and the N-type region are alternately arranged to form a super junction.
In summary, according to the method for manufacturing the deep trench type super junction device provided by the embodiment of the present application, the deep trench is formed in the epitaxial layer, and the P-type ions are injected into the bottom of the deep trench, so as to increase the P-type concentration at the bottom of the deep trench, and adjust the ion concentrations at the bottoms of the P-type region and the N-type region, thereby solving the problem that the breakdown voltage of the present deep trench type device is limited by the concentration matching degree of the P-type region and the N-type region; the effect of adjusting the concentration matching degree of the bottoms of the P-type region and the N-type region and improving the breakdown voltage of the device is achieved.
Another embodiment of the present application provides a method for manufacturing a deep trench type super junction device, which at least includes the following steps:
in step 301, an N-type epitaxial layer is grown on an N-type substrate surface.
In step 302, a P-type region pattern is defined, and the epitaxial layer is etched according to the P-type region pattern to form a deep trench.
This step can be implemented in several ways:
firstly, defining a P-type area pattern by utilizing photoresist.
And defining a P-type region pattern on the epitaxial layer mark through a photoetching process.
Specifically, a photoresist is coated on the surface of the epitaxial layer in a spinning mode, the photoresist is exposed by using a mask plate with a P-type region pattern, and after the photoresist is developed, the P-type region pattern is transferred into the photoresist.
And etching the epitaxial layer according to the pattern of the P-type region to form a deep trench. And after the deep groove is formed, removing the photoresist on the surface of the epitaxial layer.
And secondly, defining a P-type area pattern through the hard mask layer.
A hard mask layer is formed over the epitaxial layer.
And defining a P-type area pattern through a photoetching process, and etching the hard mask layer according to the P-type area pattern.
Specifically, photoresist is coated on the surface of the hard mask layer in a spinning mode, the photoresist is exposed by using a mask plate with a P-type area pattern, after development, the P-type area pattern is transferred into the photoresist, the hard mask layer is etched according to the P-type area pattern, the P-type area pattern is transferred into the hard mask layer, and after etching is completed, the photoresist on the surface of the hard mask layer is removed.
And etching the epitaxial layer to form a deep groove by taking the etched hard mask layer as a mask.
Optionally, after filling the deep trench, the hard mask layer on the surface of the epitaxial layer is removed.
Step 303, implanting P-type ions into the bottom of the deep trench.
Optionally, injecting boron ions into the bottom of the deep trench; boron ions are implanted vertically into the bottom of the deep trench.
Since the region outside the deep trench is blocked by the photoresist or the hard mask, the P-type ions are vertically injected to the bottom region of the deep trench along the deep trench, and the P-type concentration at the bottom of the deep trench is increased. The bottom of the deep trench after the P-type ion implantation is in a droplet shape, as shown in fig. 2.
Step 304, filling the deep trench with a P-type epitaxial layer.
Optionally, the deep trench is filled with a P-type epitaxial layer by using an epitaxial growth method.
In one case, CMP (Chemical mechanical planarization) is performed after the filling of the P-type epitaxial layer to remove the P-type epitaxial and hard mask layers from the surface of the epitaxial layer.
As shown in fig. 2, P-type regions and N-type regions are alternately arranged in the epitaxial layer 11 to form super junctions.
In one example, the thickness of the N-type epitaxial layer is 50um, the resistivity of the N-type epitaxial layer is 2ohm, the depth of the deep trench formed in the epitaxial layer is 42um, P-type ion implantation is performed on the bottom of the deep trench, and the parameters of the ion implantation are as follows: boron (B) ion at a dose of 2E13cm-2(ii) a The breakdown voltage of the formed deep groove type super junction device is improved by 15-30V.
The embodiment of the application provides a deep groove type super junction device, which at least comprises a substrate and an epitaxial layer positioned above the substrate, wherein a series of N-type regions and P-type regions which are alternately arranged are formed in the epitaxial layer.
The bottom of the P-type region is drop-shaped after P-type ion implantation, as shown in fig. 2.
Optionally, the substrate is N-type, and the epitaxial layer is N-type.
In summary, in the deep trench type super junction device provided in the embodiment of the present application, since P-type ions are implanted into the bottom of the P-type region, the concentration of the P-type ions at the bottom of the P-type region is increased, the concentration matching degree between the P-type region and the N-type region is improved, the P-type region and the N-type region are more completely depleted when the device is turned on, and the breakdown voltage of the device is increased.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (8)
1. A method for manufacturing a deep groove type super junction device is characterized by comprising the following steps:
forming an epitaxial layer on the surface of the substrate;
defining a P-type area pattern, and etching the epitaxial layer according to the P-type area pattern to form a deep groove;
performing P-type ion implantation on the bottom of the deep groove;
filling the deep trench.
2. The method of claim 1, wherein the implanting the P-type ions into the bottom of the deep trench comprises:
and implanting boron ions into the bottom of the deep groove.
3. The method of claim 1, wherein forming an epitaxial layer on a surface of a substrate comprises:
and growing an N-type epitaxial layer on the surface of the N-type substrate.
4. The method of claim 1, wherein the defining a P-type region pattern and etching the epitaxial layer according to the P-type region pattern to form a deep trench comprises:
forming a hard mask layer above the epitaxial layer;
defining the P-type area pattern through a photoetching process, and etching the hard mask layer according to the P-type area pattern;
and etching the epitaxial layer by using the etched hard mask layer as a mask to form the deep groove.
5. The method of claim 1, wherein the defining a P-type region pattern and etching the epitaxial layer according to the P-type region pattern to form a deep trench comprises:
defining the P-type area pattern on the surface of the epitaxial layer through a photoetching process;
and etching the epitaxial layer according to the P-type region pattern to form the deep trench.
6. The method of claim 1, wherein the filling the deep trench comprises:
and filling the deep trench with a P-type epitaxial layer.
7. A deep groove type super junction device is characterized by at least comprising a substrate and an epitaxial layer positioned above the substrate, wherein a series of N-type regions and P-type regions which are alternately arranged are formed in the epitaxial layer;
the bottom of the P-type region is in a water drop shape after P-type ion implantation.
8. The deep trench super junction device of claim 7, wherein the substrate is N-type and the epitaxial layer is N-type.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010364693.8A CN111370305A (en) | 2020-04-30 | 2020-04-30 | Deep groove type super junction device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010364693.8A CN111370305A (en) | 2020-04-30 | 2020-04-30 | Deep groove type super junction device and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112635504A (en) * | 2020-12-08 | 2021-04-09 | 华虹半导体(无锡)有限公司 | Manufacturing method of ultra-deep photodiode in CIS device and CIS device |
| CN112736103A (en) * | 2020-12-23 | 2021-04-30 | 华虹半导体(无锡)有限公司 | Deep trench isolation forming method of image sensor and semiconductor device structure |
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| CN112736103A (en) * | 2020-12-23 | 2021-04-30 | 华虹半导体(无锡)有限公司 | Deep trench isolation forming method of image sensor and semiconductor device structure |
| CN112736103B (en) * | 2020-12-23 | 2022-09-20 | 华虹半导体(无锡)有限公司 | Deep trench isolation forming method of image sensor and semiconductor device structure |
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