CN109326653A - Power device and its manufacturing method - Google Patents
Power device and its manufacturing method Download PDFInfo
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- CN109326653A CN109326653A CN201811335560.7A CN201811335560A CN109326653A CN 109326653 A CN109326653 A CN 109326653A CN 201811335560 A CN201811335560 A CN 201811335560A CN 109326653 A CN109326653 A CN 109326653A
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- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 36
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- 238000005530 etching Methods 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 description 9
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- 238000009413 insulation Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
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- 239000010703 silicon Substances 0.000 description 4
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- 229910045601 alloy Inorganic materials 0.000 description 3
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
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- 238000013473 artificial intelligence Methods 0.000 description 2
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- 238000004528 spin coating Methods 0.000 description 2
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- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
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- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
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- 150000004767 nitrides Chemical class 0.000 description 1
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- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
This disclosure relates to a kind of power device, comprising: substrate；First epitaxial layer is set on the substrate；Second epitaxial layer is set on first epitaxial layer；Multiple first bodies area is set in second epitaxial layer；Multiple second bodies area, is set to the lower section in corresponding first body area；Wherein, the multiple second body area extends downwardly into first epitaxial layer from second epitaxial layer, and the bottom in the multiple second body area is located in first epitaxial layer.
Description
Technical field
This disclosure relates to semiconductor field, and in particular, to a kind of power device and its manufacturing method and including this
The electronic equipment of power device.
Background technique
Conventional power devices (for example, VDMOS) need to reduce drift doping concentration or increase drift to bear high voltage
Area's thickness is moved, this bring direct result is that conducting resistance increased dramatically.In order to overcome the above problem, super junction power device (example
Such as, super node MOSFET) increasingly it is taken seriously.Super node MOSFET is based on charge compensation principle, makes the conducting resistance of device and hits
Voltage is worn in 1.32 power relationships, has well solved the contradiction between conducting resistance and breakdown voltage.With conventional power VDMOS
Structure is compared, and super node MOSFET is maintained using low-doped drift layer in multiple column areas substitution conventional power devices as voltage
Layer achievees the purpose that improve breakdown voltage and reduces conducting resistance.
Super junction power device needs to further increase breakdown voltage, it is therefore desirable to further increase column area length and
The thickness and resistivity of epitaxial layer.When breakdown voltage demand further rises to certain value (such as 900V or more), superjunction power
The technique controlling difficulty of device improves, product yield and reliability become unstable, and simultaneously turning on resistance can also sharply increase, because
What the super junction power device of this high-breakdown-voltage became is difficult to realize.
Summary of the invention
In view of this, the purpose of the disclosure be at least partly to provide it is a kind of with the power device for improving performance and its
Manufacturing method and electronic equipment including this power device.
According to one aspect of the disclosure, a kind of semiconductor devices is provided, comprising: substrate；First epitaxial layer, is set to
On the substrate；Second epitaxial layer is set on first epitaxial layer；Multiple first bodies area is set to second extension
In layer；Multiple second bodies area, is set to the lower section in corresponding first body area；Wherein, the multiple second body area is outside described second
Prolong layer to extend downwardly into first epitaxial layer, the bottom in the multiple second body area is located in first epitaxial layer.
Wherein, second body area is column, and the doping concentration in second body area is less than first body area
Doping concentration.
The power device further include: multiple third bodies area, be set to the lower section in corresponding second body area and with the second body area
Bottom contact.
Wherein, the doping concentration in third body area is less than the doping concentration in first body area and the second body area.
Wherein, first body area, second body area and third body area all have the second conduction type.
The power device further includes the source region for the first conduction type being formed in first body area and is formed in institute
State the drain region of the first conduction type in substrate.
Wherein, the first epitaxial layer and the second epitaxial layer all have the first conduction type, and the doping concentration of the first epitaxial layer
Greater than the doping concentration of the second epitaxial layer.
A kind of manufacturing method of power device another aspect of the present disclosure provides, comprising: extension on substrate
First epitaxial layer；The second epitaxial layer of extension on the first epitaxial layer；Hard mask layer is formed on second epitaxial layer, to described
Hard mask layer performs etching to form multiple openings；For the multiple opening position to second epitaxial layer and the first extension
Layer performs etching to form multiple deep trench, and the deep trench send second epitaxial layer to extend in first epitaxial layer；
It is doped injection in the bottom of the multiple deep trench, forms multiple third bodies area；Extension is carried out to the multiple deep trench
Doped growing forms multiple columnar second body areas；Multiple first bodies area is formed in second epitaxial layer.
The manufacturing method of the power device further include: form source region in first body area；To the substrate bottom
Portion is carried out back thinning to be made with metal layer on back, forms drain region.
According to the another aspect of the disclosure, a kind of electronic equipment is provided, including at least partly by aforementioned any one
The integrated circuit that the power device of item is formed.
The electronic equipment further include: cooperate with the display of integrated circuit cooperation and with the integrated circuit
Wireless transceiver.
The electronic equipment includes smart phone, computer, tablet computer, artificial intelligence, wearable device or mobile electricity
Source.
Thus the power device of the disclosure forms the super-junction structure with bi-layer substrate epitaxial layer and multiple body areas, thus sharp
Charge balance and device inside field distribution are effectively adjusted with the structure that column bottom increases separate component area, is reducing electric conduction
Transistor avalanche capability and reverse recovery characteristic can be improved on the basis of resistance simultaneously.Therefore, the power device of the disclosure can be with
It realizes high breakdown voltage, while keeping lower conducting resistance.
Detailed description of the invention
It is available to the more complete of theme with claim by reference to being described in detail when considering in conjunction with the following drawings
Understanding, wherein identical appended drawing reference refers to similar element in all the appended drawings.
Fig. 1-9 is the transversal of each step for showing manufacture according to the process of the power device of one embodiment of the disclosure
Face figure；
Figure 10 is to show the cross-sectional view of power device according to another embodiment of the present disclosure；
Figure 11 is to show the flow chart for manufacturing power device according to an embodiment of the present disclosure.
Specific embodiment
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are only exemplary
, and it is not intended to limit the scope of the present disclosure.In addition, in the following description, descriptions of well-known structures and technologies are omitted, with
Avoid unnecessarily obscuring the concept of the disclosure.
The various structural schematic diagrams according to the embodiment of the present disclosure are shown in the attached drawings.These figures are not drawn to scale
, wherein some details are magnified for the purpose of clear expression, and some details may be omitted.It is shown in the drawings
Various regions, the shape of layer and relative size, positional relationship between them are merely exemplary, in practice may be due to system
It makes tolerance or technical restriction and is deviated, and those skilled in the art may be additionally designed as required with difference
Shape, size, the regions/layers of relative position.
In the context of the disclosure, when one layer/element is referred to as located at another layer/element "upper", which can
May exist intermediate layer/element on another layer/element or between them.In addition, if in a kind of direction
In one layer/element be located at another layer/element "upper", then when turn towards when, which can be located at another layer/member
Part "lower".
Power device (for example, super junction power device) according to the embodiment of the present disclosure may include semiconductor source region, partly lead
Body drain area, grid and body plot structure.Wherein, sequence extension has the first epitaxial layer and the second epitaxial layer on substrate.Outside first
Prolonging layer and the second epitaxial layer can be doped respectively, and the doping concentration of the first epitaxial layer can be greater than the doping of the second epitaxial layer
Concentration.Substrate, the first epitaxial layer and the second epitaxial layer all can be the first conduction type, such as N-type.It can on the second epitaxial layer
To be formed with planar gate, which may include grid and bottom surface and the second extension positioned at grid
Gate insulating layer between the upper surface of layer.Grid for example can be polysilicon gate.Gate insulating layer can by silica or
High-k dielectrics material is made.Body plot structure can be formed in the first and second epitaxial layers, which may include first
Body area, the second body area and third body area.First body area can extend downwardly and be formed in from the upper surface of the second epitaxial layer
In second epitaxial layer.Second body area can form below first body area and connect with the bottom in first body area
Touching, second body area can extend downwardly into first epitaxial layer from second epitaxial layer, that is, the second body area can be with
Cross the interface between first epitaxial layer and second epitaxial layer.Third body area can be formed in second body
Below area and it is formed in first epitaxial layer.Third body area can be contacted with the bottom in second body area.It is described
First body area, the second body area and third body area all can be the second conduction type, such as p-type.First body area, the second body area
Reduce with the doping concentration sequence in third body area, that is, the doping concentration in second body area is less than the doping in first body area
Concentration, the doping concentration in third body area are less than the doping concentration in second body area.Wherein, the doping in first body area
Concentration range is 5 × 1015cm-3To 1 × 1019cm-3, for example, 5 × 10 can be used16cm-3Doping concentration；Second body
The doping concentration range in area is 5 × 1014cm-3To 1 × 1016cm-3, for example, 5 × 10 can be used15cm-3Doping concentration；Institute
The doping concentration range for stating third body area is 1 × 1014cm-3To 1 × 1016cm-3, for example, 1 × 10 can be used15cm-3Doping
Concentration.First body area is formed as trap shape shape, i.e. the first body area may be used as trap.Second body area is formed as column shape
Shape, that is, the second body area can also become column area, and the length in column area can adjust according to actual needs.Third body area
Be formed as the cryptomere shape being buried in the first epitaxial layer.In addition, source region, substrate can be formed in the first body area for being used as trap
It can be thinned for use as drain region.The power device can also include the conductive metal layer positioned at substrate back, the conduction
Metal layer is formed on the back side of the substrate after being thinned for use as drain electrode.It can be with shape in the top in the first body area and source region
At there is conductive metal layer, the conductive metal layer and the first body area and source contact are for use as source electrode.
The disclosure can be presented in a variety of manners, some of them example explained below.
Preparing substrate and epitaxial layer structure needed for Fig. 1 shows manufacture power device according to an embodiment of the present disclosure.
As shown in Figure 1, specifically, providing conventional chip as semiconductor substrate 1, the material of semiconductor substrate 1 can be, for example, Si.
Ion implanting can be carried out to semiconductor substrate 1 to form the semiconductor substrate 1 with the first conduction type (for example, N-type),
Extension is carried out in semiconductor substrate 1 to form the first epitaxial layer 2, continues extension on the first epitaxial layer 2 to form second
Epitaxial layer 3, the first epitaxial layer 2 and the second epitaxial layer 3 have conduction type identical with substrate, that is, the first conduction type (example
Such as, N-type).That is, the first epitaxial layer 2 and the second epitaxial layer 3 have carried out N doping, wherein the doping of the first epitaxial layer 2 is dense
Degree is greater than the doping concentration of the second epitaxial layer 3.It thus forms needed for manufacture power device according to an embodiment of the present disclosure
Preparing substrate and epitaxial layer structure.
Fig. 2 shows the power unit structures according to an embodiment of the present disclosure with hard mask opening layer.Such as Fig. 2 institute
Show, form hard mask layer above substrate shown in Fig. 1 and epitaxial layer structure, and photoetching is carried out to it, develops, tool is consequently formed
There is the hard mask layer of opening.The hard mask layer is formed directly on the upper surface of the second epitaxial layer.
Fig. 3 shows the power unit structure according to an embodiment of the present disclosure with deep trench.As shown in Figure 2 hard
The first epitaxial layer 2 and the second epitaxial layer 3 are performed etching at mask open, form deep trench.Deep trench is from the second epitaxial layer 3
Upper surface extends downwardly, and crosses the boundary of the first epitaxial layer 2 and the second epitaxial layer 3, extends in the first epitaxial layer 2.Shape
After deep trench, hard mask layer is removed.The deep trench can be formed as multiple as can be seen from Figure 3.
Fig. 4 shows the power unit structure according to an embodiment of the present disclosure with buried object area 5.As shown in Figure 4
Power unit structure in, be doped in zanjon trench bottom as shown in Figure 3, form the burial that is buried in the first epitaxial layer
The conduction type in body area 5, the buried object area 5 can be the second conduction type, for example, p-type.The doping concentration in the buried object area compared with
Low, the doping concentration range in the buried object area can be 1 × 1014cm-3To 1 × 1016cm-3, for example, 1 × 10 can be used15cm-3Doping concentration.Since the buried object area 5 is formed by being doped (for example, ion implanting) in deep channel bottom,
So the buried object area 5 is contacted with the bottom of deep trench.The buried object area 5 is buried in the first epitaxial layer, that is, is made only in
In first epitaxial layer.From fig. 4, it can be seen that the buried object area 5 can accordingly be formed as multiple with deep trench.
Fig. 5 shows the power unit structure according to an embodiment of the present disclosure with column area 4.As shown in Figure 4
Deep trench in carry out extension backfill to form column area 4, the extension backfill is realized by epi dopant growth, if
Epi dopant growth is excessive, then the doped growing object for protruding from 3 top of the second epitaxial layer can be etched away by etching technics.
The upper table of deep trench inside and the upper surface in the column area 4 and second epitaxial layer 3 is filled up in the column area 4 as a result,
Face flushes.The boundary of the second epitaxial layer 3 and the first epitaxial layer 2 is crossed since the deep trench is extended downwardly from the second epitaxial layer,
And it extends in the first epitaxial layer 2.Therefore, the column area 4 for filling deep trench can also extend downwardly more from the second epitaxial layer
The boundary of the second epitaxial layer 3 and the first epitaxial layer 2 is crossed, and is extended in the first epitaxial layer 2.Since column area 4 is filled into depth
The bottom of the groove and buried object area 5 buried is contacted with the bottom of deep trench, therefore, the buried object area 5 of burial is positioned at corresponding
It is contacted below column area 4 and with the column area 4.The conduction type in the column area 4 can be the second conduction type, example
Such as p-type.That is, the conduction type in column area 4 is identical as the conduction type in buried object area 5 of burial.The column
The doping concentration in area is greater than the doping concentration in the buried object area 5.The doping concentration range in the column area can for 5 ×
1014cm-3To 1 × 1016cm-3, for example, 5 × 10 can be used15cm-3Doping concentration.From fig. 5, it can be seen that the column area
It can accordingly be formed as multiple with deep trench and buried object area 5.
Fig. 6 shows the power unit structure according to an embodiment of the present disclosure with gate structure.As shown in fig. 6,
Gate structure is formed on the device architecture that Fig. 5 is formed, that is, the gate oxide 8 and grid that formation sequence stacks on the second epitaxial layer 2
Pole layer 9, the gate oxide 8 can be made of silica or high-k dielectric material.High-k dielectrics material for example can be
Such as hafnium oxide (HfO2), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminium oxide, hafnium oxide-oxidation
Aluminium (HfO2-A12O3) alloy, titanium nitride (TiN).Can by spin coating (SOD) technique on CVD, PVD, spin coating, dielectric or its
His suitable technology forms high-k dielectrics material.Grid layer 9 may, for example, be polycrystalline silicon grid layer.Gate oxide 8 and grid layer
9 are patterned, to form opening.As shown in fig. 6, gate oxide 8 and the formation planar gate structure of grid layer 9, however this field
Technical staff is also readily apparent that other gate structures, such as vertical gate structure.
Fig. 7 shows the power device according to an embodiment of the present disclosure with the area Jing Zhuanti 6 and the source region 7 being located therein
Structure.As shown in fig. 7, carrying out self-registered technology injection using the gate structure layer with opening shown in fig. 6 as mask with shape
At the area Jing Zhuanti 6, source region 7 is then formed inside the area Jing Zhuanti 6.The conduction type in the area Jing Zhuanti 6 can be second
Conduction type, such as p-type.Therefore, the conduction type one of the conduction type in the area Jing Zhuanti 6 and column area 4 and buried object area 5
It causes.The doping concentration in the area Jing Zhuanti 6 is greater than the doping concentration in column area 4, and the doping concentration in column area 4, which is greater than, buries
The doping concentration in body area 5.The conduction type of source region 7 can be the first conduction type, for example, N-type.Source region 7 is high-concentration dopant
, the doping of the source region may range from 5 × 1019cm-3To 5 × 1021cm-3, for example, can be 5 × 1020cm-3.Such as Fig. 7
It is shown, since the opening of the gate structure layer (gate oxide 8 and grid layer 9) in Fig. 6 as the mask of self-registered technology is corresponding
In column area 4, therefore, multiple areas Jing Zhuanti 6 are formed corresponding to multiple column areas 4.As shown in fig. 7, the area Jing Zhuanti 6 can be with
8 lower section of gate oxide is diffused laterally into below the opening.Separation there are two being respectively formed in each area Jing Zhuanti 6
Source region 7, each source region 7 can diffuse laterally into 8 lower section of gate oxide below the opening.
Fig. 8 shows the power device knot according to an embodiment of the present disclosure with dielectric insulation layer 10 and metal layer 11
Structure.As shown in figure 8, in power unit structure disposed thereon dielectric insulation layer 10 as shown in Figure 7, dielectric insulation layer 10 can be by
(such as, but not limited to) oxide of silicon, the nitride of silicon, the nitrogen oxides of silicon or oxynitride are formed.In dielectric insulation layer 10
In perform etching aperture to form the through-hole of the upper surface in the through area Jing Zhuanti 6 and/or source region 7.It is exhausted in the medium with through-hole
To form metal layer 11, the metal layer can be made 10 disposed thereon metal of edge layer of aluminium, copper or its alloy, can also be due to
The alloy of aluminium, copper and silicon is made, for example, the metal layer can be Al-Si-Cu alloy or aluminium copper, wherein the content of aluminium is accounted for
Than high main component.Due to the presence of the through-hole in dielectric insulation layer 10, metal layer 11 can go directly the area Jing Zhuanti 6 and/or
The upper surface of source region 7, to form the electrical contact with the area Jing Zhuanti 6 and/or source region 7.The metal layer may be used as power device
The source electrode of structure.
Fig. 9 shows the power unit structure according to an embodiment of the present disclosure with metal layer on back.Complete such as Fig. 8
Shown in after power semiconductor device structure, substrate back is carried out thinned, and the substrate back after being thinned carries out metal
Deposition is to form metal layer on back.The metal layer on back covers entire substrate back.Substrate after being thinned may be used as power device
The drain region of part structure, metal layer on back may be used as the drain electrode of power unit structure.
It is possible thereby to form super junction power device according to an embodiment of the present disclosure comprising by corresponding multiple trap shape bodies
The body plot structure that area 6, column area 4 and buried object area 5 form.The area Jing Zhuanti 6, column area 4 and buried object area 5 are formed in place
Downwards (that is, to substrate side in the first epitaxial layer 2 and the second epitaxial layer 3 above substrate 1 and from the surface of the second epitaxial layer 3
To) sequentially form.The area Jing Zhuanti 6 is formed in the second epitaxial layer 3, and column area 4 extends downwardly always from 6 bottom of the area Jing Zhuanti
The boundary between the first epitaxial layer 2 and the second epitaxial layer 3 is crossed to extend in the first epitaxial layer 2, buried object area 5 is formed in
It is contacted in one epitaxial layer 2 and with the bottom in column area 4.By the design structure in the three segment bodies area, embodiment of the disclosure
Very high voltage endurance capability may be implemented in super junction power device, such as realizes the breakdown voltage of 900V or more, while can be effective
Reduce conducting resistance.Buried object area in the first epitaxial layer 2 can also effectively adjust two kinds of charge balances, further mention
High voltage stability.Therefore, which can mitigate zanjon trench bottom electric field strength and the problems in excessively collect, and hit in raising
Snow slide tolerance ability can be effectively proposed while wearing voltage.In addition, this bilayer of the first epitaxial layer 2 and the second epitaxial layer 3 is outer
The structure prolonged can improve the reverse recovery characteristic of transistor.
It will be apparent to those skilled in the art that above-mentioned super junction power device structure is only one kind based on present inventive concept
Specific embodiment, rather than the limitation to protection scope of the present invention.In the case where meeting present inventive concept, those skilled in the art
Member can modify and substitute to device architecture of the invention.Device architecture after these modifications and substitutions equally falls into this
The protection scope of invention.
For example, can simplify to three-stage body plot structure for the purpose for simplifying technique, only be retained as the first body
The area Jing Zhuanti in area and column area as the second body area, without forming buried object area.Specifically, Figure 10 is shown according to this
The power unit structure of disclosed embodiment eliminated after buried object area.Its feature and power unit structure phase shown in Fig. 9
Together, in addition to eliminating the buried object area being located in the first epitaxial layer 2.
Figure 11 shows the process flow chart for manufacturing power device as shown in Figure 9.It is the following steps are included: on substrate
The first epitaxial layer of extension；The second epitaxial layer of extension on the first epitaxial layer；Hard mask layer is formed on the second epitaxial layer, to covering firmly
Film layer performs etching to form multiple openings；Multiple openings to the second epitaxial layer and the first epitaxial layer perform etching to be formed it is more
A deep trench；Deep trench extends in the first epitaxial layer from the second epitaxial layer；It is doped injection in the bottom of multiple deep trench,
Form multiple third bodies area；Epi dopant growth is carried out to multiple deep trench to form multiple columnar second body areas；Second
Multiple first bodies area is formed in epitaxial layer.Wherein, the first body area is formed using self-registered technology.
Obviously, manufacture the power device process flow can with the following steps are included: before forming the first body area
Gate oxide and grid layer are formed above second epitaxial layer；Source is formed in first body area after forming the first body area
Area；Dielectric insulation layer is formed above gate oxide and grid layer after forming source region and through-hole, deposited metal layer are connect with electricity
Touch the first body area and source region；The substrate bottom is carried out back thinning and deposits back metal on the substrate back after being thinned
Layer.
It can be applied to various electronic equipments according to the super junction power device of the embodiment of the present disclosure.For example, by integrated more
A such super junction power device and other devices (for example, transistor etc. of other forms), can form integrated circuit
(IC), electronic equipment and is thus constructed.Therefore, the disclosure additionally provides a kind of electronic equipment including above-mentioned power device.Electricity
Sub- equipment can also include and what integrated circuit cooperated shows the components such as screen and the wireless transceiver cooperated with integrated circuit.
This electronic equipment such as smart phone, computer, tablet computer (PC), artificial intelligence, wearable device, mobile power source etc..
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
Embodiment of the disclosure is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the present disclosure.The scope of the present disclosure is limited by appended claims and its equivalent.This public affairs is not departed from
The range opened, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in the disclosure
Within the scope of.
Claims (10)
1. a kind of power device, comprising:
Substrate；
First epitaxial layer is set on the substrate；
Second epitaxial layer is set on first epitaxial layer；
Multiple first bodies area is set in second epitaxial layer；
Multiple second bodies area, is set to the lower section in corresponding first body area；
Wherein, the multiple second body area extends downwardly into first epitaxial layer from second epitaxial layer, the multiple
The bottom in the second body area is located in first epitaxial layer.
2. power device according to claim 1, wherein second body area is column, and second body area
Doping concentration is less than the doping concentration in first body area.
3. power device according to claim 1, further includes:
Multiple third bodies area is set to the lower section in corresponding second body area and contacts with the bottom in the second body area.
4. power device according to claim 3, wherein the doping concentration in third body area is less than first body area
With the doping concentration in the second body area.
5. power device described in any one of -4 according to claim 1, wherein first body area, second body area and
Third body area all has the second conduction type.
6. power device according to claim 1 further includes the first conduction type being formed in first body area
Source region and the drain region for forming the first conduction type in the substrate.
7. power device according to claim 1, wherein the first epitaxial layer and the second epitaxial layer all have the first conductive-type
Type, and the doping concentration of the first epitaxial layer is greater than the doping concentration of the second epitaxial layer.
8. a kind of manufacturing method of power device, comprising:
The first epitaxial layer of extension on substrate；
The second epitaxial layer of extension on the first epitaxial layer；
Hard mask layer is formed on second epitaxial layer, the hard mask layer is performed etching to form multiple openings；
Multiple deep trench are formed to second epitaxial layer and performing etching for the first epitaxial layer in the multiple opening, it is described
Deep trench extends in first epitaxial layer from second epitaxial layer；
It is doped injection in the bottom of the multiple deep trench, forms multiple third bodies area；
Epi dopant growth is carried out to the multiple deep trench, forms multiple columnar second body areas；
Multiple first bodies area is formed in second epitaxial layer.
9. the manufacturing method of power device according to claim 8, further includes
Source region is formed in first body area；
The substrate bottom is carried out back thinning and metal layer on back makes, forms drain region.
10. a kind of electronic equipment, including at least partly being formed as the power device as described in any one of claims 1 to 7
Integrated circuit.
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| CN111244158A (en) * | 2020-01-21 | 2020-06-05 | 上海华虹宏力半导体制造有限公司 | Super junction device and manufacturing method thereof |
| CN111370305A (en) * | 2020-04-30 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Deep groove type super junction device and manufacturing method thereof |
| CN111883422A (en) * | 2020-07-16 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of super junction device |
| CN117476468A (en) * | 2023-12-26 | 2024-01-30 | 北京智芯微电子科技有限公司 | Super junction structure, manufacturing method thereof, super junction semiconductor device and semiconductor structure |
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| CN111244158A (en) * | 2020-01-21 | 2020-06-05 | 上海华虹宏力半导体制造有限公司 | Super junction device and manufacturing method thereof |
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Application publication date: 20190212 |