CN111244158B - Super junction device and manufacturing method thereof - Google Patents
Super junction device and manufacturing method thereof Download PDFInfo
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- CN111244158B CN111244158B CN202010069025.2A CN202010069025A CN111244158B CN 111244158 B CN111244158 B CN 111244158B CN 202010069025 A CN202010069025 A CN 202010069025A CN 111244158 B CN111244158 B CN 111244158B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 210000000746 body region Anatomy 0.000 claims abstract description 109
- 238000005468 ion implantation Methods 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 57
- 230000007547 defect Effects 0.000 claims abstract description 40
- 238000000137 annealing Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 11
- 230000002411 adverse Effects 0.000 abstract description 8
- 238000005530 etching Methods 0.000 description 5
- 230000002401 inhibitory effect Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Abstract
The invention discloses a super junction device, which comprises a super junction formed by alternately arranging P-type columns and N-type columns in a device unit area, wherein P-type column grooves are filled; the P-type body region is formed by superposing a first P-type doped region and a second P-type doped region; the first P-type doped region is formed by ion implantation and annealing promotion before the P-type column is formed, so that the depth of the first P-type doped region can be deepened without being limited by the process of the super junction and the junction depth of the P-type body region is deepened; the second P-type doped region is formed on two sides of the grid structure in a self-aligned mode through comprehensive ion implantation, and the second P-type doped region is used for adjusting threshold voltage of a formed channel. The invention also discloses a manufacturing method of the super junction device. The invention can deepen the depth of the body region, shield the adverse effect of surface defects of the super junction and improve the yield, and can avoid the influence on the performance and the threshold voltage of the super junction.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction device. The invention also relates to a manufacturing method of the super junction device.
Background
The super junction is composed of alternately arranged P-type thin layers also called P-type pillars (pilar) and N-type thin layers also called N-type pillars (N-type pillars) formed in a semiconductor substrate, and the device using the super junction is a super junction device such as a super junction MOSFET. The in vivo surface electric field (Resurf) reduction technology utilizing the charge balance of the P-type thin layer and the N-type thin layer can improve the reverse breakdown voltage of the device and keep smaller on-resistance.
The PN-spaced pilar structure of the superjunction is the biggest feature of the superjunction. There are two main methods for manufacturing the PN-spaced pilar structure, one is obtained by multiple epitaxy and ion implantation, and the other is manufactured by deep trench etching and Epitaxial (EPI) filling. The latter method is to manufacture a super junction device by a trench process, and it is necessary to etch a trench with a certain depth and width on an N-type doped epitaxial layer on the surface of a semiconductor substrate, such as a silicon substrate, and then fill a P-type doped silicon epitaxial layer on the etched trench by using an epitaxial Filling (EPI) method.
When the super junction is manufactured through deep trench, namely super junction trench etching and epitaxial filling processes, defects are easily formed in bulk silicon close to the surface due to the influence of epitaxial layer steps such as silicon steps (Step silicon) near the surface of the super junction trench, so that leakage failure of a device is caused.
In the prior art, a P-type body region is formed in a super junction device such as a super junction MOSFET, the P-type body region is formed by ion implantation and annealing and pushing after the trench of the super junction is filled, the bottom of the P-type body region is an N-type drift region corresponding to an N-type column, and a body diode is formed between the P-type body region and the N-type drift region. The vast majority of surface defects can be removed from the depletion region by deepening the depth of the P-type body region, so that the electric leakage of the device can be well improved. That is, if the adverse effects of surface defects of the superjunction need to be shielded, a deeper P-type body region is required.
In superjunction devices, the surface of the P-type body region is typically used to form a channel, and in particular, the surface of the P-type body region covered by a gate structure is used to form a channel. Because of the complex fabrication process of the Pillar (pilar) structures of the superjunction, i.e., the P-type Pillar and the N-type Pillar, the gate structure is typically placed after the fabrication of the Pillar structure is completed; the P-type body region is formed after the gate structure is formed. The existing processes of forming the columnar structure of the super junction, forming the grid structure and forming the P-type body region firstly have the following contradiction:
deep P-type body regions are required to shield the effect of surface defects of the superjunction, but the deep P-type body regions require a large thermal process, i.e., the temperature of the thermal anneal drive-in can be high and can be long; however, after the columnar structure is formed, a large thermal process is not desirable, because the large thermal process causes the P-type column impurities and the N-type column impurities in the columnar structure to diffuse into each other and compensate each other to reduce the net doping concentration, and thus the device performance may deteriorate greatly.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a super junction device which can deepen the depth of a body region and shield the adverse effect of surface defects of the super junction, thereby improving the product yield, and simultaneously can avoid the adverse effect of the annealing advancing thermal process of the body region on the performance of the super junction and simultaneously does not influence the threshold voltage of the device. The invention also provides a manufacturing method of the super junction device.
In order to solve the above technical problems, the device cell region of the super junction device provided by the present invention includes:
the super junction consists of P-type columns and N-type columns which are alternately arranged, and a super junction unit consists of one P-type column and one adjacent N-type column.
The P-type columns are composed of P-type epitaxial layers filled in super junction trenches, the N-type columns are composed of first N-type epitaxial layers located between the P-type columns, and the super junction trenches are formed in the first N-type epitaxial layers. In general, surface defects generated by filling the superjunction trenches are easily formed on the superjunction surface.
And a P-type body region formed by overlapping the first P-type doped region and the second P-type doped region is formed in the first N-type epitaxial layer.
The first P-type doped region is formed by ion implantation and annealing promotion before the P-type column, the doping concentration and depth of the first P-type doped region are determined by corresponding ion implantation and annealing promotion processes, and the annealing promotion process of the first P-type doped region has the characteristic of being not limited by the process conditions of the super junction comprising the P-type column, so that the depth of the first P-type doped region can be deepened, and the junction depth of the P-type body region is deepened accordingly. When the super junction surface is provided with surface defects, a depletion region of a body junction between the P-type body region and the first N-type epitaxial layer at the bottom is completely positioned at the bottom of the surface defects, electric leakage caused by the surface defects is prevented, and the deeper the junction depth of the P-type body region is, the better the effect of inhibiting the electric leakage caused by the surface defects is.
Each super junction device unit further comprises a grid structure, the grid structure is formed at the top of the corresponding super junction unit, the second P-type doped region is formed in the first P-type doped regions at two sides of the grid structure in a self-aligned mode through comprehensive ion implantation, the surface of the P-type body region covered by the grid structure is used for forming a channel, and the comprehensive ion implantation of the second P-type doped region is used for adjusting the threshold voltage for forming the channel.
A terminal region of the super junction device is further formed on the peripheral side of the device unit region; the terminal region comprises a P-type ring surrounding the device unit region, the first P-type doped region and the P-type ring have the same doped structure and are formed simultaneously by the same ion implantation and annealing advancing process, and the junction depth of the P-type body region is 1-5 microns.
In a further improvement, the first N-type epitaxial layer is formed on the surface of the semiconductor substrate.
The semiconductor substrate is a silicon substrate, the first N-type epitaxial layer is a silicon epitaxial layer, and the P-type epitaxial layer of the P-type column is a silicon epitaxial layer.
The further improvement is that the gate structure is a trench gate and comprises a gate trench, a gate dielectric layer formed on the inner side surface of the gate trench and a polysilicon gate filled in the gate trench.
The ion implantation of the first P-type doped region is comprehensive ion implantation; at least one side surface of the gate trench is positioned in the N-type column, and the depth of the gate trench is larger than the junction depth of the P-type body region.
The N+ doped source region is formed on the surface of the P-type body region at two sides of the trench gate, and the channel is connected with the source region and the N-type column at the bottom of the P-type body region when the device is conducted.
The grid structure is a planar grid and comprises a grid dielectric layer and a polysilicon gate which are sequentially formed on the surface of the super junction unit.
The ion implantation area of the first P type doped region is defined through photoetching, the P type body region extends to the bottom of the grid structure, and the grid structure also covers the surface of the N type column adjacent to the P type body region.
And the N+ doped source region is formed on the surface of the P-type body region at the side surface of the grid structure in a self-aligned mode, and the channel is connected with the source region and the N-type column when the device is conducted.
The further improvement is that an N+ doped drain region is formed at the bottom of the first N-type epitaxial layer, wherein the drain region is formed by thinned N+ doped semiconductor substrate or by thinned semiconductor substrate plus N+ back ion implantation.
A further improvement is that the ion implantation dosage of the first P-type doped region is 2e13cm -2 The junction depth of the P-type body region is 3 microns.
In order to solve the above technical problems, the method for manufacturing a super junction device according to the present invention includes the steps of:
step one, providing a first N-type epitaxial layer, and performing ion implantation and annealing promotion to form a first P-type doped region;
and adjusting the doping concentration and depth of the first P-type doped region through ion implantation and annealing advancing processes.
And step two, forming super junction grooves in the first N-type epitaxial layers, filling the P-type epitaxial layers in the super junction grooves to form P-type columns, and forming N-type columns by the first N-type epitaxial layers positioned between the P-type columns.
The P-type columns and the N-type columns are alternately arranged to form a super junction, and one P-type column and one adjacent N-type column form a super junction unit.
In general, surface defects generated by filling the superjunction trenches are easily formed on the superjunction surface.
And thirdly, forming a grid structure corresponding to each super junction device unit, wherein the grid structure is positioned at the top of the corresponding super junction unit.
And fourthly, performing overall ion implantation in the first P-type doped regions at two sides of the grid structure to form second P-type doped regions in a self-alignment mode.
And the P-type body region is formed by overlapping the first P-type doped region and the second P-type doped region.
Utilizing the characteristic that the annealing advancing process of the first P-type doped region in the first step is not limited by the process conditions of the super junction comprising the P-type column, so that the depth of the first P-type doped region can be deepened, and the junction depth of the P-type body region is deepened; when the super junction surface is provided with surface defects, a depletion region of a body junction between the P-type body region and the first N-type epitaxial layer at the bottom is completely positioned at the bottom of the surface defects, electric leakage caused by the surface defects is prevented, and the deeper the junction depth of the P-type body region is, the better the effect of inhibiting the electric leakage caused by the surface defects is.
The surface of the P-type body region covered by the gate structure is used for forming a channel, and the full ion implantation of the second P-type doped region is used for adjusting the threshold voltage for forming the channel.
A further improvement is that a termination region including a superjunction device is also formed on the peripheral side of the device cell region; the termination region includes a P-type ring surrounding the device cell region.
In the first step, the first P-type doped region and the P-type ring are formed simultaneously by adopting the same ion implantation and annealing promotion process. The junction depth of the P-type body region is 1-5 microns.
The implantation dosage of the ion implantation of the first P-type doped region is 2e13cm -2 The above.
In a further improvement, the first N-type epitaxial layer is formed on the surface of the semiconductor substrate.
The semiconductor substrate is a silicon substrate, the first N-type epitaxial layer is a silicon epitaxial layer, and the P-type epitaxial layer of the P-type column is a silicon epitaxial layer.
In the third step, the gate structure is a trench gate, and the method comprises the steps of forming a gate trench, forming a gate dielectric layer on the inner side surface of the gate trench, and filling a polysilicon gate in the gate trench.
The ion implantation of the first P-type doped region is comprehensive ion implantation; at least one side surface of the gate trench is positioned in the N-type column, and the depth of the gate trench is larger than the junction depth of the P-type body region.
And step four, the step of performing N+ injection on the surfaces of the P-type body regions at the two sides of the trench gate to form a source region, wherein the channel is connected with the source region and the N-type column at the bottom of the P-type body region when the device is conducted.
The method is characterized in that the grid structure is a planar grid, the forming step of the planar grid comprises the steps of sequentially forming a grid dielectric layer and a polysilicon gate on the surface of the super junction unit, and then photoetching is carried out to form the planar grid formed by overlapping the grid dielectric layer and the polysilicon gate only in the grid structure area.
The ion implantation region of the first P-type doped region in the first step is defined by photolithography, the P-type body region extends to the bottom of the gate structure, and the gate structure also covers the surface of the N-type column adjacent to the P-type body region.
And step four, the step of performing N+ injection on the surfaces of the P-type body regions at the two sides of the planar gate to form a source region, wherein the channel is connected with the source region and the N-type column when the device is conducted.
Further improvement comprises the step of forming an n+ doped drain region at the bottom of the first N-type epitaxial layer.
The drain region is directly formed after the N+ doped semiconductor substrate is thinned.
Or the drain region is formed by carrying out N+ back ion implantation on the thinned semiconductor substrate after thinning the semiconductor substrate.
The invention particularly sets the process structure of the P-type body region, divides the P-type body region into a superposition structure of the first P-type doped region and the second P-type doped region, and deepens the depth of the first P-type doped region to the extent that the adverse effect of the surface defect of the super junction can be shielded, thereby preventing electric leakage caused by the surface defect and improving the product yield.
Unlike the prior art that the P-type body region needs to be formed after the grid structure, the P-type body region is divided into the first P-type doped region and the second P-type doped region, the second P-type doped region is only needed to be formed after the grid structure, and the first P-type doped region is prevented from being formed before the super junction forming process, so that the thermal process required by the annealing promotion of the first P-type doped region is not limited by the super junction, that is, the P-type body region cannot be different from the thermal process in the prior art, the first P-type doped region can be adjusted to the required depth, the deepening of the first P-type doped region can be realized, the influence of the surface defect of the super junction, such as electric leakage, can be eliminated when the surface defect of the super junction appears, and meanwhile, the performance of the super junction cannot be adversely affected, that is, PN impurities of the super junction cannot be mutually expanded due to the deepening of the first P-type doped region.
Meanwhile, the second P-type doped region is formed after the grid electrode structure is formed, so that the second P-type doped region can realize the adjustment of the threshold voltage of the device, and the setting of the body region structure does not influence the threshold voltage of the device. In addition, the second P-type doped region can also enable the whole surface to have higher P-type body region doping concentration, because the second P-type doped region can compensate the doping loss of the super junction trench etching process to the P-type body region.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a schematic diagram of the structure of a super junction device according to a first embodiment of the present invention;
fig. 2 is a schematic structural view of a superjunction device according to a second embodiment of the present invention;
fig. 3A-3E are schematic structural views of the first embodiment of the super junction device according to the present invention at various steps in the method for manufacturing the same.
Detailed Description
The super junction device of the first embodiment of the invention:
FIG. 1 is a schematic diagram of a super junction device according to a first embodiment of the present invention; the device unit area of the super junction device in the first embodiment of the invention comprises:
the super junction consists of P-type columns 5 and N-type columns which are alternately arranged, and a super junction unit consists of one P-type column 5 and one adjacent N-type column.
The P-type columns 5 are composed of P-type epitaxial layers filled in the super junction trenches 4, the N-type columns are composed of first N-type epitaxial layers 2 positioned between the P-type columns 5, and the super junction trenches 4 are formed in the first N-type epitaxial layers 2; surface defects generated by filling the superjunction trenches 4 are easily formed on the superjunction surface. The area of formation of the surface defects is shown by the dashed box 101 in fig. 3D.
A P-type body region formed by overlapping the first P-type doped region 3 and the second P-type doped region 8 is formed in the first N-type epitaxial layer 2.
The first P-type doped region 3 is formed by ion implantation and annealing promotion before the P-type column 5 is formed, the doping concentration and depth of the first P-type doped region 3 are determined by corresponding ion implantation and annealing promotion processes, and the annealing promotion process of the first P-type doped region 3 has the characteristic of being not limited by the process conditions of the super junction comprising the P-type column 5, so that the depth of the first P-type doped region 3 can be deepened and thus the junction depth of the P-type body region is deepened. When the super junction surface is formed with surface defects, the depletion region of the body junction between the P-type body region and the first N-type epitaxial layer 2 at the bottom is completely located at the bottom of the surface defects, so that electric leakage caused by the surface defects is prevented, and the deeper the junction depth of the P-type body region, the better the effect of inhibiting electric leakage caused by the surface defects is. In the embodiment of the invention, the junction depth of the P-type body region is 1-5 microns. More preferably, the junction depth of the P-type body region is 3 microns.
Each super junction device unit further comprises a gate structure, the gate structure is formed at the top of the corresponding super junction unit, the second P-type doped region 8 is formed in the first P-type doped region 3 at two sides of the gate structure in a self-aligned manner through comprehensive ion implantation, the surface of the P-type body region covered by the gate structure is used for forming a channel, and the comprehensive ion implantation of the second P-type doped region 8 is used for adjusting the threshold voltage for forming the channel.
In the first embodiment of the present invention, a terminal region of a superjunction device is further formed on the peripheral side of the device cell region; the terminal region comprises a P-type ring surrounding the device unit region, the first P-type doped region 3 and the P-typeThe rings have the same doping structure and are formed simultaneously using the same ion implantation and anneal advancing processes. The implantation dosage of the ion implantation of the first P-type doped region 3 is 2e13cm -2 The above.
The first N-type epitaxial layer 2 is formed on the surface of the semiconductor substrate 1. Preferably, the semiconductor substrate 1 is a silicon substrate, the first N-type epitaxial layer 2 is a silicon epitaxial layer, and the P-type epitaxial layer of the P-type column 5 is a silicon epitaxial layer.
The gate structure is a trench gate and comprises a gate trench, a gate dielectric layer 6 formed on the inner side surface of the gate trench and a polysilicon gate 7 filled in the gate trench.
The ion implantation of the first P-type doped region 3 is full ion implantation; at least one side surface of the gate trench is positioned in the N-type column, and the depth of the gate trench is larger than the junction depth of the P-type body region. In fig. 1, two sides of the gate trench are located in the N-type pillars, so that the top of one of the N-type pillars can form two channels.
An n+ doped source region (not shown) is formed on the surface of the P-type body region on both sides of the trench gate, the channel connecting the source region and the N-type column at the bottom of the P-type body region when the device is turned on.
The n+ doped drain region is formed at the bottom of the first N-type epitaxial layer 2, and the drain region is formed by thinned n+ doped semiconductor substrate 1 or by thinned semiconductor substrate 1 plus n+ back ion implantation.
The first embodiment of the invention makes special settings on the process structure of the P-type body region, divides the P-type body region into a superposition structure of the first P-type doped region 3 and the second P-type doped region 8, and deepens the depth of the first P-type doped region 3 to the extent that the adverse effect of the surface defect of the super junction can be shielded, thereby preventing electric leakage caused by the surface defect;
unlike the prior art that the P-type body region needs to be formed after the gate structure, the P-type body region of the present invention is divided into the first P-type doped region 3 and the second P-type doped region 8, and the second P-type doped region 8 is formed after the gate structure, and the first P-type doped region 3 is formed before the super junction forming process, so that the thermal process required for annealing and advancing the first P-type doped region 3 will not be limited by the super junction, that is, the P-type body region cannot be adjusted to the desired depth unlike the limitation of the super junction on the thermal process in the prior art, the first embodiment of the present invention can enable the first P-type doped region 3 to be adjusted to the desired depth, so that deepening of the first P-type doped region 3 can be realized to eliminate the influence of the surface defect of the super junction, that is, such as electric leakage, generated when the surface defect occurs on the super junction surface, at the same time, the PN of the super junction will not be adversely affected by the super junction, that is not mutually expanded due to the deepening of the first P-type doped region 3.
Meanwhile, the second P-type doped region 8 of the first embodiment of the present invention is formed after the gate structure is formed, so that the second P-type doped region 8 can realize the adjustment of the threshold voltage of the device, and therefore, the setting of the body region structure of the first embodiment of the present invention does not affect the threshold voltage of the device. In addition, the second P-type doped region 8 of the first embodiment of the present invention can also enable the entire surface to have a higher doping concentration of the P-type body region, because the second P-type doped region 8 can compensate the doping loss of the P-type body region by the super junction trench etching process.
The second embodiment super junction device of the present invention:
the super junction device of the second embodiment of the present invention differs from the super junction device of the second embodiment of the present invention in that:
FIG. 2 is a schematic diagram of a super junction device according to a second embodiment of the present invention; the gate structure in the super junction device according to the second embodiment of the present invention is a planar gate, and includes a gate dielectric layer 6a and a polysilicon gate 7a sequentially formed on the surface of the super junction unit.
The ion implantation region of the first P-type doped region 3 is defined by photolithography, the P-type body region extends to the bottom of the gate structure, and the gate structure also covers the N-type column surface adjacent to the P-type body region.
And the N+ doped source region is formed on the surface of the P-type body region at the side surface of the grid structure in a self-aligned mode, and the channel is connected with the source region and the N-type column when the device is conducted.
The manufacturing method of the super junction device comprises the following steps:
as shown in fig. 3A to 3E, the structure of the super junction device according to the first embodiment of the present invention at each step of the method for manufacturing the super junction device is schematically shown; the method for manufacturing the super junction device according to the first embodiment of the present invention includes the steps of:
step one, as shown in fig. 3A, a first N-type epitaxial layer 2 is provided.
The first N-type epitaxial layer 2 is formed on the surface of the semiconductor substrate 1. Preferably, the semiconductor substrate 1 is a silicon substrate, the first N-type epitaxial layer 2 is a silicon epitaxial layer, and the P-type epitaxial layer of the P-type column 5 formed later is a silicon epitaxial layer.
As shown in fig. 3B, ion implantation and annealing promotion are performed to form a first P-type doped region 3; the doping concentration and depth of the first P-type doped region 3 are adjusted by ion implantation and annealing advancing processes.
Step two, as shown in fig. 3C, a super junction trench 4 is formed in the first N-type epitaxial layer 2.
As shown in fig. 3D, P-type epitaxial layers are filled in the super junction trenches 4 to form P-type columns 5, and the first N-type epitaxial layers 2 between the P-type columns 5 form N-type columns.
The P-type columns 5 and the N-type columns are alternately arranged to form a super junction, and one super junction unit is formed by one P-type column 5 and one adjacent N-type column.
Surface defects generated by filling the superjunction trenches 4 are easily formed on the superjunction surface. The area of surface defect formation is shown by the dashed box 101.
And step three, as shown in fig. 3E, forming a gate structure corresponding to each super junction device unit, wherein the gate structure is positioned at the top of the corresponding super junction unit.
In the method of the first embodiment of the present invention, the gate structure is a trench gate, and the method includes the steps of forming a gate trench, forming a gate dielectric layer 6 on the inner side surface of the gate trench, and filling a polysilicon gate 7 in the gate trench.
The ion implantation of the first P-type doped region 3 is full ion implantation; at least one side surface of the gate trench is positioned in the N-type column, and the depth of the gate trench is larger than the junction depth of the P-type body region.
And fourthly, performing overall ion implantation in the first P-type doped region 3 at the two sides of the grid structure to form a second P-type doped region 8 in a self-aligned mode.
A P-type body region formed by the superposition of the first P-type doped region 3 and the second P-type doped region 8.
Utilizing the characteristic that the annealing advancing process of the first P-type doped region 3 in the first step is not limited by the process conditions of the super junction comprising the P-type column, the depth of the first P-type doped region 3 can be deepened, and the junction depth of the P-type body region is deepened accordingly; when the super junction surface is formed with surface defects, the depletion region of the body junction between the P-type body region and the first N-type epitaxial layer 2 at the bottom is completely located at the bottom of the surface defects, so that electric leakage caused by the surface defects is prevented, and the deeper the junction depth of the P-type body region, the better the effect of inhibiting electric leakage caused by the surface defects is. In the method of the embodiment of the invention, the junction depth of the P-type body region is 1-5 microns. More preferably, the junction depth of the P-type body region is 3 microns.
The surface of the P-type body region covered by the gate structure is used to form a channel, and the full ion implantation of the second P-type doped region 8 is used to adjust the threshold voltage for forming the channel.
Forming a termination region including a super junction device on a peripheral side of the device cell region; the termination region includes a P-type ring surrounding the device cell region.
In the first step, the first P-type doped region 3 and the P-type ring are formed simultaneously by the same ion implantation and annealing process.
The implantation dosage of the ion implantation of the first P-type doped region 3 is 2e13cm -2 The above.
And step four, the step of performing N+ injection on the surfaces of the P-type body regions at the two sides of the trench gate to form a source region, wherein the channel is connected with the source region and the N-type column at the bottom of the P-type body region when the device is conducted.
And forming an N+ doped drain region at the bottom of the first N-type epitaxial layer 2.
The drain region is directly formed by thinning the n+ doped semiconductor substrate 1.
Alternatively, the drain region is formed by thinning the semiconductor substrate 1 and then performing n+ back ion implantation on the thinned semiconductor substrate 1.
The manufacturing method of the super junction device of the second embodiment of the invention comprises the following steps:
the difference from the method for manufacturing a super junction device according to the first embodiment of the present invention is that the method for manufacturing a super junction device according to the second embodiment of the present invention has the following features:
as shown in fig. 2, in the third step, the gate structure is a planar gate, and the forming step of the planar gate includes sequentially forming a gate dielectric layer 6a and a polysilicon gate 7a on the surface of the super junction unit, and then performing photolithography etching to form the planar gate formed by stacking the gate dielectric layer 6a and the polysilicon gate 7a only in the gate structure region.
The ion implantation region of the first P-type doped region 3 in the first step is defined by photolithography, the P-type body region extends to the bottom of the gate structure, and the gate structure also covers the N-type column surface adjacent to the P-type body region.
And step four, the step of performing N+ injection on the surfaces of the P-type body regions at the two sides of the planar gate to form a source region, wherein the channel is connected with the source region and the N-type column when the device is conducted.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (15)
1. A superjunction device, comprising in a device cell region of the superjunction device:
the super junction consists of P-type columns and N-type columns which are alternately arranged, and a super junction unit consists of one P-type column and one adjacent N-type column;
the P-type columns are composed of P-type epitaxial layers filled in the super junction grooves, the N-type columns are composed of first N-type epitaxial layers positioned between the P-type columns, and the super junction grooves are formed in the first N-type epitaxial layers; a P-type body region formed by overlapping a first P-type doped region and a second P-type doped region is formed in the first N-type epitaxial layer;
the first P-type doped region is formed by ion implantation and annealing promotion before the P-type column, the doping concentration and depth of the first P-type doped region are determined by corresponding ion implantation and annealing promotion processes, and the annealing promotion process of the first P-type doped region has the characteristic of being not limited by the process conditions of the super junction comprising the P-type column, so that the depth of the first P-type doped region can be deepened and the junction depth of the P-type body region is deepened; when a surface defect is formed on the surface of the super junction, the depth of the first P-type doped region enables a depletion region of the P-type body region meeting the requirement of a body junction between the P-type body region and the first N-type epitaxial layer at the bottom to be completely positioned at the bottom of the surface defect;
each super junction device unit further comprises a grid structure, the grid structure is formed at the top of the corresponding super junction unit, the second P-type doped region is formed in the first P-type doped regions at two sides of the grid structure in a self-aligned mode through comprehensive ion implantation, the surface of the P-type body region covered by the grid structure is used for forming a channel, and the comprehensive ion implantation of the second P-type doped region is used for adjusting the threshold voltage for forming the channel.
2. The superjunction device of claim 1, wherein: a terminal region of a super junction device is formed on the peripheral side of the device unit region; the terminal region comprises a P-type ring surrounding the device unit region, the first P-type doped region and the P-type ring have the same doped structure and are formed simultaneously by the same ion implantation and annealing advancing process, and the junction depth of the P-type body region is 1-5 microns.
3. The superjunction device of claim 2, wherein: the first N-type epitaxial layer is formed on the surface of the semiconductor substrate.
4. The superjunction device of claim 3, wherein: the semiconductor substrate is a silicon substrate, the first N-type epitaxial layer is a silicon epitaxial layer, and the P-type epitaxial layer of the P-type column is a silicon epitaxial layer.
5. The superjunction device of claim 3, wherein: the gate structure is a trench gate and comprises a gate trench, a gate dielectric layer formed on the inner side surface of the gate trench and a polysilicon gate filled in the gate trench;
the ion implantation of the first P-type doped region is comprehensive ion implantation; at least one side surface of the grid groove is positioned in the N-type column, and the depth of the grid groove is larger than the junction depth of the P-type body region;
the N+ doped source region is formed on the surface of the P-type body region at two sides of the trench gate, and the channel is connected with the source region and the N-type column at the bottom of the P-type body region when the device is conducted.
6. The superjunction device of claim 3, wherein: the grid structure is a planar grid and comprises a grid dielectric layer and a polysilicon gate which are sequentially formed on the surface of the super junction unit;
the ion implantation area of the first P-type doped region is defined through photoetching, the P-type body region extends to the bottom of the grid structure, and the grid structure also covers the surface of the N-type column adjacent to the P-type body region;
and the N+ doped source region is formed on the surface of the P-type body region at the side surface of the grid structure in a self-aligned mode, and the channel is connected with the source region and the N-type column when the device is conducted.
7. The superjunction device of claim 5 or 6, wherein: and the N+ doped drain region is formed at the bottom of the first N-type epitaxial layer, and consists of the thinned N+ doped semiconductor substrate or is formed by adding N+ into the thinned semiconductor substrate and performing back ion implantation.
8. The superjunction device of claim 2, wherein: the implantation dosage of the ion implantation of the first P-type doped region is 2e13cm -2 The junction depth of the P-type body region is 3 microns.
9. A method of fabricating a superjunction device, the step of forming a device cell region of the superjunction device comprising:
step one, providing a first N-type epitaxial layer, and performing ion implantation and annealing promotion to form a first P-type doped region;
adjusting the doping concentration and depth of the first P-type doped region through ion implantation and annealing advancing processes;
step two, forming super junction grooves in the first N-type epitaxial layers, filling P-type epitaxial layers in the super junction grooves to form P-type columns, and forming N-type columns by the first N-type epitaxial layers positioned between the P-type columns;
the P-type columns and the N-type columns are alternately arranged to form a super junction, and one P-type column and one adjacent N-type column form a super junction unit;
forming a grid structure corresponding to each super junction device unit, wherein the grid structure is positioned at the top of the corresponding super junction unit;
step four, performing overall ion implantation in the first P-type doped regions at two sides of the grid structure to form second P-type doped regions in a self-alignment manner;
overlapping the first P-type doped region and the second P-type doped region to form a P-type body region;
utilizing the characteristic that the annealing advancing process of the first P-type doped region in the first step is not limited by the process conditions of the super junction comprising the P-type column, so that the depth of the first P-type doped region can be deepened, and the junction depth of the P-type body region is deepened; when a surface defect is formed on the surface of the super junction, the depth of the first P-type doped region enables a depletion region of the P-type body region meeting the requirement of a body junction between the P-type body region and the first N-type epitaxial layer at the bottom to be completely positioned at the bottom of the surface defect;
the surface of the P-type body region covered by the gate structure is used for forming a channel, and the full ion implantation of the second P-type doped region is used for adjusting the threshold voltage for forming the channel.
10. The method of fabricating a superjunction device according to claim 9, wherein: forming a termination region including a super junction device on a peripheral side of the device cell region; the terminal region comprises a P-type ring surrounding the device unit region;
in the first step, the first P-type doped region and the P-type ring are formed simultaneously by adopting the same ion implantation and annealing advancing process; the junction depth of the P-type body region is 1-5 microns
The implantation dosage of the ion implantation of the first P-type doped region is 2e13cm -2 The above.
11. The method of fabricating a superjunction device according to claim 10, wherein: the first N-type epitaxial layer is formed on the surface of the semiconductor substrate.
12. The method of fabricating a superjunction device of claim 11, wherein: the semiconductor substrate is a silicon substrate, the first N-type epitaxial layer is a silicon epitaxial layer, and the P-type epitaxial layer of the P-type column is a silicon epitaxial layer.
13. The method of fabricating a superjunction device of claim 11, wherein: the third step, the gate structure is a trench gate, and comprises the steps of forming a gate trench, forming a gate dielectric layer on the inner side surface of the gate trench and filling a polysilicon gate in the gate trench;
the ion implantation of the first P-type doped region is comprehensive ion implantation; at least one side surface of the grid groove is positioned in the N-type column, and the depth of the grid groove is larger than the junction depth of the P-type body region;
and step four, the step of performing N+ injection on the surfaces of the P-type body regions at the two sides of the trench gate to form a source region, wherein the channel is connected with the source region and the N-type column at the bottom of the P-type body region when the device is conducted.
14. The method of fabricating a superjunction device of claim 11, wherein: the grid structure is a planar grid, the forming step of the planar grid comprises the steps of sequentially forming a grid dielectric layer and a polysilicon gate on the surface of the super junction unit, and then performing photoetching to form the planar grid formed by overlapping the grid dielectric layer and the polysilicon gate only in the region of the grid structure;
the ion implantation area of the first P-type doped region in the first step is defined by photoetching, the P-type body region extends to the bottom of the grid structure, and the grid structure also covers the surface of the N-type column adjacent to the P-type body region;
and step four, the step of performing N+ injection on the surfaces of the P-type body regions at the two sides of the planar gate to form a source region, wherein the channel is connected with the source region and the N-type column when the device is conducted.
15. A method of fabricating a superjunction device according to claim 13 or 14, characterised in that: the method further comprises the step of forming an N+ doped drain region at the bottom of the first N-type epitaxial layer;
the drain region is directly formed after the N+ doped semiconductor substrate is thinned;
or the drain region is formed by carrying out N+ back ion implantation on the thinned semiconductor substrate after thinning the semiconductor substrate.
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| CN102479699A (en) * | 2010-11-25 | 2012-05-30 | 上海华虹Nec电子有限公司 | Manufacturing method of super-junction semiconductor device structure |
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