CN107342226A - The manufacture method of extra small unit size longitudinal direction super-junction semiconductor device - Google Patents

The manufacture method of extra small unit size longitudinal direction super-junction semiconductor device Download PDF

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CN107342226A
CN107342226A CN201710591038.4A CN201710591038A CN107342226A CN 107342226 A CN107342226 A CN 107342226A CN 201710591038 A CN201710591038 A CN 201710591038A CN 107342226 A CN107342226 A CN 107342226A
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main
super
hard mask
layer
junction
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CN201710591038.4A
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Chinese (zh)
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朱袁正
李宗清
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无锡新洁能股份有限公司
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Publication of CN107342226A publication Critical patent/CN107342226A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666Vertical transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

Abstract

The present invention relates to a kind of manufacture method of extra small unit size longitudinal direction super-junction semiconductor device, this method is deep plough groove etched using being carried out using hard mask layer on the first conductive type semiconductor substrate;Deposit one layer of second conductive type epitaxial layer;Anisotropic etching is carried out again, removes deep trench bottom epitaxial layer;Carry out the first conductive type impurity injection;Deposit the first conductive type epitaxial layer filling deep trench;The first main surface of semiconductor substrate is planarized, and remove hard mask layer, second conductive type epitaxial layer of zanjon groove sidewall forms the second conductivity type columns of longitudinal super-junction structure, and the first conduction type substrate and the first conductive type epitaxial layer respectively constitute first the first post of conduction type and first the second post of conduction type.The super-junction structure of this method manufacture, the unit size of super-junction structure can be significantly reduced in the case where not increasing technology difficulty, while break limitation of the existing process ability to the second conductivity type columns width.

Description

The manufacture method of extra small unit size longitudinal direction super-junction semiconductor device

Technical field

The present invention relates to a kind of manufacture method of super-junction semiconductor device, especially a kind of extra small unit size longitudinal direction superjunction The manufacture method of semiconductor devices.

Background technology

In mesohigh power semiconductor field, longitudinal super-junction structure(Super Junction)Adopted extensively With contrasting conventional power MOSFET element, super-junction structure can obtain that more excellent device is pressure-resistant to close with the compromise of conducting resistance System.Super-junction structure is formed in the drift region of semiconductor devices, and drift layer is extended to from semiconductor device surface through-thickness In vivo, super-junction structure includes N conductivity type columns(N posts)With P conductivity type columns(P posts), N posts replace with P posts to be provided adjacent to form Multiple P-N posts to formed super-junction structure.N posts have N conductive type impurities, and P posts have P conductive type impurities.When with super During the MOSFET element cut-off of junction structure, N posts and P posts in super-junction structure are depleted respectively, and depletion layer is from each N posts and P posts Between P-N junction interface extension, charge balance can be kept by controlling the impurity concentration in P posts and N posts, therefore depletion layer prolongs Stretch and completely depleted N posts and P posts, so as to which supports is pressure-resistant.When break-over of device, due to the resistance of superjunction devices drift region Rate is lower, so the conducting resistance of superjunction devices can be greatly lowered compared with commonplace components.Using 600V super-junction MOSFET devices as Example, the more common VDMOS device of its specific on-resistance can reduce by 70% or so.

Influence that superjunction devices is pressure-resistant mainly following factor:1), super-junction structure depth(Thickness);2), superjunction devices The unit size of middle super-junction structure(pitch);3), drift region impurity concentration.Because although the impurity concentration reduction of drift region can It is pressure-resistant to improve, but device on-resistance can be increased.But in actual process, the depth of P posts can be increased by improving super-junction structure depth Wide ratio, it is difficult to increase considerably to increase device manufacture difficulty and manufacturing cost, super-junction structure depth.Therefore, superjunction product is improved Performance, it is general using cellular size is reduced, reduce the mode of the resistivity of drift region.Using the unit size for reducing super-junction structure It is mode the most frequently used in current actual product, the unit size of super-junction structure refers to N column dimensions and P column dimension sums.Reduce The unit size of super-junction structure can reduce device it is pressure-resistant when bottom device depletion layer curvature, improve device it is pressure-resistant.Work as drift region During concentration increase, device is pressure-resistant to be declined, but the pressure-resistant fall of device of smaller super-junction structure unit size also can be smaller.

Further, since when N-type super-junction semiconductor device turns on, only N columnar regions are as current flow paths, therefore most When small unit size is identical, current flow paths can be effectively increased by reducing P post region field width degree, reduce device on-resistance.

The preparation difficulty of longitudinal super-junction structure can steeply rise with the increase of super-junction structure depth-to-width ratio in drift region.At present Main longitudinal super-junction structure manufacture method has two kinds.A kind of is multiple extension, photoetching, injection, the scheme of annealing, uses the party During case, due to make the p-type injection region between different epitaxial layers be connected it is necessary to be annealed using high temperature knot, resulting P The increase of P posts width, limits the reduction of super-junction structure unit size during type impurity horizontal proliferation.If use the outer of more numbers Prolong, to reduce epitaxial thickness, if reducing knot temperature and P post horizontal proliferation, manufacturing cost certainly will be increased.Therefore it is general current When 600V products use program batch micro operations, more from 4~6 extensions, P posts width is typically in more than 6um, device pitch Typically in more than 10um.The manufacture method of another super-junction structure is the deep trench as referred in United States Patent (USP) US7601597B2 Etch, the mode manufacture of extension filling, the P post width in drift region is approximately equal to zanjon well width.When the list of super-junction structure Elemental size reduce when, certainly will zanjon well width be reduced, with reduce P posts width (because N-type device in, the N posts area of super-junction structure Domain is only current flow paths, if only to reduce N posts area's size to reduce super-junction structure size, break-over of device characteristic on the contrary can It is deteriorated).Zanjon well width is reduced under conditions of depth is constant means bigger groove depth-to-width ratio, and bigger aspect ratio trench The problem of very big can be run into etching and filling, at this stage by taking 600V superjunction as an example, be limited by etching and fill process ability System, using the volume production product P posts width of the program typically between 3~6um, device super-junction structure unit size is generally higher than P More than twice of post width.And when manufacturing super-junction semiconductor device with above two ways, under the conditions of phase isomorphism unit size, P Post restricted width and technological limits ability, can not further reduce.

As can be seen here, if it is desired to further reducing longitudinal super-junction structure unit size, and technology difficulty can not increased In the case of reach the condition of volume production, existing process program can not meet requirement.

The content of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art, there is provided a kind of extra small unit size longitudinal direction superjunction half The manufacture method of conductor device, it can effectively solve the technique run into when existing longitudinal super-junction structure unit size reduces Limitation, in the case where not increasing process costs and technology difficulty, is reduced significantly super-junction structure unit size.

According to technical scheme provided by the invention, the manufacturer of the extra small unit size longitudinal direction super-junction semiconductor device Method, it is characterized in that, comprise the following steps:

(1)The first conductive type semiconductor base with the first main surface and the corresponding with the first interarea second main surface is provided Plate;

(2)One layer of hard mask layer is deposited on the first main surface of semiconductor substrate, etching hard mask layer forms multiple hard masks Opening, hard mask open extend to the first main surface, and the width of hard mask open is W1, and the spacing of adjacent hard mask open is W2;

(3)The first main surface in hard mask open is etched, it is interior on the first major surface to form multiple deep trench, the deep trench Semiconductor-based intralamellar part is extended to from the first interarea along semiconductor-based plate thickness direction;Zanjon groove sidewall and semiconductor substrate edge are thick For the inclination angle a spent on direction between 0~10 degree, zanjon groove bottom width is W3;

(4)In the second conductive type epitaxial layer that first main surface deposition a layer thickness is W4, W4<1/2×W3;

(5)Perform etching on the first major surface, remove the second conductive type epitaxial layer of zanjon trench bottom;Retain deep trench side The second conductive type epitaxial layer on wall;

(6)The first conductive type impurity injection is carried out on the first main surface of semiconductor;The first conductive-type is formed in zanjon trench bottom Type compensating basin;

(7)In the first main conductive type epitaxial layer of surface deposition first, the first conductive type epitaxial layer fills up deep trench;

(8)Planarization process is carried out to the first main surface, the first conductive type epitaxial layer on the first main surface is removed and covers firmly Mold layer;Second conductive type epitaxial layer of zanjon groove sidewall forms the second conductivity type columns of super-junction structure, the first conduction type Substrate and the first conductive type epitaxial layer respectively constitute first the first post of conduction type and first the second post of conduction type.

In a detailed embodiment, the hard mask layer includes LPTEOS, thermal oxide silica adds chemical gaseous phase Deposition silica or thermal silicon dioxide add silicon nitride.

In a detailed embodiment, the hard mask A/F W1 and adjacent hard mask extended distance W2 difference phase Deng.

In a detailed embodiment, the manufacture method is used to manufacture longitudinal superjunction diode, the insulation of longitudinal superjunction Gate field-effect transistor, longitudinal superjunction IGBT.

The technical scheme in United States Patent (USP) US7601597B2 is contrasted, under the limitation of identical etching and fill process ability, Assuming that the permission width of zanjon channel opening is W1, the technical scheme in patent US7601597B2, the superjunction semiconductor of formation are used The minimum superjunction unit size of device(pitch)It is naturally larger than W1, generally more than twice of W1.And use the skill of this patent Art, the minimum superjunction unit size of the super-junction semiconductor device formed(pitch)Certainly less than W1.And second in the present invention Conductivity type columns width depends on and step 4)The thickness of the second conductive type epitaxial layer of middle deposit, is not limited by technological limits ability System.Therefore the width of the second conductivity type columns in super-junction structure unit can be effectively reduced, increases current flow paths, is reduced The conducting resistance of device.In addition, step 6)In the first conductive type impurity injection, can effectively suppress due to deep plough groove etched The difference of bottom spacing, prevents charge unbalance between adjacent cellular between adjacent second conductive type post caused by Sidewall angles And the difference of current density.

Brief description of the drawings

Accompanying drawing 1 show the cross section structure diagram that the embodiment of the present invention forms semiconductor substrate;

Accompanying drawing 2 show the cross section structure diagram that the embodiment of the present invention is formed after hard mask opening 12;

Accompanying drawing 3 show the cross section structure diagram that the embodiment of the present invention is formed after deep trench 13;

Accompanying drawing 4 show the cross section structure diagram that the embodiment of the present invention is formed after p-type epitaxial layer 14;

Accompanying drawing 5 show the cross section structure diagram after etching p-type of embodiment of the present invention epitaxial layer 14;

Accompanying drawing 6 show the cross section structure diagram that the embodiment of the present invention is formed behind N+ types compensating basin 21;

Accompanying drawing 7 show the cross section structure diagram that the embodiment of the present invention is formed after N-type epitaxy layer 15;

Accompanying drawing 8 show the sectional structure signal that the embodiment of the present invention is formed after the first post of N-type 22, the second posts of N 23 and P posts 24 Figure;

Accompanying drawing 9 show longitudinal superjunction MOS device cross section structure diagram that the embodiment of the present invention is formed after the MOS structure of surface;

Description of reference numerals:The interareas of 001- first;The interareas of 002- second;01-N types drift region;02-N+ type substrates;11- hard masks Layer;12- hard mask layer openings;13- deep trench;14-P type epitaxial layers;15-N type epitaxial layers;21-N+ types compensating basin;22-N types One post;The post of 23-N types second;24-P type posts;25-P+ Xing Ti areas;26- gate oxides;27- gate electrodes;28-N+ type source regions;29- Insulating medium layer;30- source metals;31- drain metals.

Embodiment

Below by taking the super node MOSFET of N-type trench gate longitudinal direction as an example, the present invention is made into one with reference to specific drawings and examples Walk explanation.For N-type super-junction semiconductor device, first conduction type is N-type, and second conduction type is P-type conduction; For p-type super-junction semiconductor device, first conduction type is p-type.

As shown in figure 8, the extra small unit size longitudinal direction super-junction semiconductor device includes semiconductor substrate, semiconductor substrate For with the N-type semiconductor substrate including the first main surface 001 and the corresponding with the first interarea 001 second main surface 002;Institute N-type semiconductor substrate is stated by the N-type drift layer 01 including the first interarea 001 and the structure of N+ types substrate 02 including the second interarea 002 Into;It is provided with multiple deep trench in the N-type drift layer 01, the deep trench is from the first main surface 001 along semiconductor-based plate thickness Direction is extended to inside N-type drift layer 01;Zanjon groove sidewall is with the inclination angle a on semiconductor substrate through-thickness between 0~10 Between degree, zanjon groove bottom width is W3;There is p-type post 24 in zanjon groove sidewall, zanjon trench bottom has N-type compensating basin 21, The second post of filling N-type 23 in deep trench, N-type drift layer 01 forms the first post of N-type 22.

As shown in figure 9, the first main surface 001 is provided with P+ type body area 25, the upper surface in P+ type body area 25 is provided with N+ source regions It is provided with multiple gate grooves in 28, N+ source regions 28, gate groove extends to the first post of N-type 22 and the second post of N-type 23, on gate groove inwall Provided with gate oxide 26;Gate electrode 27 is provided with gate oxide 26;N+ source regions 28 are provided with insulating medium layer 29;P+ type body area 25 The source metal 30 of Ohmic contact is provided with the surface of N+ source regions 28;Second main surface 002 is provided with and the Ohmic contact of N+ substrates 02 Drain metal 31.

The manufacture method of the extra small unit size longitudinal direction super-junction semiconductor device, comprises the following steps:

(1), as shown in Figure 1, there is provided there is the N-type semiconductor substrate of two opposing main faces, two relative main surfaces include the One main surface 001 and the second main surface 002 corresponding with the first main surface 001;N-type semiconductor substrate is by including the second main table The N+ types substrate 02 in face 002 and N-type drift layer 01 including the first main surface 001 are formed;

(2), as shown in Fig. 2 one layer is deposited on the first main surface 001 of semiconductor substrate has high etch with semi-conducting material The hard mask layer 11 of ratio is selected, usually if semiconductor substrate is silicon materials, silica, silicon nitride etc. can be used to form Hard mask layer 11;Hard mask layer 11 is optionally sheltered and etches, to form multiple hard mask opens 12, A/F W1, It is W2 with the adjacent spacing of hard mask open 12;W2 is less than W1;In the present embodiment, W2=5um, W1 is taken to be equal to 7um;

The hard mask layer 11 can include LPTEOS, thermal oxide silica adds chemical vapor deposition silica or hot dioxy SiClx adds silicon nitride etc.;The width W1 of hard mask opening 12 and and adjacent hard mask opening 12 distance W2 difference it is equal;

(3), as shown in figure 3, by above-mentioned hard mask open 12, using anisotropic etching method on the first main surface 001 Interior to form multiple deep trench 13, the deep trench 13 extends to N-type drift from the first main surface 001 along semiconductor-based plate thickness direction Move inside layer 01;Inclination angle a in the side wall of deep trench 13 and semiconductor substrate through-thickness is between 0~10 degree, deep trench 13 bottom width is W3;By taking 600V products as an example, the depth of general deep trench 13 is counted using inclination angle a as 5 degree in 40um or so Calculate, bottom width W3 is in 3.5um or so for deep trench 13;

(4), as shown in figure 4, on the first main surface 001 of the semiconductor substrate deposit a layer thickness be W4 p-type extension Layer 14, there is the second conductive type epitaxial layer in the hard mask on the side wall of deep trench 13 and bottom and the first main surface 001 14 form;Thickness W4=1/2 of p-type epitaxial layer 14 × (W1-W2), and W4<1/2 × W3, in the present embodiment, W4 values are 1/ 2 × (W1-W2)=1um, meets W4<1/2 × W3 condition;

(5), as shown in figure 5, carrying out anisotropic etching on the first main surface 001, by controlling etch period, can remove The p-type epitaxial layer 14 of the bottom of deep trench 13;Due to being etched for anisotropy, the p-type epitaxial layer 14 in the side wall of deep trench 13 is protected Stay;Due to the presence of hard mask layer 11, in addition to surface p-type epitaxial layer 14, remaining structure on the first main surface 001 is not carved Erosion;

(6), as shown in fig. 6, on the main surface 001 of semiconductor first carry out N-type impurity injection, control Implantation Energy, make impurity Hard mask layer 11 is cannot pass through, due to the presence of hard mask layer 11, N-type impurity injection is substantially injected only in the bottom of deep trench 13 Portion, and form N+ types compensating basin 21 in the bottom of deep trench 13;

(7), as shown in fig. 7, depositing N-type epitaxy layer 15 on the main surface 001 of semiconductor first, N-type epitaxy layer 15 fills up deep trench 13;The impurity concentration of N-type epitaxy layer 15 of filling can select the impurity concentration equal to drift layer 01, can also be not equal to drift layer 01 impurity concentration;Adjust N-type epitaxy layer 15 and the impurity concentration of p-type epitaxial layer 14, it is ensured that superjunction devices charge balance;

(8), as shown in figure 8, using planarization etc. conventional semiconductor process, the main surface of semiconductor substrate first 001 is put down Smoothization, more N-type epitaxy layers 15 is removed, and remove hard mask layer 11;The p-type epitaxial layer 14 of the left and right sides wall of deep trench 13 is distinguished The p-type post 24 of super-junction structure is formed, the N-type drift layer 01 adjacent with p-type post 24 and N-type epitaxy layer 15 respectively constitute N-type first Post 22 and the second post of N-type 23;

The wherein top width of the first post of N-type 22 is approximately equal to W2, is in the present embodiment 5um, and the top width of the second post of N-type 23 is about W1-W4=5um, the bottom width of the second post of N-type 23 is about W3-2 × W4=1.5um.

(9), using conventional semiconductor process, form the other structures of super-junction semiconductor device, include but is not limited to:Half The top etch gate groove of the first post of N-type 22 and the second post of N-type 23 on the main surface 001 of conductor first, growth thermal oxide layer are formed Gate oxide 26;Simultaneously etches polycrystalline silicon is filled, forms gate electrode 27;Selective implantation p type impurity and knot, form P+ type body area 25;Selective implantation N-type impurity is simultaneously annealed, and forms N+ source regions 28;Deposit silica or phosphorosilicate glass etc. and form dielectric Layer 29;Insulating medium layer 29 is etched, and layer of metal is deposited on the main surface 001 of semiconductor first, is formed and P+ type body area 25 With the source metal 30 of the Ohmic contact of N+ source regions 28;Layer of metal is deposited on the main surface 002 of semiconductor second, is formed and is served as a contrast with N+ The drain metal 31 of the Ohmic contact of bottom 02.

Above-mentioned manufacture method can be used for manufacturing longitudinal superjunction diode, longitudinal superjunction isolated gate FET, longitudinally surpass Tie IGBT etc..

The technical scheme in United States Patent (USP) US7601597B2 is contrasted, under the limitation of identical etching and fill process ability, Assuming that in the case where ensureing deep plough groove etched and loading production capacity power, the permission width of zanjon channel opening is 7um, then using special Technical scheme in sharp US7601597B2, the minimum superjunction unit size of the super-junction semiconductor device of formation(pitch)It is inevitable big In 7um, to ensure enough current flow paths width, therefore minimum superjunction unit size(pitch)Generally twice of 7um More than, i.e., the minimum dimension of each P/N repeat units is in 14um or so.And use in the present embodiment, the superjunction formed is partly led The minimum superjunction unit size of body device(pitch)About W2+W4=6um.Smaller superjunction unit size(pitch)Can be Under conditions of ensureing that device is pressure-resistant, the denseer drift layer concentration of use, therefore can further reduce device on-resistance.

Secondly, contrast US7601597B2 in technical scheme, the present invention in p-type post width depend on step 4 in deposit The thickness of p-type epitaxial layer 14, do not limited by deep plough groove etched and fill process limit capacity, using the P post width of the present embodiment About 1um;Such as using the technical scheme in US7601597B2, then P posts width is limited by deep plough groove etched and filling capacity, Under the conditions of the present embodiment identical technological ability, then P posts minimum widith is about 7um.Due to P posts when superjunction devices turns on simultaneously Current flowing is not involved in, only plays a part of having lateral depletion when device ends, therefore under the conditions of identical pitch, P post width Narrower, break-over of device characteristic is better.

In addition, in actual process, due to the uniformity of deep trench to be ensured filling, in general zanjon groove sidewall and half All there is certain inclination angle in the thickness direction of conductor substrate, thus can cause the bottom width of the second post of N-type 23 compared with the first post of N-type 22 Less than normal, the first conductive type impurity in step 6 injects the N+ types compensating basin 21 to be formed and is in the bottom of the second post of N-type 23, can be with Effectively suppress due to N-type 23 bottom widths of the second post smaller the problem of causing local conducting resistance increase, prevent adjacent member The difference of charge unbalance and current density between born of the same parents.

Above to the present invention and embodiments thereof be described, this describe it is no restricted, shown in accompanying drawing also only It is one of embodiments of the present invention, actual structure is not limited thereto.All in all if the ordinary skill people of this area Member is enlightened by it, without departing from the spirit of the invention, similar to the technical scheme without designing for creativeness Frame mode and embodiment, protection scope of the present invention all should be belonged to.

Claims (4)

1. a kind of manufacture method of extra small unit size longitudinal direction super-junction semiconductor device, it is characterized in that, comprise the following steps:
(1)Offer has the first main surface(001)And with the first main surface(001)The second corresponding main surface(002) One conductive type semiconductor substrate;
(2)On the first main surface of semiconductor substrate(001)One layer of hard mask layer of upper deposit(11), etch hard mask layer(11)Shape Into multiple hard mask opens(12), hard mask open(12)Extend to the first main surface(001), hard mask open(12)Width For W1, adjacent hard mask open(12)Spacing be W2;
(3)Etch hard mask open(12)The first interior main surface(001), on the first main surface(001)It is upper to form multiple zanjons Groove(13), the deep trench(13)From the first main surface(001)Extended to along semiconductor-based plate thickness direction in semiconductor substrate Portion;The deep trench(13)Inclination angle a in side wall and semiconductor substrate through-thickness is between 0~10 degree, deep trench (13)Bottom width is W3;
(4)On the first main surface(001)Deposit the second conductive type epitaxial layer that a layer thickness is W4, W4<1/2×W3;
(5)On the first main surface(001)On perform etching, remove deep trench(13)Second conductive type epitaxial layer of bottom;Protect Stay deep trench(13)The second conductive type epitaxial layer in side wall;
(6)On the first main surface of semiconductor(001)Carry out the first conductive type impurity injection;In deep trench(13)Bottom forms the One conduction type compensating basin;
(7)On the first main surface(001)The first conductive type epitaxial layer is deposited, the first conductive type epitaxial layer fills up deep trench (13);
(8)To the first main surface(001)Planarization process is carried out, removes the first main surface(001)On the first conduction type outside Prolong layer and hard mask layer(11);Deep trench(13)Second conductive type epitaxial layer of side wall forms the second conductive-type of super-junction structure Type post, deep trench(13)First conduction type substrate of sidepiece and the first conductive type epitaxial layer respectively constitute the first conduction type First post and first the second post of conduction type.
2. the manufacture method of extra small unit size longitudinal direction as claimed in claim 1 super-junction semiconductor device, it is characterized in that:It is described hard Mask layer(11)Chemical vapor deposition silica or thermal silicon dioxide is added to add nitridation including LPTEOS, thermal oxide silica Silicon.
3. the manufacture method of extra small unit size longitudinal direction as claimed in claim 1 super-junction semiconductor device, it is characterized in that:It is described hard Mask open(12)Width W1 and adjacent hard mask opening(12)Distance W2 difference is equal.
4. the manufacture method of extra small unit size longitudinal direction as claimed in claim 1 super-junction semiconductor device, it is characterized in that:The system Method is made to be used to manufacture longitudinal superjunction diode, longitudinal superjunction isolated gate FET, longitudinal superjunction IGBT.
CN201710591038.4A 2017-07-19 2017-07-19 The manufacture method of extra small unit size longitudinal direction super-junction semiconductor device CN107342226A (en)

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