CN104576743B - Power MOS (Metal Oxide Semiconductor) device with groove and its manufacture method - Google Patents
Power MOS (Metal Oxide Semiconductor) device with groove and its manufacture method Download PDFInfo
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 35
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 230000001413 cellular effect Effects 0.000 claims abstract description 174
- 239000002184 metal Substances 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims description 74
- 238000005530 etching Methods 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 239000002210 silicon-based material Substances 0.000 claims description 2
- 230000008021 deposition Effects 0.000 abstract description 4
- 238000000407 epitaxy Methods 0.000 description 12
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- 238000000151 deposition Methods 0.000 description 3
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- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- 238000009413 insulation Methods 0.000 description 2
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- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
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- 230000003628 erosive effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a kind of deep-groove power MOS component with superelevation cellular density and its manufacture method, cellular in its cellular region uses groove structure, on the section of power MOS (Metal Oxide Semiconductor) device, the inwall and bottom grown of cellular groove, which have in gate oxide, cellular groove, is deposited with conductive polycrystalline silicon；Thermal oxide layer is set in the notch of cellular groove, deposition has an insulating medium layer on thermal oxide layer, the insulating medium layer and thermal oxide layer only and are distributed in the notch of cellular groove；On the section of the power MOS (Metal Oxide Semiconductor) device, source contact openings are extended down into the second conduction type well layer from the first conduction type source area, source metal, source metal and the first conduction type source area, the second equal Ohmic contact of conduction type well layer are filled with source contact openings.Compact conformation of the present invention, can be greatly lowered MOS device channel resistance, so as to reduce the specific on-resistance of whole device.
Description
Technical field
The present invention relates to a kind of power MOS (Metal Oxide Semiconductor) device and its manufacture method, especially a kind of power MOS (Metal Oxide Semiconductor) device with groove and its system
Method is made, belongs to the technical field of power semiconductor.
Background technology
Power MOS (Metal Oxide Semiconductor) device with groove has the characteristics of integrated level is high, conducting resistance is low, switching speed is fast, switching loss is small, extensively
It is general to be applied to all kinds of power managements and switch conversion.With industrial expansion, global warming causes climatic environment more and more severe,
Various countries start increasingly to pay attention to carbon reduction and sustainable development, therefore for the power consumption and its conversion efficiency of power MOS (Metal Oxide Semiconductor) device
It is required that more and more higher, in the case where applying frequency is not high, power consumption is mainly determined that conduction loss is largely determined by by conduction loss
The influence of specific on-resistance size；Wherein, specific on-resistance is smaller, and conduction loss is smaller.
It is that, by improving cellular density, increase unit area is total effectively wide to reduce one of effective ways of specific on-resistance
Degree, so as to reach the purpose of reduction specific on-resistance.It is that need to reduce adjacent cellular spacing to improve cellular density（pitch）, mesh
The minimum pitch of preceding existing domestic and international volume production at 1.0 μm or so, prior art reduce still further below be limited by photolithographic process capability and
Litho machine aligning accuracy, photolithographic process capability refers mainly to expose the groove line width and contact hole line width of minimum, aligning accuracy
Hole and the aligning accuracy of cellular groove during main finger-hole exposure.Country's batch production technique can expose and can keep pattern after etching at present
Good minimum cellular trench line is wide about 0.25 μm, finally etch and make sacrificial oxide layer and insulation gate oxide after, groove
About 0.4 μm of line width, domestic volume production can expose and can keep about 0.25 μm good of minimum cellular contact hole line width of pattern after etching,
248nmDUV litho machines aligning accuracy is in 60nm or so, to ensure enough process windows, and cellular contact hole is to finally finishing insulation
The spacing of gate oxide cellular groove is at least 0.09 μm, such prior art processes, and the pitch that minimum can reach is about 0.83
μm, it is difficult to further reduction.
Therefore, how to be designed by improving device, overcome technological ability to limit to, to improve cellular density, reduce electric conduction
Important research direction of the resistance as those skilled in the art of the present technique.
The content of the invention
The purpose of the present invention is to overcome the deficiencies in the prior art there is provided a kind of power MOS (Metal Oxide Semiconductor) device with groove and its system
Method is made, its compact conformation, cellular density is only limited by the minimum feature and spacing of cellular groove, technique, source contact openings
Etching uses self-registered technology, without being bound by the aligning accuracy in contact hole line width and hole to cellular groove, and cellular density can be from normal
0.645G single cell structure/inch2 liftings of technique are advised to 2.133G single cell structure/inch2, MOS devices can be greatly lowered
Part channel resistance, so as to reduce the specific on-resistance of whole device.
The technical scheme provided according to the present invention, the power MOS (Metal Oxide Semiconductor) device with groove, in the vertical view of the power MOS (Metal Oxide Semiconductor) device
In plane, including cellular region and terminal protection area on semiconductor substrate, the cellular region is located at semiconductor substrate
Center, terminal protection area is around the encirclement cellular region；On the section of the power MOS (Metal Oxide Semiconductor) device, semiconductor substrate includes
Superposed first conductive type epitaxial layer and the first conductivity type drain area positioned at bottom, first conduction type
Drain region is abutted with the first conductive type epitaxial layer；
In cellular region, the top in the first conductive type epitaxial layer is provided with the second conduction type well layer, cellular region Nei Bao
Include the cellular in some cellulars being arranged in parallel, cellular region and use groove structure, cellular groove is located at the second conduction type well layer,
Depth is stretched into the first conductive type epitaxial layer below the second conduction type well layer, is provided with above the side wall of adjacent cellular groove
First conduction type source area, the first conduction type source area is located at the top in the second conduction type well layer and and cellular
The side wall of groove is in contact；It is characterized in that：
On the section of the power MOS (Metal Oxide Semiconductor) device, the inwall and bottom grown of cellular groove have gate oxide, described
Growth, which has in the cellular groove of gate oxide, is deposited with conductive polycrystalline silicon；In the notch of cellular groove, thermal oxide layer is set, it is described
Conductive polycrystalline silicon below the gate oxide and cellular groove notch of thermal oxide layer covering cellular trenched side-wall, in thermal oxide layer
Upper deposition has an insulating medium layer, and the insulating medium layer and thermal oxide layer only and are distributed in the notch of cellular groove；
On the section of the power MOS (Metal Oxide Semiconductor) device, source contact openings, the source are provided with above the second conduction type well layer
Pole contact hole is extended down into the second conduction type well layer from the first conduction type source area, is filled in source contact openings
There are source metal, the source metal and the first conduction type source area, the second equal Ohmic contact of conduction type well layer, and source electrode
Metal is mutually dielectrically separated from the conductive polycrystalline silicon in cellular groove by insulating medium layer and thermal oxide layer.
First conductive type epitaxial layer is included outside first the first epitaxial layer of conduction type and the first conduction type second
Prolong layer, first the first epitaxial layer of conduction type is located at first the second epitaxial layer of conduction type and the first conductivity type drain is interval,
And first the first epitaxial layer adjacent of conduction type the first conductivity type drain area and first the second epitaxial layer of conduction type；Second leads
Electric type well layer is located at the top in first the second epitaxial layer of conduction type；The depth of cellular groove stretches into the first conduction type
In two epitaxial layers or first the first epitaxial layer of conduction type.
Using the thermal oxide layer and insulating medium layer that are distributed in cellular groove notch as blocking masking layer, using from right
Quasi- etching technics, obtains source contact openings.
A kind of manufacture method of power MOS (Metal Oxide Semiconductor) device with groove, the manufacture method of the power MOS (Metal Oxide Semiconductor) device comprises the following steps：
The semiconductor substrate of a, offer with two opposing main faces, described two opposing main faces include the first interarea and second
Interarea, includes the first conductive type epitaxial layer and the first conductivity type drain area, first between the first interarea and the second interarea
The upper surface of conductive type epitaxial layer forms the first interarea of semiconductor substrate, and the lower surface in the first conductivity type drain area is formed
Second interarea of semiconductor substrate；
B, on the first interarea of above-mentioned semiconductor substrate hard mask layer is deposited, optionally shelter and etch hard mask
Layer, to form the hard mask window of etching groove above the first interarea of semiconductor substrate；
C, utilize above-mentioned hard mask window, the first interarea of etching semiconductor substrate, to obtain institute in semiconductor substrate
The deep trench needed, the deep trench includes cellular groove；
D, grow sacrificial oxide layer on above-mentioned the first interarea for moving substrate to, the sacrificial oxide layer covering is semiconductor-based
First interarea of plate, and it is covered in the side wall and bottom wall of cellular groove；
E, by etching the above-mentioned sacrificial oxide layer being covered in the first interarea and cellular groove is removed, and it is sacrificial removing
Gate oxide is grown on first interarea of domestic animal oxide layer, the gate oxide covers the first interarea of semiconductor substrate, and covers
In the side wall and bottom wall of cellular groove；
F, the deposit Gate Electrode Conductive polysilicon material layer on the first interarea of above-mentioned semiconductor substrate, the Gate Electrode Conductive are more
Crystal silicon material layer is filled on the gate oxide in cellular groove and being covered in above the first interarea；
Gate Electrode Conductive polysilicon material layer above g, the above-mentioned interarea of semiconductor substrate first of removal, to obtain being located at cellular
Conductive polycrystalline silicon in groove；
H, inject the second conductive type impurity ion on the first interarea of above-mentioned semiconductor substrate, and by push away after trap
The second conduction type well layer being located in cellular region is formed in first conductive type epitaxial layer, the bottom land of cellular groove is located at cellular
The lower section of second conduction type well layer in area；
I, on the first interarea of above-mentioned semiconductor substrate, carry out source area photoetching, and inject the first conductive type impurity
Ion, by forming the first conduction type source area in the second conduction type well layer of cellular region after knot；
J, on the first interarea of above-mentioned semiconductor substrate pass through thermal oxide growth thermal oxide layer；
K, insulating medium layer is deposited on the first interarea of above-mentioned semiconductor substrate, the insulating medium layer is covered in hot oxygen
Change on layer；
L, to above-mentioned insulating medium layer carry out contact hole photoetching, with obtain be located at cellular groove on the outside of source contact openings,
The source contact openings are extended down into the second conduction type well layer from the first conduction type source area；
M, inject the second conductive type impurity ion on the first interarea of above-mentioned semiconductor substrate and annealed；
In n, the deposited metal above the first interarea of above-mentioned semiconductor substrate, the metal level filling source contact openings
And cover on the insulating medium layer above cellular groove notch, to form metal connecting line；The metal connecting line includes source metal,
The source metal and the first conduction type source area and the second equal Ohmic contact of conduction type well layer.
The thickness of the thermal oxide layer is the à of 1000 à ~ 5000.
In step l, following steps are specifically included：
L1, the insulating medium layer and thermal oxide layer above the interarea of semiconductor substrate first are performed etching, to remove member
Insulating medium layer and thermal oxide layer outside born of the same parents' groove notch；
L2, the insulating medium layer using cellular groove notch and thermal oxide layer carry out Self-aligned etching, to obtain source electrode
Contact hole.
The hard mask layer is LPTEOS, thermal oxide silica adds chemical vapor deposition silica or thermal silicon dioxide
Plus silicon nitride.
The insulating medium layer is silica glass（USG）, boron-phosphorosilicate glass（BPSG）Or phosphorosilicate glass（PSG）.
The material of the semiconductor substrate includes silicon, and first conductive type epitaxial layer includes the first conduction type first
Epitaxial layer and first the second epitaxial layer of conduction type, first the first epitaxial layer of conduction type are located at first the second extension of conduction type
Layer is interval with the first conductivity type drain, and first the first epitaxial layer adjacent of conduction type the first conductivity type drain area and first
The epitaxial layer of conduction type second；Second conduction type well layer is located at the top in first the second epitaxial layer of conduction type；Cellular ditch
The depth of groove is stretched into first the second epitaxial layer of conduction type or first the first epitaxial layer of conduction type.
It is conductive for N-type metal-oxide-semiconductor field effect transistor, first in both described " first conduction type " and " the second conduction type "
Type refers to N-type, and the second conduction type is p-type；For p-type metal-oxide-semiconductor field effect transistor, the first conduction type and the second conduction type are signified
Type and N-type metal-oxide-semiconductor field effect transistor contrast.
Advantages of the present invention：The top of conductive polycrystalline silicon and the growth of cellular trench sidewall area have thermal oxide in cellular groove
Insulating medium layer is deposited with layer, thermal oxide layer, the thermal oxide layer and insulating medium layer are only covered in the groove of cellular groove
Mouthful, can realize the Self-aligned etching of source contact openings using thermal oxide layer and insulating medium layer, i.e., by cellular groove above
Thermal oxide layer and insulating medium layer realize that cellular groove lateral wall source contact openings autoregistration is generally carved as screen layer is blocked
Erosion.Due to being to use Self-aligned etching technique, therefore the cellular density of cellular region is no longer limited by contact hole line width and contact hole is arrived
The aligning accuracy of cellular groove, is only limited by the minimum feature and spacing of cellular groove, can be from 1.0 μm of pitch of common process
2.133G single cell structure of 0.645G single cell structure of cellular density/inch2 liftings to 0.55 μm of pitch cellular density/
Inch2, cellular density improves about 220%, MOS device channel resistance can be greatly lowered, so that the feature for reducing whole device is led
Be powered resistance.
Brief description of the drawings
Fig. 1 is structure sectional view of the invention.
Fig. 2 ~ Figure 15 is specific implementation process step sectional view of the invention, wherein
Fig. 2 is the sectional view of semiconductor substrate of the present invention.
Fig. 3 obtains the sectional view of hard mask window for the present invention.
Fig. 4 obtains the sectional view after cellular groove for the present invention.
Fig. 5 obtains the sectional view after sacrificial oxide layer for the present invention.
Fig. 6 obtains the sectional view after gate oxide for the present invention.
Fig. 7 obtains the sectional view after Gate Electrode Conductive polysilicon material layer for the present invention.
Fig. 8 obtains the sectional view after conductive polycrystalline silicon for the present invention.
Fig. 9 is the sectional view after p-type well layer of the present invention.
Figure 10 obtains the sectional view after N-type source region for the present invention.
Figure 11 obtains the sectional view after thermal oxide layer for the present invention.
Figure 12 obtains the sectional view after insulating medium layer for the present invention.
Figure 13 is the sectional view after the present invention is performed etching to insulating medium layer and thermal oxide layer.
Figure 14 obtains the sectional view after source contact openings for the present invention.
Figure 15 obtains the sectional view after source metal for the present invention.
Description of reference numerals：1-N types drain region, the epitaxial layer of 2-N types first, the epitaxial layer of 3-N types second, 4-P types well layer, 5-
Source metal, 6- cellulars groove, 7-N types source area, 8- source contact openings, 9- insulating medium layers, 10- thermal oxide layers, 11- grid oxygens
Change layer, 12- conductive polycrystalline silicons, the interareas of 13- first, the interareas of 14- second, 15- hard mask layers, the hard mask windows of 16-, 17- to sacrifice
Oxide layer and 18- notches.
Embodiment
With reference to specific drawings and examples, the invention will be further described.
As shown in Fig. 1 and Figure 15：In order to which MOS device channel resistance can be greatly lowered, so as to reduce the spy of whole device
Conducting resistance is levied, it is of the invention in the top plan view of the power MOS (Metal Oxide Semiconductor) device by taking N-type power MOS (Metal Oxide Semiconductor) device as an example, including positioned at
Cellular region and terminal protection area on semiconductor substrate, the cellular region are located at the center of semiconductor substrate, terminal protection
Area is around the encirclement cellular region；On the section of the power MOS (Metal Oxide Semiconductor) device, semiconductor substrate is included outside superposed N-type
Prolong layer and the N-type drain electrode 1 positioned at bottom, the N-type drain electrode 1 is abutted with N-type epitaxy layer；
In cellular region, the top in N-type epitaxy layer, which is provided with p-type well layer 4, cellular region, includes some members being arranged in parallel
Cellular in born of the same parents, cellular region uses groove structure, and cellular groove 6 is located at p-type well layer 4, and depth stretches into the N-type of the lower section of p-type well layer 4
In epitaxial layer, N-type source region 7 is provided with above the side wall of adjacent cellular groove 6, the N-type source region 7 is located in p-type well layer 4
Top and it is in contact with the side wall of cellular groove 6；
On the section of the power MOS (Metal Oxide Semiconductor) device, the inwall and bottom grown of cellular groove 6 have gate oxide 11,
The growth, which has, is deposited with conductive polycrystalline silicon 12 in the cellular groove 6 of gate oxide 11；In the notch 18 of cellular groove 6, heat is set
Below oxide layer 10, the gate oxide 11 and cellular groove notch 18 of the side wall of the covering cellular of thermal oxide layer 10 groove 6
Conductive polycrystalline silicon 12, deposition has insulating medium layer 9 on thermal oxide layer 10, and the insulating medium layer 9 and thermal oxide layer 10 are only
And it is distributed in the notch 18 of cellular groove 6；
On the section of the power MOS (Metal Oxide Semiconductor) device, source contact openings 8, the source contact are provided with the top of p-type well layer 4
Hole 8 is extended down into p-type well layer 4 from N-type source region 7, and source metal 5, the source electrode are filled with source contact openings 8
Conductive polycrystalline silicon 12 in metal 5 and N-type source region 7, the equal Ohmic contact of p-type well layer 4, and source metal 5 and cellular groove 6 leads to
Cross insulating medium layer 9 and thermal oxide layer 10 is mutually dielectrically separated from.
Specifically, the terminal protection area of correspondence power MOS (Metal Oxide Semiconductor) device can be not limited to any form, the shape in N-type epitaxy layer
Into after p-type well layer 4, on the section of cellular region, p-well layer 4 is located at the top of N-type epitaxy layer, and the bottom land of cellular groove 6 is located at P
The lower section of well layer 4, N-type source region 7 is located in the top of the adjacent side wall of cellular groove 6, and N-type source region 7 and cellular groove 6
Conductive polycrystalline silicon 12 overlaps mutually.
In the embodiment of the present invention, thermal oxide layer 10 and insulating medium layer 9 only and are distributed in the notch position of cellular groove 6
Put, the gate oxide 11 corresponding with 6 inner tank mouths of cellular groove, 18 positions of thermal oxide layer 10 and leading positioned at the position of notch 18
Electric polysilicon 12 is in contact, and insulating medium layer 9 is covered on thermal oxide layer 10, passes through insulating medium layer 9 and thermal oxide layer 10
It as screen layer is blocked, can realize that the autoregistration of the lateral wall source contact openings 8 of cellular groove 6 is generally etched, to cause cellular
The cellular density in area is no longer limited by contact hole line width and source contact openings to the aligning accuracy of cellular groove 6, i.e., with distribution
In the thermal oxide layer 10 in cellular groove notch 18 and insulating medium layer 9 as masking layer is blocked, using Self-aligned etching work
Skill, obtains source contact openings 8, so as to which MOS device channel resistance is greatly reduced, and reduces the feature conducting of whole MOS device
Resistance.
Source contact openings 8 are through N-type source region 7 and enter in p-type well layer 4, and source contact openings 8 are in p-type well layer 4
Depth is not more than the depth of p-type well layer 4, after source contact openings 8 run through N-type source region 7, obtains on the lateral wall of cellular groove 6
N-type source region 7, source metal 5 contacts with N-type source region 7 and p-type well layer 4, and source metal 5 and N-type source region 7
With the equal Ohmic contact of p-type well layer 4, the source electrode of power MOS (Metal Oxide Semiconductor) device can be obtained by source metal 5, due to insulating medium layer 9 with
And thermal oxide layer 10 is distributed in the notch 18 of cellular groove 6, therefore, the conductive polycrystalline silicon 12 in cellular groove 6 is by exhausted
Edge dielectric layer 9 and thermal oxide layer 10 are isolated with the mutually insulated of source metal 5, and the gate electrode for not interfering with whole MOS device draws
Go out.
Further, the N-type epitaxy layer includes the first epitaxial layer of N-type 2 and the second epitaxial layer of N-type 3, the extension of N-type first
Layer 2 is located between the second epitaxial layer of N-type 3 and N-type drain electrode 1, and outside the adjoining N-type drain electrode 1 of the first epitaxial layer of N-type 2 and N-type second
Prolong layer 3；P-type well layer 4 is located at the top in the second epitaxial layer of N-type 3；The depth of cellular groove 6 stretches into the second epitaxial layer of N-type 3 or N
In the first epitaxial layer of type 2.The depth of cellular groove 6 is not more than the thickness of N-type epitaxy layer, the i.e. bottom land of cellular groove 6 positioned at N
The top of type drain region 1.
It is above-mentioned that there is superelevation cellular density deep-groove power MOS component as shown in Fig. 2 ~ Figure 15, following techniques can be passed through
Step is prepared, and specific steps include：
A, provide the semiconductor substrate with two opposing main faces, described two opposing main faces include the first interarea 13 and the
Two interareas 14, between the first interarea and 13 second interareas 14 include N-type epitaxy layer and N-type drain electrode 1, N-type epitaxy layer it is upper
Surface forms the first interarea 13 of semiconductor substrate, the second interarea 14 of the lower surface formation semiconductor substrate of N-type drain electrode 1；
As shown in Fig. 2 the material of semiconductor substrate includes silicon, N-type epitaxy layer includes the first epitaxial layer of N-type 2 and N-type the
Two epitaxial layers 3, the doping concentration of N-type drain electrode 1 is more than the doping concentration of the first epitaxial layer of N-type 2, and the first epitaxial layer of N-type 2 is mixed
Miscellaneous concentration is more than the doping concentration of the second epitaxial layer of N-type 3, and in the specific implementation, N-type epitaxy layer can also only include N-type first
Epitaxial layer 2 or the second epitaxial layer of N-type 3, can specifically be selected, here is omitted as needed.
B, the deposit hard mask layer 15 on the first interarea 13 of above-mentioned semiconductor substrate, optionally shelter and etch and cover firmly
Film layer 15, forms the hard mask window 16 of etching groove with the top of the first interarea 13 in semiconductor substrate；
As shown in figure 3, the hard mask layer 15 is LPTEOS, thermal oxide silica adds chemical vapor deposition silica
Or thermal silicon dioxide adds silicon nitride.The hard insertion hard mask layer 15 of mask window 16, sets on the first interarea 13 of semiconductor substrate
It is no longer to go to live in the household of one's in-laws on getting married herein known to those skilled in the art to put hard mask layer 15 and obtain the technical process of hard mask window 16
State.
C, utilize above-mentioned hard mask window 16, the first interarea 13 of etching semiconductor substrate, with semiconductor substrate
To required deep trench, the deep trench includes cellular groove 6；
As shown in figure 4, because the position of hard mask window 16 can carry out selection setting as needed, then have hard mask windows
The position of mouth 16 is exposed by semiconductor substrate the first interarea 13 of bottom, by dry etching semiconductor substrate, so that hard having
The position of mask window 16 obtains deep trench, because cellular region uses groove structure in the present invention, therefore, and deep trench includes cellular
Groove 6, cellular groove 6 is extended downwardly from the first interarea 13, and the depth of cellular groove 6 is not more than the thickness of N-type epitaxy layer.
D, the growth sacrificial oxide layer 17 on above-mentioned the first interarea 14 for moving substrate to, the covering of sacrificial oxide layer 17 half
First interarea 13 of conductor substrate, and it is covered in the side wall and bottom wall of cellular groove 6；
As shown in figure 5, the carbon dioxide layer of sacrificial oxide layer 17, sacrificial oxide layer 17 can be obtained by thermal oxide growth.
E, by etching the above-mentioned sacrificial oxide layer 17 being covered in the first interarea 13 and cellular groove 6 is removed, and
Remove and gate oxide 11 is grown on the first interarea 13 of sacrificial oxide layer 17, the of the gate oxide 11 covering semiconductor substrate
One interarea 13, and it is covered in the side wall and bottom wall of cellular groove 6；
As shown in fig. 6, can be removed in the first interarea of semiconductor substrate 13 and cellular groove 6 by sacrificial oxide layer 17
Impurity, improve the cleannes in semiconductor substrate the first interarea 13 and cellular groove 6, removing sacrificial oxide layer 17 can adopt
With existing conventional etching technics, specifically repeat no more.After sacrificial oxide layer 17 is removed, thermal oxide growth obtains grid oxygen again
Change layer 11.
F, deposit Gate Electrode Conductive polysilicon material layer, the Gate Electrode Conductive on the first interarea 13 of above-mentioned semiconductor substrate
Polysilicon material layer is filled in cellular groove 6 and is covered on the gate oxide 11 of the top of the first interarea 13；
As shown in fig. 7, being used to form conductive polycrystalline silicon by Gate Electrode Conductive polysilicon material layer.
G, the Gate Electrode Conductive polysilicon material layer for removing the above-mentioned top of the first interarea of semiconductor substrate 13, to obtain being located at member
Conductive polycrystalline silicon 12 in born of the same parents' groove 6；
As shown in figure 8, removing the Gate Electrode Conductive polysilicon material layer of the top of the first interarea of semiconductor substrate 13, it is located at
Conductive polycrystalline silicon 12 in conductive polycrystalline silicon 12 in cellular groove 6, cellular groove 6 is less than the height of cellular groove 6, with member
The notch of born of the same parents' groove 6 has one section of vacant height.Remove the specific work of Gate Electrode Conductive polysilicon material layer on the first interarea 13
Skill is that here is omitted known to those skilled in the art.
H, the implanting p-type foreign ion on the first interarea 13 of above-mentioned semiconductor substrate, and by pushing away after trap in N-type extension
The p-type well layer 4 being located in cellular region is formed in layer, the bottom land of cellular groove 6 is located at the lower section of p-type well layer 4 in cellular region；
As shown in figure 9, in the top implanting p-type foreign ion of the first interarea 13 of semiconductor substrate, so that the shape after trap is pushed away
Into p-type well layer 4, implanting p-type concentration impurity ion and the process for pushing away trap are known to those skilled in the art, no longer to go to live in the household of one's in-laws on getting married herein
State, depth of the p-type well layer 4 in N-type epitaxy layer is less than the depth of cellular groove 6, the i.e. bottom land of cellular groove 6 and is located at p-type trap
The lower section of layer 4.
I, on the first interarea 13 of above-mentioned semiconductor substrate, carry out source area photoetching, and inject N-type impurity ion, lead to
Cross and form N-type source region 7 after knot in the p-type well layer 4 of cellular region；
As shown in Figure 10, after p-well layer 4 is formed, by injecting N-type impurity ion and source area photoetching, so that in p-type
N-type source region 7 is formed in well layer 4, the mistake of source area photoetching and injection N-type impurity ion knot formation N-type source region 7 is carried out
Journey is the technological means that the art is commonly used, and is that known to those skilled in the art, here is omitted.
J, on the first interarea 13 of above-mentioned semiconductor substrate pass through thermal oxide growth thermal oxide layer 10；
As shown in figure 11, thermal oxide layer 10 is silicon dioxide layer, and the thickness of the thermal oxide layer 10 is the à of 1000 à ~ 5000.
Because gate oxide 11 and thermal oxide layer 10 are silicon dioxide layer, therefore, the silicon dioxide layer on the first interarea 13, equal shape
Into the thermal oxide layer 10 of silicon dioxide layer.
K, the deposition insulating medium layer 9 on the first interarea 13 of above-mentioned semiconductor substrate, the insulating medium layer 9 are covered in
On thermal oxide layer 10；
As shown in figure 12, the insulating medium layer 9 is silica glass（USG）, boron-phosphorosilicate glass（BPSG）Or phosphorosilicate glass
（PSG）.
L, contact hole photoetching is carried out to above-mentioned insulating medium layer 9, to obtain the source contact openings for being located at the outside of cellular groove 6
8, the source contact openings 8 are extended down into p-type well layer 4 from N-type source region 7；
As shown in Figure 13 and Figure 14, in step l, following steps are specifically included：
L1, insulating medium layer 9 and thermal oxide layer 10 to the top of the first interarea of semiconductor substrate 13 are performed etching, to go
Insulating medium layer 9 and thermal oxide layer 10 in addition to cellular groove notch 18；
In the embodiment of the present invention, insulating medium layer 9 and thermal oxide layer 10 are performed etching, until by the first interarea 13
Insulating medium layer 9 and thermal oxide layer 10 etch totally, that is, retain insulating medium layer 9 and thermal oxide layer in notch 18
10, the technique performed etching to insulating medium layer 9 and thermal oxide layer 10 is known to those skilled in the art, no longer to go to live in the household of one's in-laws on getting married herein
State, the result after etching is as shown in figure 13.
L2, the insulating medium layer 9 using cellular groove notch and thermal oxide layer 10 carry out Self-aligned etching, to obtain source
Pole contact hole 8.
By the use of insulating medium layer 9 and thermal oxide layer 10 as screen layer is blocked, silicon etching is carried out to semiconductor substrate,
After generally being etched using the autoregistration of contact hole, source contact openings 8 can be obtained, source contact openings 8 run through N-type source region 7, so that
Also the N-type source region 7 being in contact above the side wall of cellular groove 6 and with the lateral wall of cellular groove 6 can be obtained, as shown in figure 14.
M, implanting p-type foreign ion and annealed on the first interarea 13 of above-mentioned semiconductor substrate；
In the embodiment of the present invention, the concentration of implanting p-type foreign ion does not interfere with N-type source region 7, implanting p-type impurity from
Son and the processing step annealed, can improve the reliable of source metal 5 and N-type source region 7 and the Ohmic contact of p-type well layer 4
Property.The p type impurity ion is usually BF2（Boron difluoride）Or B（Boron）, Implantation Energy is generally in 20kev ~ 80kev, injection
Dosage is generally between 1e13 ~ 1e15, and annealing temperature is generally at 700 DEG C ~ 900 DEG C or so.
N, the top deposited metal of the first interarea 13 in above-mentioned semiconductor substrate, the metal level fill source contact openings
On 8 insulating medium layers 9 that are interior and covering the top of cellular groove notch 18, to form metal connecting line；The metal connecting line includes source
Pole metal 5, the source metal 5 and N-type source region 7 and the equal Ohmic contact of p-type well layer 4.
As shown in figure 15, the metal level of deposit can be commonly used using the art material and technique, in the gold of formation
Category line can form the electrode of power MOS (Metal Oxide Semiconductor) device, that is, include the source metal 5 of the present invention, source can be formed by source metal 5
Electrode.
The top of conductive polycrystalline silicon 12 and the growth of the sidewall areas of cellular groove 6 have thermal oxide layer in cellular groove 6 of the present invention
10, insulating medium layer 9 is deposited with thermal oxide layer 10, and the thermal oxide layer 10 and insulating medium layer 9 are only covered in cellular ditch
The notch 18 of groove 6, can realize the Self-aligned etching of source contact openings 8, i.e., by member using thermal oxide layer 10 and insulating medium layer 9
The thermal oxide layer 10 and insulating medium layer 9 of the top of born of the same parents' groove 6 realize that the lateral wall source electrode of cellular groove 6 connects as screen layer is blocked
Contact hole autoregistration is generally etched.Due to being to use Self-aligned etching technique, therefore the cellular density of cellular region is no longer limited by contact
Hole line width and contact hole are only limited by the minimum feature and spacing of cellular groove 6 to the aligning accuracy of cellular groove 6, can be from normal
Advise the 0.645G single cell structure/inch2 liftings to 0.55 μm of pitch cellular density of 1.0 μm of pitch cellular density of technique
2.133G single cell structure/inch2, cellular density improve about 220%, MOS device channel resistance can be greatly lowered so that
Reduce the specific on-resistance of whole device.
Claims (6)
1. a kind of power MOS (Metal Oxide Semiconductor) device with groove, in the top plan view of the power MOS (Metal Oxide Semiconductor) device, including on semiconductor substrate
Cellular region and terminal protection area, the cellular region be located at semiconductor substrate center, terminal protection area around surround institute
State cellular region；On the section of the power MOS (Metal Oxide Semiconductor) device, semiconductor substrate includes superposed first conductive type epitaxial layer
And the first conductivity type drain area positioned at bottom, the first conductivity type drain area and the first conductive type epitaxial layer neighbour
Connect；
In cellular region, the top in the first conductive type epitaxial layer is provided with the second conduction type well layer, if including in cellular region
Cellular in the dry cellular being arranged in parallel, cellular region uses groove structure, and cellular groove is located at the second conduction type well layer, depth
Stretch into the first conductive type epitaxial layer below the second conduction type well layer, first is provided with above the side wall of adjacent cellular groove
Conduction type source area, the first conduction type source area be located at the second conduction type well layer in top and with cellular groove
Side wall be in contact；It is characterized in that：
On the section of the power MOS (Metal Oxide Semiconductor) device, the inwall and bottom grown of cellular groove have gate oxide, in the growth
Have in the cellular groove of gate oxide and be deposited with conductive polycrystalline silicon；In the notch of cellular groove, thermal oxide layer, the hot oxygen are set
Change the conductive polycrystalline silicon below the gate oxide and cellular groove notch of layer covering cellular trenched side-wall, sunk on thermal oxide layer
Product has an insulating medium layer, and the insulating medium layer and thermal oxide layer only and are distributed in the notch of cellular groove；
On the section of the power MOS (Metal Oxide Semiconductor) device, source contact openings are provided with above the second conduction type well layer, the source electrode connects
Contact hole is extended down into the second conduction type well layer from the first conduction type source area, fills active in source contact openings
Pole metal, the source metal and the first conduction type source area, the second equal Ohmic contact of conduction type well layer, and source metal
Mutually it is dielectrically separated from by insulating medium layer and thermal oxide layer with the conductive polycrystalline silicon in cellular groove；
First conductive type epitaxial layer includes first the first epitaxial layer of conduction type and first the second epitaxial layer of conduction type,
First the first epitaxial layer of conduction type is located at first the second epitaxial layer of conduction type and the first conductivity type drain is interval, and first
The first epitaxial layer adjacent of conduction type the first conductivity type drain area and first the second epitaxial layer of conduction type；Second conduction type
Well layer is located at the top in first the second epitaxial layer of conduction type；The depth of cellular groove stretches into first the second extension of conduction type
In layer or first the first epitaxial layer of conduction type；
Thermal oxide layer and insulating medium layer to be distributed in cellular groove notch are carved as masking layer is blocked using autoregistration
Etching technique, obtains source contact openings.
2. a kind of manufacture method of power MOS (Metal Oxide Semiconductor) device with groove, it is characterized in that, the manufacture method of the power MOS (Metal Oxide Semiconductor) device is included such as
Lower step：
（a）, the semiconductor substrate with two opposing main faces is provided, described two opposing main faces include the first interarea to be led with second
Face, includes the first conductive type epitaxial layer and the first conductivity type drain area, first leads between the first interarea and the second interarea
The upper surface of electric type epitaxial layer forms the first interarea of semiconductor substrate, the lower surface formation half in the first conductivity type drain area
Second interarea of conductor substrate；
（b）, on the first interarea of above-mentioned semiconductor substrate deposit hard mask layer, optionally shelter and etch hard mask layer,
To form the hard mask window of etching groove above the first interarea of semiconductor substrate；
（c）, utilize above-mentioned hard mask window, the first interarea of etching semiconductor substrate, with needed for being obtained in semiconductor substrate
Deep trench, the deep trench include cellular groove；
（d）, grow sacrificial oxide layer on the first interarea of above-mentioned semiconductor substrate, the sacrificial oxide layer covering is semiconductor-based
First interarea of plate, and it is covered in the side wall and bottom wall of cellular groove；
（e）, by etching remove the above-mentioned sacrificial oxide layer being covered in the first interarea and cellular groove, and sacrificed removing
Gate oxide is grown on first interarea of oxide layer, the gate oxide covers the first interarea of semiconductor substrate, and is covered in
The side wall and bottom wall of cellular groove；
（f）, on the first interarea of above-mentioned semiconductor substrate deposit Gate Electrode Conductive polysilicon material layer, the Gate Electrode Conductive polycrystalline
Silicon material layer is filled on the gate oxide in cellular groove and being covered in above the first interarea；
（g）, Gate Electrode Conductive polysilicon material layer above the above-mentioned interarea of semiconductor substrate first is removed, to obtain being located at cellular ditch
Conductive polycrystalline silicon in groove；
（h）, the second conductive type impurity ion is injected on the first interarea of above-mentioned semiconductor substrate, and by pushing away after trap
The second conduction type well layer being located in cellular region is formed in one conductive type epitaxial layer, the bottom land of cellular groove is located at cellular region
The lower section of interior second conduction type well layer；
（i）, on the first interarea of above-mentioned semiconductor substrate, carry out source area photoetching, and inject the first conductive type impurity from
Son, by forming the first conduction type source area in the second conduction type well layer of cellular region after knot；
（j）, on the first interarea of above-mentioned semiconductor substrate pass through thermal oxide growth thermal oxide layer；
（k）, insulating medium layer is deposited on the first interarea of above-mentioned semiconductor substrate, the insulating medium layer is covered in thermal oxide
On layer；
（l）, to above-mentioned insulating medium layer carry out contact hole photoetching, with obtain be located at cellular groove on the outside of source contact openings, institute
Source contact openings are stated to extend down into the second conduction type well layer from the first conduction type source area；
In step（l）In, specifically include following steps：
（l1）, the insulating medium layer and thermal oxide layer above the interarea of semiconductor substrate first are performed etching, to remove cellular
Insulating medium layer and thermal oxide layer outside groove notch；
（l2）, insulating medium layer using cellular groove notch and thermal oxide layer carry out Self-aligned etching, connect with obtaining source electrode
Contact hole；
（m）, inject the second conductive type impurity ion on the first interarea of above-mentioned semiconductor substrate and annealed；
（n）, above the first interarea of above-mentioned semiconductor substrate in deposited metal, metal level filling source contact openings simultaneously
Cover on the insulating medium layer above cellular groove notch, to form metal connecting line；The metal connecting line includes source metal, institute
State source metal and the first conduction type source area and the second equal Ohmic contact of conduction type well layer.
3. the manufacture method of power MOS (Metal Oxide Semiconductor) device with groove according to claim 2, it is characterized in that：The thickness of the thermal oxide layer
For the à of 1000 à ~ 5000.
4. the manufacture method of power MOS (Metal Oxide Semiconductor) device with groove according to claim 2, it is characterized in that：The hard mask layer is
LPTEOS, thermal oxide silica add chemical vapor deposition silica or thermal silicon dioxide plus silicon nitride.
5. the manufacture method of power MOS (Metal Oxide Semiconductor) device with groove according to claim 2, it is characterized in that：The insulating medium layer is silicon
Glass（USG）, boron-phosphorosilicate glass（BPSG）Or phosphorosilicate glass（PSG）.
6. the manufacture method of power MOS (Metal Oxide Semiconductor) device with groove according to claim 2, it is characterized in that：The material of the semiconductor substrate
Material includes silicon, and first conductive type epitaxial layer is included outside first the first epitaxial layer of conduction type and the first conduction type second
Prolong layer, first the first epitaxial layer of conduction type is located at first the second epitaxial layer of conduction type and the first conductivity type drain is interval,
And first the first epitaxial layer adjacent of conduction type the first conductivity type drain area and first the second epitaxial layer of conduction type；Second leads
Electric type well layer is located at the top in first the second epitaxial layer of conduction type；The depth of cellular groove stretches into the first conduction type
In two epitaxial layers or first the first epitaxial layer of conduction type.
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| CN106653836B (en) * | 2016-12-01 | 2023-09-01 | 无锡新洁能股份有限公司 | Insulated gate bipolar transistor device with low on-voltage drop and method of manufacturing the same |
| CN107578992A (en) * | 2017-07-17 | 2018-01-12 | 中航（重庆）微电子有限公司 | The high-density, trench type device architecture in self-aligned source contacts hole and preparation method thereof |
| CN107204372B (en) * | 2017-07-19 | 2023-06-06 | 无锡新洁能股份有限公司 | Trench type semiconductor device with optimized terminal structure and manufacturing method |
| CN108172563B (en) * | 2017-12-14 | 2019-09-03 | 华润微电子（重庆）有限公司 | A kind of ditch flute profile device and its manufacturing method with self-aligned contact hole |
| CN107994069B (en) * | 2017-12-29 | 2024-03-15 | 安徽赛腾微电子有限公司 | IGBT device and manufacturing method thereof |
| CN108649072B (en) * | 2018-02-09 | 2024-02-02 | 江苏捷捷微电子股份有限公司 | Low-on-resistance trench MOSFET device and manufacturing method thereof |
| CN109003938A (en) * | 2018-07-26 | 2018-12-14 | 长鑫存储技术有限公司 | Semiconductor contact structure, memory structure and preparation method thereof |
| CN112133750B (en) * | 2019-06-25 | 2024-02-13 | 华润微电子（重庆）有限公司 | Deep trench power device and preparation method thereof |
| CN110416211A (en) * | 2019-07-24 | 2019-11-05 | 上海朕芯微电子科技有限公司 | A kind of super-self-aligned power Trench MOSFET production method and structure |
| CN112117331A (en) * | 2020-10-16 | 2020-12-22 | 华羿微电子股份有限公司 | Trench VDMOS device and preparation method |
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