CN208189598U - A kind of rectifier diode chip - Google Patents
A kind of rectifier diode chip Download PDFInfo
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- CN208189598U CN208189598U CN201820743538.5U CN201820743538U CN208189598U CN 208189598 U CN208189598 U CN 208189598U CN 201820743538 U CN201820743538 U CN 201820743538U CN 208189598 U CN208189598 U CN 208189598U
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Abstract
The utility model discloses a kind of rectifier diode chips, including growing base area N, and the P layer and P on the growing base area upper layer N is arranged in+Layer, is arranged in the N of growing base area N lower layer+Layer；It is additionally provided with voltage slot, the voltage slot is from P+Layer extends downwardly into the N of growing base area；The surrounding of the diode chip for backlight unit is provided with N+End wall, the N+End wall from N+Layer extends upwardly to the bottom of voltage slot.The utility model passes through setting N+The structure of layer cut-off wall, can effectively improve the usable floor area of chip, reduce the loss of raw material, reduce production cost, at the same time it can also improve the electrical parameter of chip, and then improve the overall performance of chip.It can be widely applied to semiconductor power device technology field.
Description
Technical field
The utility model relates to semiconductor power device technology fields, and in particular to a kind of rectifier diode chip.
Background technique
Rectifier diode is widely used in power electronic devices, and market demand is huge.The rectification core used inside it
Piece primary structure is PNN+Junction structure, in PNN+As voltage constantly increases in knot, space-charge region broadens in N-type base area to be reached
To N+After layer, due to N+Layer concentration is high, and the broadening of space-charge region becomes smaller, and interface electric field strength at this moment continues to increase, to be achieved
When snowslide electric field strength, reverse current is just sharply increased, and the pressure resistance of the shorter PN junction in base area original in this way is just than no N+Mention
Gao Liao.N+Presence improve the electric field strength in the area N, improve backward voltage, be thinned N-type base area thickness, reduce logical
State pressure drop.In voltage 1500V-3000V or so, its knot terminal framework generally uses table top digging groove technique (see Fig. 1).
Table top digging groove technological advantage between the two, advantage 1: is suitble to automated production between angle lap and planar technology；It is excellent
Point 2: photoetching process is not necessarily to the higher equipment of precision, at low cost.But in order to bear higher voltage (1500V-3000V), in P
Digging groove can occupy the area of about 15-20% in type level.
The main shortcoming of this traditional design is: trench bottom surfaces layer is base area, and doping concentration is low.Electric field is in trench bottom
Distance is broadened than there is N N+The broadening of layer is much bigger.Such as in the width holding of trench bottom and base area commensurateiy wide, then tying
When the maximum field intensity in area is lower than breakdown field strength, which has opened up full.Such as space-charge region and electric field
Intensity continues to increase, it is possible to and section contact coarse after scribing, section are contacted with metal layer electrode again, lead to big loading gage
Stream enters space-charge region, increased dramatically electric current, causes early break-through and soft breakdown.Again since the trench bottom is in space electricity
At lotus area sensitivity, when scribing caused by small chipping, Crack Damage can all cause the increase of leakage current.So generally requiring
The width of voltage slot bottom about 3 times of metric space wider than base area has also resulted in the diminution of chip P level product in the hope of insurance, increases
Big pressure drop, causes power loss big.
Utility model content
The purpose of the utility model is to provide a kind of rectifier diode chips, solve the voltage of existing rectifier diode chip
Slot occupies P level product greatly, causes pressure drop big, the big problem of power loss.
To solve this technical problem, the technical solution adopted in the utility model is: a kind of rectifier diode chip, including length
The P layer and P on the growing base area upper layer N is arranged in base area N+Layer, is arranged in the N of growing base area N lower layer+Layer；It is additionally provided with voltage slot, it is described
Voltage slot is from P+Layer extends downwardly into the N of growing base area；The surrounding of the diode chip for backlight unit is provided with N+End wall, the N+Cut-off
Wall is from N+Layer extends upwardly to the bottom of voltage slot.
To guarantee space-charge region broadening to N+Layer before not with N+End wall contact, the N+End the inside of wall to electric
The vertical range of indent side is not less than the width of growing base area N.
To prevent the chipping generated in scribing, crackle equivalent damage from leakage current being caused to increase, C-V characteristic softens, so N+
The width for ending wall is not less than 80um.
In order to realize in trench bottom and N+Interlayer forms N+End wall, the N+The bottom of layer is provided with a circle blind hole, blind hole
Positioned at N+End the lower section of wall.
Preferably, the blind hole is laser hole or etched hole.
As formation N+End another technological means of wall, the N+The bottom of layer is provided with a circle groove, and groove is located at
N+End the lower section of wall.
Further, the groove is located at N+Layer is internal or is located at N+In the side edge of layer, it is located at N+In the side edge of layer
Groove, that is, adjacent two chip shares a groove, and the side edge after scribing in one single chip forms unilateral slot structure.
The utility model has the beneficial effects that passing through setting N+The structure of layer cut-off wall, it is suppressed that space-charge region is in voltage
The broadening in the area slot bottom N can effectively improve P layers of chip of usable floor area, reduce the loss of raw material, reduce production cost,
At the same time it can also improve the electrical parameter of chip, and then improve the overall performance of chip.
※ the utility model preferably the first laser boring method is implemented.
Below with reference to drawings and examples, the utility model is described in detail.
Detailed description of the invention
Fig. 1 is the cross-sectional view of existing chip structure.
Fig. 2 is the cross-sectional view one of the utility model.
Fig. 3 is the bottom view one of the utility model.
Fig. 4 is the cross-sectional view two of the utility model.
Fig. 5 is the bottom view two of the utility model.
Fig. 6 is the cross-sectional view three of the utility model.
Fig. 7 is the bottom view three of the multiple chips of the utility model.
Specific embodiment
Embodiment 1:
A kind of rectifier diode chip, as shown in Figure 2 and Figure 3, including growing base area N1, the P layer on the growing base area upper layer N1 is set
2 and P+Layer 3, is arranged in the N of growing base area N1 lower layer+Layer 4 and is covered on N+4 and P of layer+The metalization layer 7 on 3 surface of layer.It also sets up
There is a voltage slot 5, the voltage slot 5 is from P+Layer 3 extends downwardly into the N1 of growing base area, is provided with glassivation on the voltage slot 5
Layer 6.The surrounding of the diode chip for backlight unit is provided with N+End wall 8, the N+End wall from N+Layer extends upwardly to voltage slot 5
Bottom, the N+End wall 8 and N+Layer 4 is linked together.
The N of heavy doping high concentration is equipped at 5 bottom of voltage slot+Layer is used as N+End wall 8, so that it may so that space-charge region is at this
Region broadening is suppressed, and is played buffer layer barrier effect, is allow space-charge region and electric field strength to continue to increase, work as electric field
When intensity reaches avalanche breakdown intensity, electric current just starts to steeply rise, and reaches avalanche voltage.Again due to heavily doped N+End wall with
N+Layer is communicated, is not broadened in range effectively in space charge sensitizing range, then has small chipping, crackle that will not lead to big loading gage
Stream enters space-charge region and electric current is caused to increased dramatically, and causes " break-through " and soft breakdown, reduces voltage, so N+End wall
8 width is not less than 80um.The N+The inside for ending wall is not less than the width of growing base area N to the vertical range W of voltage slot side
Spend a, so that it may guarantee that electric field strength reaches maximum value.
Due to after grooving voltage trench bottom away from N+There are also a distances for layer, in order in voltage trench bottom and N+Between layer
Form N+End wall, it is therefore desirable in N+The one circle blind hole 9 of bottom setting of layer, the blind hole 9 are located at N+The lower section for ending wall 8, can
It is formed in the method using laser boring or etching.Pass through the bottom of blind hole and periphery and N+Level expands heavily doped N-type impurity simultaneously
Form N+End wall.
N is carried out with silicon wafer large area using after laser boring+The synchronous diffusion of layer, utilizes N+Impurity lateral, Zong Xiangxiang in silicon
The characteristics of counterdiffusion, is formed with the N of laser bore region+Layer diffusion junction depth is higher than large area N+The junction depth of layer diffusion zone is formed high
Low difference, this difference are then the depth of laser hole.Section forms one of N after etching groove, scribing+Divider wall, this road wall play
The broadening for stopping space charge, reduces carrier and enters depletion layer (also referred to as space-charge region) and improve electric field strength, improves
Voltage.
By taking the chip pressure resistance 2000V of 10mmx10mm as an example, the depth of laser hole makes the knot at this plus the junction depth of diffusion
Large-area planar N can be exceeded deeply+90-110 μm of layer.The N of large area+The junction depth of layer is 70-80 μm, so the thickness of cut-off wall
It can reach 160-190 μm.N+The width for ending wall is controlled at 50-100 μm；N+End the inside of wall to the vertical of voltage slot side
Distance is 100-200 μm.
Using traditional structure, for the electrical characteristics for reaching chip, the width of voltage slot needs to reach 0.65mm, effectively uses
The side length in region is 10mm-0.65mmx2=8.7mm；Therefore effectively usable floor area is 8.7mmx8.7mm=75.69mm2, loss
P+Level product is 100mm2-75.69mm2=24.31mm2。
Using the structure of the utility model, the width of voltage slot is 0.28mm, and the side length of effective using area is 10mm-
0.28mmx2=9.44mm；Therefore effectively usable floor area is 9.44mmx9.44mm=89.11mm2, the P of loss+Level product is
100mm2-89.11mm2=10.89mm2。
The two compares, and effective usable floor area of the utility model improves 13.42mm than existing structure2, improve
17.7%, reduce raw material significantly, reduce production cost, improve electrical parameter, improves the overall performance of chip.
Embodiment 2:
A kind of rectifier diode chip, as shown in Figure 4, Figure 5, including growing base area N1, the P layer on the growing base area upper layer N1 is set
2 and P+Layer 3, is arranged in the N of growing base area N1 lower layer+Layer 4 and is covered on N+4 and P of layer+The metalization layer 7 on 3 surface of layer.It also sets up
There is a voltage slot 5, the voltage slot 5 is from P+Layer 3 extends downwardly into the N1 of growing base area, is provided with glassivation on the voltage slot 5
Layer 6.The surrounding of the diode chip for backlight unit is provided with N+End wall 8, the N+End wall from N+Layer extends upwardly to voltage slot 5
Bottom, the N+End wall 8 and N+Layer 4 is linked together.The N+The bottom of layer is provided with a circle groove 10, and groove 10 is located at N+It cuts
Only the lower section of wall and be located at N+Layer is internal, and the depth of groove 10 is identical as the depth of blind hole 9, other are the same as embodiment 1.
Embodiment 3:
The P layer 2 and P on the growing base area upper layer N1 is arranged in a kind of rectifier diode chip, including growing base area N1+Layer 3, setting
In the N of growing base area N1 lower layer+Layer 4 and is covered on N+4 and P of layer+The metalization layer 7 on 3 surface of layer.It is additionally provided with voltage slot 5, institute
Voltage slot 5 is stated from P+Layer 3 extends downwardly into the N1 of growing base area, is provided with glass passivation layer 6 on the voltage slot 5.Two pole
The surrounding of tube chip is provided with N+End wall 8, the N+End wall from N+Layer extends upwardly to the bottom of voltage slot 5, the N+Cut-off
Wall 8 and N+Layer 4 is linked together.The N+The bottom of layer is provided with a circle groove 10, and groove 10 is located at N+End wall 8 lower section and
Positioned at N+In the side edge of layer 4, it is located at N+Layer side edge on groove, that is, adjacent two chip share a groove, after scribing
The side edge of one single chip forms unilateral slot structure.The other the same as in Example 2.
Embodiment 4:
A kind of preparation method of rectifier diode chip, by taking the chip of pressure-resistant 2000V as an example, comprising the following steps:
1) first single side carries out laser boring on silicon wafer, and laser hole depth is 60-110 μm, and point pitch-row is 120 μm.
2) it is diffused after Wafer Cleaning with the paper source of N-type, time 6h.
3) N of the another side of non-laser boring is subtracted with sandblasting or thinned machine+Layer, then cleaning is stand-by.
4) it is placed on the silicon chip surface of not laser hole with the paper source of p-type, carries out load diffusion, time 30h is used after taking-up
After hydrofluoric acid dips, cleaning, drying is stand-by.
5) by the two-sided sandblasting of silicon wafer after drying, 1 is then boiled#、2#Liquid, cleaning, drying are stand-by.
6) it is dried for use after the silicon wafer after drying being got rid of photoresist, drying glue, exposure, development, rinsing.
7) stand-by silicon wafer will be dried to be placed in hybrid corrosion liquid, corrosion potentials slot, corrosion liquid formula (3:5:1/ hydrogen fluorine
Acid: nitric acid: glacial acetic acid), corrode 160-190 μm of groove depth, then uses (18 megaohms) of high purity water flushings 5 times or more, drying is stand-by.
8) drying stand-by having formed etching tank and removed is scraped into glassing on the silicon wafer face after photoresist, then preliminary drying
Dry to carry out glass powder sintering, temperature is 800 DEG C or so, is taken out for use after being cooled to room temperature slowly.
9) the burned silicon wafer of glass powder in slot is subjected to chemical nickel plating, silicon nickel alloy (temperature is 700 DEG C), after silicon nickel alloy
Secondary nickel plating, cleaning, drying are carried out again for use.
10) silicon wafer that nickel plating is good fills electricity with polyimides after scribing is good with scribing machine by the pattern scribing set
Indent is warming up to 300 DEG C or so drying slowly.
11) one single chip after drying tested, sorted, packed, be put in storage.
Claims (7)
1. the P layer and P on the growing base area upper layer N is arranged in a kind of rectifier diode chip, including growing base area N+Layer is arranged in growing base area
The N of N lower layer+Layer；It is additionally provided with voltage slot, the voltage slot is from P+Layer extends downwardly into the N of growing base area；It is characterized by: described
The surrounding of diode chip for backlight unit is provided with N+End wall, the N+End wall from N+Layer extends upwardly to the bottom of voltage slot.
2. rectifier diode chip as claimed in claim 1, it is characterised in that: the N+End the inside of wall to voltage slot
The vertical range of side is not less than the width of growing base area N.
3. rectifier diode chip as claimed in claim 1, it is characterised in that: the N+The width of cut-off wall is not less than
80um。
4. rectifier diode chip as claimed in claim 1, it is characterised in that: the N+It is blind that the bottom of layer is provided with a circle
Hole, blind hole are located at N+End the lower section of wall.
5. rectifier diode chip as claimed in claim 4, it is characterised in that: the blind hole is laser hole or etched hole.
6. rectifier diode chip as claimed in claim 1, it is characterised in that: the N+It is recessed that the bottom of layer is provided with a circle
Slot, groove are located at N+End the lower section of wall.
7. rectifier diode chip as claimed in claim 6, it is characterised in that: the groove is located at N+Layer is internal or is located at N+In the side edge of layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820743538.5U CN208189598U (en) | 2018-05-17 | 2018-05-17 | A kind of rectifier diode chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820743538.5U CN208189598U (en) | 2018-05-17 | 2018-05-17 | A kind of rectifier diode chip |
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| Publication Number | Publication Date |
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| CN208189598U true CN208189598U (en) | 2018-12-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108565293A (en) * | 2018-05-17 | 2018-09-21 | 安徽省祁门县黄山电器有限责任公司 | A kind of rectifier diode chip |
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2018
- 2018-05-17 CN CN201820743538.5U patent/CN208189598U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108565293A (en) * | 2018-05-17 | 2018-09-21 | 安徽省祁门县黄山电器有限责任公司 | A kind of rectifier diode chip |
| CN108565293B (en) * | 2018-05-17 | 2024-06-21 | 黄山芯微电子股份有限公司 | Rectifier diode chip |
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Address after: 245000 No. 449 Xinxing Road, Qimen County, Anhui, Huangshan City Patentee after: Huangshan core Microelectronics Co., Ltd Address before: 245000 No. 449 Xinxing Road, Qimen County, Anhui, Huangshan City Patentee before: HUANGSHAN ELECTRIC APPLIANCE Co.,Ltd. |