CN205488142U - Low pressure surpasses knot MOSFET terminal structure - Google Patents
Low pressure surpasses knot MOSFET terminal structure Download PDFInfo
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- CN205488142U CN205488142U CN201620261345.7U CN201620261345U CN205488142U CN 205488142 U CN205488142 U CN 205488142U CN 201620261345 U CN201620261345 U CN 201620261345U CN 205488142 U CN205488142 U CN 205488142U
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Abstract
The utility model discloses a low pressure surpasses knot MOSFET terminal structure, active area and terminal area including the epitaxial layer division, be provided with active area zanjon groove in the active area, be provided with in the terminal area and contain two at least and around the terminal area zanjon groove in active area zanjon groove, wherein, at least one is close to the terminal area zanjon groove in active area zanjon groove is the isolating ring, and an at least terminal area zanjon groove that is close to the scribing groove is cut -off ring, sedimentary polycrystalline silicon layer is the zero potential with source electrode surface metal short circuit in the isolating ring, cut -off ring floats in vain. The utility model discloses under can keeping the unchangeable prerequisite of terminal breakdown voltage, reduce the light shield quantity in the device production to can enough traditional semiconductor device manufacture technology realize, can not increase the degree of difficulty of technology, thereby reduce device manufacturing cost.
Description
Technical field
This utility model belongs to semiconductor power device technology field, is specifically related to a kind of low pressure super node MOSFET terminal structure.
Background technology
For traditional power MOSFET device, there is certain trade-off relation (Ron ∝ BV in device on-resistance (Ron) and source and drain breakdown voltage2 . 5), limit the development of power MOSFET device for a long time.Low pressure super node MOSFET utilizes charge balance concept so that even if N-type drift region also can realize the breakdown voltage that device is higher in the case of higher-doped concentration, thus obtain relatively low conducting resistance, has broken the theoretical silicon limit of conventional power MOSFET.Yet with device terminal electric field Relatively centralized so that its breakdown voltage ratio is relatively low, so a good Terminal Design is indispensable for power device.
The market competitiveness of device, in addition to the unit for electrical property parameters that device self is good, additionally depends on self manufacturing cost.Reducing individual devices cost conveniently to set about from two, one is to be designed by optimization, is continuously increased the number of devices above single silicon chip；Two is the process costs reducing silicon chip, and process costs depends primarily on the reticle quantity in flow technique.
Current existing low pressure super node MOSFET is when manufacturing, field oxide photoetching process can be used to retain the field oxide of terminal shading ring region surface when field oxide returns quarter, masking layer during in order to inject as p trap, only etch away the field oxide above active area and cut-off ring region, can form the p-n junction cut-off ring as terminal after p trap injects, this kind of method needs when etching field oxide to use reticle.
Utility model content
In view of this, main purpose of the present utility model is to provide a kind of low pressure super node MOSFET terminal structure.
For reaching above-mentioned purpose, the technical solution of the utility model is achieved in that
This utility model embodiment provides a kind of low pressure super node MOSFET terminal structure, this terminal structure includes active area and the termination environment that epitaxial layer divides, active area deep trench it is provided with in described active area, it is provided with in described termination environment including at least two and is surrounded with the termination environment deep trench of source region deep trench, wherein, at least one is shading ring near the termination environment deep trench of described active area deep trench, and at least one is cut-off ring near the termination environment deep trench of scribe line；In described shading ring, the polysilicon layer of deposition and source electrode surface metal short circuit are zero potential, described cut-off ring floating.
In such scheme, the spacing between described terminal deep trench be 1um and more than.
In such scheme, described shading ring and cut-off ring two deep trench spacing close to each other 5um and more than.
In such scheme, the width of described termination environment deep trench is equal to or more than the width of described active area deep trench.
Compared with prior art, the beneficial effects of the utility model:
On the premise of this utility model can keep terminal breakdown voltage constant, reduce the light shield quantity in device production, and can realize with traditional semiconductor fabrication process, the difficulty of technique will not be increased, thus reduce device production cost.
Accompanying drawing explanation
Fig. 1 is the sectional view of this utility model device；
Fig. 2 is the schematic diagram of this utility model step one；
Fig. 3 is the schematic diagram of this utility model step 2；
Fig. 4 is the schematic diagram of this utility model step 3；
Fig. 5 is the schematic diagram of this utility model step 4；
Fig. 6 is the schematic diagram of this utility model step 5；
Fig. 7 is the schematic diagram of this utility model step 6；
Fig. 8 is the schematic diagram of this utility model step 7；
Fig. 9 is the schematic diagram of this utility model step 8；
Figure 10 is the schematic diagram of this utility model step 9；
Figure 11 is the schematic diagram of this utility model step 10；
Figure 12 is the schematic diagram of this utility model step 11；
Figure 13 is the schematic diagram of this utility model step 12；
Figure 14 is the schematic diagram of this utility model step 13；
Figure 15 is the schematic diagram of this utility model step 14.
Detailed description of the invention
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, this utility model is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain this utility model, is not used to limit this utility model.
This utility model embodiment provides a kind of low pressure super node MOSFET terminal structure, as shown in Figure 1, this terminal structure includes active area and the termination environment that epitaxial layer divides, active area deep trench it is provided with in described active area, it is provided with in described termination environment including at least two and is surrounded with the termination environment deep trench of source region deep trench, wherein, at least one is shading ring near the termination environment deep trench of described active area deep trench, and at least one is cut-off ring near the termination environment deep trench of scribe line；This utility model uses deep groove structure to instead of traditional p-n junction and does the cut-off ring of termination environment, and such P-well is injected can carry out general note, it is no longer necessary to field oxygen makees masking layer, therefore need not extra reticle when field oxide returns quarter.In described shading ring, the polysilicon layer of deposition and source electrode surface metal short circuit are zero potential, described cut-off ring floating.
In view of technique problem of implementation, as a kind of preferred version of the present utility model:
Spacing between described terminal deep trench be 1um and more than；
Described shading ring and cut-off ring two deep trench spacing close to each other 5um and more than；
The width of described termination environment deep trench is equal to or more than the width of described active area deep trench.
This utility model embodiment provides the manufacture method of a kind of low pressure super node MOSFET terminal structure, and as shown in figures 1-15, the method is realized by following steps:
Step one: n type heavily doped n+ substrate is provided, and forms N-shaped epitaxial layer on n+ substrate, as shown in Figure 2；
Step 2: forming deep trench by photoetching, dry etching in N-shaped extension, described deep trench includes source region deep trench and termination environment deep trench, described termination environment deep trench surrounds active area deep trench, as shown in Figure 3；
Step 3: by wet thermal oxidation process bottom described deep trench and sidewall growth field oxide, as shown in Figure 4；
Step 4: carry out polysilicon for the first time by polycrystalline silicon deposition process and deposit, as shown in Figure 5；
Step 5: carry out polysilicon by dry corrosion process and return quarter, is etched to polysilicon and epitaxial layer upper surface flush, as shown in Figure 6；
Step 6: add wet corrosion technique by dry method and remove surface field oxide layer, as shown in Figure 7；
Step 7: successively carry out back carving to the first polysilicon in active area deep trench and field oxide by photoetching, etching polysilicon and wet corrosion technique; make above described active area deep trench, to obtain two shallow trenchs interconnected; the first polysilicon and field oxide in the deep trench of described termination environment do not return quarter, as shown in Figure 8 under the protection of photoresist；
Step 8: grow gate oxide through dry method thermal oxidation technology, forms MOSFET element grid oxygen, as shown in Figure 9；
Step 9: polysilicon deposit for the second time, as shown in Figure 10；
Step 10: polysilicon dry back is carved for the second time, forms shallow slot MOSFET element grid, as shown in figure 11；
Step 11: P-BODY injects, and forms p-well, as shown in figure 12；
Step 12: N+ injects, and forms device source electrode, as shown in figure 13；
Step 13: dielectric layer deposition, contact hole photoetching and pitting corrosion, as shown in figure 14；
Step 14: complete contact hole tungsten and fill, and surface metal technique formation device Facad structure, as shown in figure 15；
Step 15: finally complete back metal technique, forms device drain terminal, completes low pressure super node MOSFET terminal structure, as shown in Figure 1.
Use trench termination structure and the manufacture method of power MOSFET described in the utility model, the deep trench simultaneously made with active area is utilized to do shading ring and cut-off ring, need not reticle when field oxide returns quarter the field oxygen of shading ring with cut-off ring surface is sheltered, active area all returns quarter with the field oxygen on surface, termination environment, as shown in Figure 7, the method simplifies technique on the premise of not affecting device property, has saved manufacturing cost.
Described step 6 particularly as follows:
Step one: field oxide etching process uses oxide layer dry corrosion process jointly to complete with wet corrosion technique, the oxide layer about first dry etching residue 1000 ± 200 thickness, then use wet etching residue oxide layer all to be divested；
Step 2: field oxide etches rear oxidation layer and is not more than 500A to deep trench sunken inside.
The above, preferred embodiment the most of the present utility model, it is not intended to limit protection domain of the present utility model.
Claims (4)
1. a low pressure super node MOSFET terminal structure, it is characterized in that, this terminal structure includes active area and the termination environment that epitaxial layer divides, active area deep trench it is provided with in described active area, it is provided with in described termination environment including at least two and is surrounded with the termination environment deep trench of source region deep trench, wherein, at least one is shading ring near the termination environment deep trench of described active area deep trench, and at least one is cut-off ring near the termination environment deep trench of scribe line；In described shading ring, the polysilicon layer of deposition and source electrode surface metal short circuit are zero potential, described cut-off ring floating.
A kind of low pressure super node MOSFET terminal structure the most according to claim 1, it is characterised in that: the spacing between described terminal deep trench be 1um and more than.
A kind of low pressure super node MOSFET terminal structure the most according to claim 1 and 2, it is characterised in that: described shading ring two deep trench spacing close to each other with ending ring 5um and more than.
A kind of low pressure super node MOSFET terminal structure the most according to claim 3, it is characterised in that: the width of described termination environment deep trench is equal to or more than the width of described active area deep trench.
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| CN201620261345.7U CN205488142U (en) | 2016-03-31 | 2016-03-31 | Low pressure surpasses knot MOSFET terminal structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105655402A (en) * | 2016-03-31 | 2016-06-08 | 西安龙腾新能源科技发展有限公司 | Low-voltage super-junction MOSFET (metal-oxide-semiconductor field effect transistor) terminal structure and method for manufacturing same |
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2016
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105655402A (en) * | 2016-03-31 | 2016-06-08 | 西安龙腾新能源科技发展有限公司 | Low-voltage super-junction MOSFET (metal-oxide-semiconductor field effect transistor) terminal structure and method for manufacturing same |
| CN105655402B (en) * | 2016-03-31 | 2019-11-19 | 西安龙腾新能源科技发展有限公司 | Low pressure super node MOSFET terminal structure and its manufacturing method |
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Address after: 710021 export processing zone, No. twelve, 1 road, Fengcheng, Shaanxi, Xi'an Patentee after: Longteng Semiconductor Co.,Ltd. Address before: 710021 export processing zone, No. twelve, 1 road, Fengcheng, Shaanxi, Xi'an Patentee before: LONTEN SEMICONDUCTOR Co.,Ltd. Address after: 710021 export processing zone, No. twelve, 1 road, Fengcheng, Shaanxi, Xi'an Patentee after: LONTEN SEMICONDUCTOR Co.,Ltd. Address before: 710021 export processing zone, No. twelve, 1 road, Fengcheng, Shaanxi, Xi'an Patentee before: XI'AN LONTEN RENEWABLE ENERGY TECHNOLOGY Inc. |
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Effective date of registration: 20220321 Address after: 710000 export processing zone, No. 1, Fengcheng 12th Road, Xi'an Economic and Technological Development Zone, Shaanxi Province Patentee after: Longteng Semiconductor Co.,Ltd. Patentee after: Xi'an Longxiang Semiconductor Co.,Ltd. Address before: 710021 export processing zone, No.1, Fengcheng 12th Road, Xi'an City, Shaanxi Province Patentee before: Longteng Semiconductor Co.,Ltd. |