CN102751315B

CN102751315B - High voltage terminal

Info

Publication number: CN102751315B
Application number: CN201110303575.7A
Authority: CN
Inventors: 李思敏
Original assignee: Individual
Current assignee: Individual
Priority date: 2011-10-09
Filing date: 2011-10-09
Publication date: 2014-12-24
Anticipated expiration: 2031-10-09
Also published as: CN102751315A

Abstract

Disclosed is a high voltage terminal. A heavy doping P+ type groove-shaped field limiting ring is arranged on the periphery of an active area of a gate associated transistor of a groove-shaped gate polycrystalline silicon structure, the depth of a groove is in a range from 1micrometers to 6 micrometers, a heavy doping N+ type polycrystalline silicon annular field plate is arranged above the field limiting ring, the upper surface of the polycrystalline silicon field plate is connected with a metal layer AL, and the metal layer AL is connected with the bottom surface of the groove of the P+ type groove-shaped field limiting ring. The high voltage terminal has the advantages that the high voltage terminal is matched with a transistor core process of the gate associated transistor of the groove-shaped gate polycrystalline silicon structure, materials are saved, photoetching times are reduced, the cost is lowered, and the processing cycle is shortened.

Description

A kind of secondary terminal

Technical field

The present invention relates to a kind of secondary terminal, belong to Si semiconductor power device technology field.

Background technology

The gate associated transistor of grooved gate polysilicon structure is a kind of novel high-pressure power device.The terminal of high voltage power device generally adopts the termination extension (ITE) of field limiting ring, field plate and knot.Junior college's teaching material " power MOSFET and high voltage integrated circuit " (Chen Xing assist publishing house of Southeast China University May nineteen ninety) PP 86-120 has detailed introduction to this.

Fig. 1 is the structural representation of the field limiting ring terminal of prior art, and Fig. 2 is the structural representation of the terminal that the field plate of prior art combines with field limiting ring.The lower floor 41 of silicon substrate 4 is N+ type silicon, and upper strata 42 is N-type silicon.The main knot 2 in base, field limiting ring 21 and 22 are territory, p type island region, and silicon dioxide insulating layer 7,71 and 72 covers the upper surface of silicon substrate.Aluminium field plate 1,11 and between 12 and silicon substrate across silicon dioxide insulating layer 7,71 and 72, aluminium field plate 1,11 with 12 respectively knot 2,21 main with base be connected with 22.Because the main knot 2 in base, field limiting ring 21 and 22 make on a silicon substrate, so, also can regard as between the main knot 2 of aluminium field plate 1,11 and 12 and base, field limiting ring 21 and 22 across silicon dioxide insulating layer 7,71 and 72.

In order to reduce costs, choosing of secondary terminal is general in accordance with two principle: the least possible photoetching number of times, terminal width narrow as far as possible.Commercially available power crystal is effective obtains the most generally field limiting ring terminal, and its advantage is simply, is easy to processing, but terminal width is wider.Some documents are pointed out, field limiting ring is combined with field plate, and the width of terminal can be made significantly to reduce.But seldom adopt this kind of structure in commercially available power transistor, reason is the bad control of technique.Conventional field plate adopts aluminium field plate, and the corrosion of aluminium generally adopts wet etching, the bad control of its width, and consistency and the repeatability of processing are poor, thus have had a strong impact on the performance of the secondary terminal that field limiting ring combines with field plate.

The gate associated transistor of the grooved gate polysilicon structure of prior art adopts ITE terminal structure.Adopt the termination extension of knot, i.e. ITE, can adopt the narrowest terminal width, but, need to do a photoetching specially more.The technique of the gate associated transistor of the grooved gate polysilicon structure of prior art adopts 8 photoetching, i.e. photoetching ITE, flute profile grid region, base, emitter region, polysilicon, contact hole, aluminium and passivation layer.

Carefully analyze and can see, ITE can cancel, and for the formation of active area, base and emitter region can only complete with 1 photoetching and autoregistration, and polysilicon and contact hole also can only complete with 1 photoetching and autoregistration.And key is corresponding secondary terminal how to match with the active area technique of tube core.Adopt flute profile grid region to do field limiting ring and save material than conventional planar shaped field limiting ring, same junction depth, the area is laterally little.Adopt polysilicon field plate to be easy to control than conventional aluminium field plate, because polysilicon field plate adopts plasma etching to be formed, not only machining accuracy is high, and reproducible.Polysilicon field plate is mixed secondary terminal that flute profile field limiting ring forms not only have area occupied little, bear that voltage is high, consistency and reproducible advantage, and match with the active area technique of tube core, photoetching number of times can be saved, reduce chip manufacture cost.

Summary of the invention

In view of above-mentioned, the object of the invention is for the deficiencies in the prior art, a kind of new high-voltage terminal structure is provided, the tube core technique of the gate associated transistor of it and grooved gate polysilicon structure matches, and can save material, reduces photoetching number of times, reduce costs, shorten the process-cycle.

For completing object of the present invention, the technical scheme that the present invention takes is:

A kind of secondary terminal, in the periphery of the active area of the gate associated transistor of grooved gate polysilicon structure, has field limiting ring, has field plate, have insulator separation, it is characterized in that between field limiting ring and field plate above field limiting ring:

Field limiting ring is heavy doping P+ type flute profile ring, and the degree of depth of groove is 1-6 micron:

Field plate is heavy doping N+ type polysilicon ring, and the upper surface of polysilicon field plate is connected with metallic aluminum, and metallic aluminum is connected with the bottom surface of the groove of P+ type flute profile field limiting ring.

Compared with prior art, the invention has the beneficial effects as follows: save photoetching number of times, significantly reduce terminal width, reduce cost, shorten the process-cycle.

Accompanying drawing explanation

Fig. 1 and Fig. 2 is the structural representation of prior art:

Fig. 3 is the structural representation of one embodiment of the present of invention.

Embodiment

The present invention is described in detail by preferred embodiment hereinafter with reference to accompanying drawing.

In figure: 1. with flute profile grid region, (, prior art is the main knot in base, ), the aluminium field plate be connected: the 11. aluminium field plates be connected with first field limiting ring: the 12. aluminium field plates be connected with second field limiting ring: the main knot in 2.P type base: first P type field limiting ring of the secondary terminal of 21. prior arts: second P type field limiting ring of the secondary terminal of 21. prior arts: 4. silicon substrate: 41.N+ type silicon substrate lower floor: 42.N-type silicon substrate upper strata: the silicon groove in 5.P+ type flute profile grid region: the silicon groove of 51. first P+ type flute profile field limiting rings: the silicon groove of 52. second P+ type flute profile field limiting rings: 6.P+ type flute profile grid region: 61. first P+ type flute profile field limiting rings: 62. second P+ type flute profile field limiting rings: 7.P+ type flute profile grid region, (, prior art is the main knot in P type base, ), and the silicon dioxide layer between polysilicon field plate: 71. first P+ type flute profile field limiting rings, (, prior art is P type field limiting ring, ), and the silicon dioxide layer between field plate: 72. second P+ type flute profile field limiting rings, (, prior art is P type field limiting ring, ), and the silicon dioxide layer between field plate: the N+ type polysilicon field plate above 9.P+ type flute profile grid region: the N+ type polysilicon field plate above 91. first P+ type flute profile field limiting rings: the N+ type polysilicon field plate above 92. second P+ type flute profile field limiting rings.

In the secondary terminal embodiment of the gate associated transistor of the grooved gate polysilicon structure of the present invention shown in Fig. 3, the lower floor 41 of silicon substrate 4 is collector electrode, it is the N+ type silicon of thickness 420 μm of resistivity 0.01 Ω .cm, and upper strata 42 is the N-type silicon of 60 μm of resistivity 45 Ω .cm.3 concentric flute profile rings 5,51 and 52 around gate associated transistor are had at the upper surface of silicon substrate 4.Simultaneously flute profile ring 5, flute profile ring 51 and flute profile ring 52 process with the flute profile grid region 5 of the gate associated transistor of grooved gate polysilicon structure, and the part in inner ring flute profile ring 5 inherently flute profile grid region 5.The degree of depth of the groove of flute profile ring 5,51 and 52 is 3 μm.The degree of depth of groove should not be shallower than 1 μm, also should not dark mistake 6 μm, has so both been convenient to processing, and can have given full play to again the advantage of bathtub construction.The width of flute profile ring 5 is 20 μm, and flute profile ring 51 and 52 width is 5 μm, and the distance between flute profile ring 5 and 51 is 20 μm, and the distance between flute profile ring 51 and 52 is 25 μm.Flute profile ring 5,51 and 52 is by injecting boron ion and being advanced formation P+ type area with high mercury 6,61 and 62, P+ type area with high mercury 6 to be flute profile grid region, and 61 and 62 is first and second field limiting ring.The degree of depth of the P+N-knot in region 6,61 and 62 is 8 μm.Above flute profile grid region 6, field limiting ring 61 and 62, there is thickness to be the N+ type polysilicon field plate 9,91 and 92 of 0.5 μm respectively.The outboard alignment of the inner side of polysilicon field plate 9,91 and 92 and flute profile grid region 6, field limiting ring 61 and 62, the width of polysilicon field plate 9,91 and 92 is 10 μm.In flute profile grid region 6, field limiting ring 61 and 62 and polysilicon field plate 9, the silicon dioxide insulating layer 7,71 and 72 that has thickness to be 1.5 μm between 91 and 92 respectively.Polysilicon field plate 9,91 with 92 upper surface be that the aluminium lamination 1,11 of 4 μm is connected with 12 respectively with thickness.Aluminium lamination 1,11 and 12 also can regard aluminium field plate as, in flute profile grid region 6, the silicon dioxide insulating layer of the bottom of the groove of field limiting ring 61 and 62 is corroded totally, and aluminium lamination 1,11 is connected with the bottom of groove of the flute profile field limiting ring of 62 with flute profile grid region 6, field limiting ring 61 respectively with 12.Outermost field limiting ring 62 leaves dicing lane 30 μm, is beneficial to strengthen voltage endurance capability.

Above-mentioned whole secondary terminal width is 85 μm, can reach the puncture voltage of 600V.The width algorithm conveniently of secondary terminal ring is the outside from inner ring, the distance namely from the outside of cannelure 5 to dicing lane.

The die active district technique of the gate associated transistor of the grooved gate polysilicon structure of secondary terminal of the present invention and 5 photoetching matches.And adopt conventional plane field limiting ring terminal, at least need 140 μm, also need 6 photoetching.And compared with the ITE terminal of the gate associated transistor of the grooved gate polysilicon structure of prior art, 3 photoetching that the latter is multiplex, the terminal width of ITE also needs 65 μm.Therefore, the die active district technique of the gate associated transistor of the grooved gate polysilicon structure of high-voltage terminal structure of the present invention and 5 photoetching matches, and can save the tube core cost of 20-30%, and significantly reduce the process-cycle.

What need statement is; above-described embodiment is only unrestricted for the present invention will be described, therefore, for a person skilled in the art; when not deviating from spirit and scope of the invention, various apparent change is carried out to it, all should within protection scope of the present invention.

Claims

1. a secondary terminal, in the periphery of the active area of the gate associated transistor of grooved gate polysilicon structure, has field limiting ring, has field plate, have insulator separation, it is characterized in that between field limiting ring and field plate above this field limiting ring:

Described field limiting ring is heavy doping P+ type flute profile ring, and the degree of depth of groove is 1-6 micron:

Described field plate is heavy doping N+ type polysilicon ring, and the upper surface of polysilicon field plate is connected with metallic aluminum, and metallic aluminum is connected with the bottom surface of the groove of P+ type flute profile field limiting ring.