CN108767002A - A kind of terminal for semiconductor power device - Google Patents
A kind of terminal for semiconductor power device Download PDFInfo
- Publication number
- CN108767002A CN108767002A CN201810873584.1A CN201810873584A CN108767002A CN 108767002 A CN108767002 A CN 108767002A CN 201810873584 A CN201810873584 A CN 201810873584A CN 108767002 A CN108767002 A CN 108767002A
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- field plate
- field
- polysilicon
- metal
- plate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 82
- 229920005591 polysilicon Polymers 0.000 claims abstract description 81
- 239000002184 metal Substances 0.000 claims abstract description 73
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 19
- 230000015556 catabolic process Effects 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000001727 in vivo Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of terminal for semiconductor power device, which includes：Collector, base area, multiple field limiting rings and multiple field plate groups corresponding with the field limiting ring, the field plate group includes the first polysilicon field plate and Metal field plate being electrically connected with each other, first polysilicon field plate, the Metal field plate are sequentially located at the top of the field limiting ring, first polysilicon field plate and the Metal field plate are electrically connected with the field limiting ring, and the Metal field plate covers first polysilicon field plate.The terminal for semiconductor power device of the present invention can improve breakdown voltage and reduce the spike electric field at field plate edge.
Description
【Technical field】
The present invention relates to technical field of semiconductor device, more particularly to a kind of terminal for semiconductor power device.
【Background technology】
For the terminal (Insulated Gate Bipolar Transistor, IGBT) of semiconductor power device, be by
The compound full-control type voltage driven type power semiconductor of BJT (double pole triode) and MOS (insulating gate type field effect tube) compositions
Device, it has the advantages that unipolar device and bipolar devices simultaneously, for example, driving circuit is simple, control circuit power consumption and at
This is low, on-state voltage drop is low, becomes one of semiconductor devices power of current mainstream.
In IGBT manufacturing processes, multiple oxidation process, mainly thermal oxide so that be inevitably present in oxide layer
Some positive charges.PN junction intermediate approximation is in planar junction, and in edge, such as near the interface of silicon and silica, by
Positive charge can attract electronics to cause the concentration on silicon face N-type region surface to increase in silicon face concentration in oxide layer, this will be in silicon
A vertical electric field that silicon substrate is directed toward by oxide layer, the electric field and depletion layer electric field at surface are formed at the near surface of substrate
Closing electric field will gather at the silicon face on the outside of PN junction, and then depletion layer is caused to narrow compared to inside at surface, electric-field strength
Degree is higher than in vivo, is easy to happen breakdown so that the breakdown voltage of device and diffusion junctions phase in ideal plane existing for no interface charge
Than can decrease.
On the other hand, the IGBT device in practical application, chip surface usually cover for encapsulation insulating layer or
Epoxy resin.When IGBT bears big voltage, peak electric field is formed in vivo, the insulating layer or epoxy resin layer of surface covering
Polarization is will produce, and the produced charge that polarizes can inhibit the depletion layer of surface of silicon to extend, and peak surface electric field is caused to increase.
When peak electric field reaches breakdown point, the variation or degeneration of pressure resistance are may result in, IGBT is also resulted in and fails in some environments.
However, existing terminal structure includes electric field limitation ring (FLR), field plate techniques, knot extended surface etc., these structures
Actually play the role of outward broadening main knot depletion region, finally improves breakdown voltage.Wherein field plate structure is because it can be with
It is realized using common process, terminal area is small, the advantages that being not very sensitive to interface charge, is widely used, but the structure
Potential difference between midfield plate edge and silicon is very big, causes to be easy to puncture in the outer edge of field plate.
Therefore, it is necessary to a kind of terminal for semiconductor power device be provided, to solve asking present in the prior art
Topic.
【Invention content】
The purpose of the present invention is to provide a kind of terminal for semiconductor power device, can improve breakdown voltage and
Reduce the spike electric field at field plate edge.
In order to solve the above technical problems, the present invention provides a kind of terminal for semiconductor power device comprising：
Collector, base area, multiple field limiting rings and multiple field plate groups corresponding with the field limiting ring, the field plate group include
The first polysilicon field plate and Metal field plate being electrically connected with each other, first polysilicon field plate, the Metal field plate position successively
In the top of the field limiting ring, first polysilicon field plate and the Metal field plate are electrically connected with the field limiting ring, institute
It states Metal field plate and covers first polysilicon field plate.
In the terminal for semiconductor power device of the present invention, the terminal for semiconductor power device is also wrapped
The second polysilicon field plate is included, second polysilicon field plate is between the field limiting ring and the Metal field plate, and the gold
Belong to field plate and only partly covers second polysilicon field plate.
In the terminal for semiconductor power device of the present invention, second polysilicon field plate and first polycrystalline
Silicon field plate is located at same layer, and setting is spaced between second polysilicon field plate and first polysilicon field plate.
In the terminal for semiconductor power device of the present invention, the part covering institute of first part of the Metal field plate
The second polysilicon field plate is stated, and the first part of the Metal field plate is the separate Metal field plate and institute in the Metal field plate
State the part of the junction of field limiting ring.
In the terminal for semiconductor power device of the present invention, the Metal field plate covers second polysilicon field
The half of plate.
In the terminal for semiconductor power device of the present invention, the length of the Metal field plate is more than more than described first
The length of crystal silicon field plate.
In the terminal for semiconductor power device of the present invention, first polysilicon field plate and the field limiting ring it
Between be provided with field oxide, the first via is provided on the field oxide, first polysilicon field plate passes through described first
Via is electrically connected with the field limiting ring.
In the terminal for semiconductor power device of the present invention, first polysilicon field plate and the Metal field plate
Between and the Metal field plate and the field limiting ring not covered by first polysilicon field plate and the field oxide between
It is provided with dielectric layer, the second via is provided on the dielectric layer, the Metal field plate passes through second via and the field
Ring is limited to be electrically connected.
In the terminal for semiconductor power device of the present invention, third via, institute are additionally provided on the dielectric layer
The first polysilicon field plate is stated to be electrically connected by the third via and the Metal field plate.
In the terminal for semiconductor power device of the present invention, second via and first via are located at institute
State the same side of field limiting ring.
The terminal for semiconductor power device of the present invention, by using the field plate of polysilicon field plate and Metal field plate
Group, and Metal field plate is electrically connected with field limiting ring and polysilicon field plate respectively so that main knot depletion region effectively broadens outward, to
It improves breakdown voltage and reduces the spike electric field at field plate edge.
【Description of the drawings】
Fig. 1 is the structural schematic diagram for the terminal for being currently used for semiconductor power device；
Fig. 2 is the structural schematic diagram of the terminal for semiconductor power device of the present invention.
【Specific implementation mode】
The explanation of following embodiment is to refer to additional schema, to illustrate the particular implementation that the present invention can be used to implement
Example.The direction term that the present invention is previously mentioned, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outside", " side "
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be illustrate and understand the present invention, rather than to
The limitation present invention.The similar unit of structure is to be given the same reference numerals in the figure.
As shown in Figure 1, the existing terminal for semiconductor power device include collector 11, base area 12 (namely lining
Bottom), multiple field limiting rings 13, the dielectric layer 14 and field plate 15 being arranged between field limiting ring 13 and field plate 15, the field limiting ring 13
Include being formed by two kinds of doped regions that conduction type is identical but doping concentration is different, which is P+ types.
Fig. 2 is please referred to, Fig. 2 is the structural schematic diagram of the terminal for semiconductor power device of the present invention.
As shown in Fig. 2, the terminal for semiconductor power device of the present invention includes collector 11, base area 12, multiple fields
It includes the first polycrystalline being electrically connected with each other to limit ring 13 and multiple field plate groups corresponding with the field limiting ring 13, the field plate group
Silicon field plate 22 and Metal field plate 24, the collector 11 are the p semiconductors of the second conduction type, and base area 12 is the first conduction type
N semiconductors.The field limiting ring 13 includes being formed by two kinds of doped regions that conduction type is identical but doping concentration is different, should
Conduction type is P+ types.
First polysilicon field plate 22, the Metal field plate 24 are sequentially located at the top of the field limiting ring 13, Ye Jisuo
The top that the first polysilicon field plate 22 is located at the field limiting ring 13 is stated, the Metal field plate 24 is located at first polysilicon field plate
22 top.First polysilicon field plate 22 and the Metal field plate 24 are electrically connected with the field limiting ring 13, the gold
Belong to field plate 24 and covers first polysilicon field plate 22.In one embodiment, the Metal field plate 24 is completely covered described
One polysilicon field plate 22.The Metal field plate 24 constitutes step-like field plate group with first polysilicon field plate 22.
Wherein the length of the Metal field plate 24 is more than the length of first polysilicon field plate 22.Due to Metal field plate 24
Length to be longer than the length of the first polysilicon field plate 22 so that the two forms the structure of step field plate so that main knot consumes
Area to the greatest extent effectively broadens outward, further increases breakdown voltage.
Wherein, field oxide 21, the field oxygen are provided between first polysilicon field plate 22 and the field limiting ring 12
Change and be provided with the first via 201 on layer 21, first polysilicon field plate 22 passes through first via 201 and the field limiting ring
13 are electrically connected.
Wherein, between first polysilicon field plate 22 and the Metal field plate 24 and the Metal field plate 24 with not by
It is both provided with dielectric layer 25, the medium between the field limiting ring 12 that first polysilicon field plate 22 and the oxide layer 21 cover
It is provided with the second via 202 on layer 25, the Metal field plate 24 is electrically connected by second via 202 with the field limiting ring 13
It connects.In one embodiment, second via 202 and first via 201 are located at the same side of the field limiting ring 13.
Wherein, third via 203 is additionally provided on the dielectric layer 25, first polysilicon field plate 22 passes through described
Three vias 203 are electrically connected with the Metal field plate 24.In one embodiment, the thickness of the dielectric layer 25 is more than the field
The thickness of oxide layer 21 so that the depth of second via 202 is more than the depth of first via 201.
In another embodiment, the terminal for semiconductor power device further includes the second polysilicon field plate 23, institute
The second polysilicon field plate 23 is stated between the field limiting ring 13 and the Metal field plate 24, and the only part of the Metal field plate 24
Cover second polysilicon field plate 23.Second polysilicon field plate 23 is not electrical with field limiting ring 13 and Metal field plate 24
Connection.Field oxide 21 is also located between the second polysilicon field plate 23 and the field limiting ring 13.Dielectric layer 25 is also located at more than second
Between crystal silicon field plate 23 and the Metal field plate 24.Due to the presence of the second polysilicon field plate, when IGBT bears pressure resistance, the areas N-
For high potential, P+ field limiting rings area is low potential, Metal field plate 24 and 13 equipotential of field limiting ring, is also low potential.So that a part
Power line is from the areas N to the second polysilicon field plate 23 and another part power line from the second polysilicon field plate 23 to Metal field plate
24.Because field plate is floating thus, the flux of this two parts power line is equal.This be equivalent in the areas N of semiconductor depletion layer and
Metal layer introduces opposite polarity charge respectively, and the direction of electric field and original electric field that both charges generate is on the contrary, therefore
Reduce peak value electric field.
In one embodiment, in order to simplify making technology, second polysilicon field plate 23 and first polysilicon
Field plate 22 is located at same layer, and setting is spaced between second polysilicon field plate 23 and second polysilicon field plate 22.Institute
It states between the second polysilicon field plate 23 and first polysilicon field plate 22 by there is dielectric layer 25 to be isolated.In an embodiment
In, second polysilicon field plate 23 is with first polysilicon field plate 22 by made from same making technology.
The first part part of the Metal field plate 24 covers second polysilicon field plate 23, and the Metal field plate 24
First part be the junction far from the Metal field plate 24 and the field limiting ring 13 in the Metal field plate 24 part.Than
If the first part of the Metal field plate 24 is the part far from the second via 202 and the first via 201.When the second via 202
When being located at the left side of Metal field plate 24 with the first via 201, the first part of the Metal field plate 24 is such as right part.When
When second via 202 and the first via 201 are located at the right side of Metal field plate 24, the first part of the Metal field plate 24 is such as
Left part.
The Metal field plate 24 covers the half of second polysilicon field plate 23.That is, and the second polysilicon field plate 23
Center correspond to the right edge position of Metal field plate 24, to further decrease between Metal field plate edge and silicon substrate
Potential difference, and then effectively reduce spike electric field.
Due to the field plate group by using polysilicon field plate and Metal field plate so that main knot depletion region effectively broadens outward；
Avoid in silicon and silicon dioxide interface electric field concentration phenomenon, improve breakdown voltage, and Metal field plate respectively with field limiting ring and
Polysilicon field plate is electrically connected so that Metal field plate keeps equipotential with field limiting ring and polysilicon field plate respectively.Due to metal field
Plate covers polysilicon field plate, so as to form the structure of step field plate so that main knot depletion region effectively broadens outward, improves and hits
Voltage is worn, in addition, also reducing the spike electric field at field plate edge.
It should be understood that other than the field limiting ring that the present invention is connected in addition to first with IGBT cellulars, each field limiting ring later
13 Metal field plate 24 joins in vertical direction with the second polysilicon field plate 23 in 13 structure of a upper field limiting ring, you can with
Realize that the terminal structure of this present invention projects the cross section of the area and entire terminal in the section that superposition is formed in vertical direction
Product is equal, and field plate also may make to project the cross-sectional area phase of the area and entire terminal in the section that superposition is formed in vertical direction
Deng to avoid silica to the shielding difference of interface charge and the mobile ion product introduced in processes such as technique manufacture, encapsulation
Gather in oxide layer or penetrates the problem of oxide layer enters silicon, field distribution is made to change.
The terminal for semiconductor power device of the present invention, by using the field plate of polysilicon field plate and Metal field plate
Group, and Metal field plate is electrically connected with field limiting ring and polysilicon field plate respectively so that main knot depletion region effectively broadens outward, to
It improves breakdown voltage and reduces the spike electric field at field plate edge.
In conclusion although the present invention is disclosed above with preferred embodiment, above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention is subject to the range that claim defines.
Claims (9)
1. a kind of terminal for semiconductor power device, which is characterized in that including：
Collector, base area, multiple field limiting rings and multiple field plate groups corresponding with the field limiting ring, the field plate group include mutual
The first polysilicon field plate and Metal field plate being electrically connected, first polysilicon field plate, the Metal field plate are sequentially located at institute
The top of field limiting ring is stated, first polysilicon field plate and the Metal field plate are electrically connected with the field limiting ring, the gold
Belong to field plate and covers first polysilicon field plate.
2. the terminal according to claim 1 for semiconductor power device, which is characterized in that described to be used for semiconductor work(
The terminal of rate device further includes the second polysilicon field plate, and second polysilicon field plate is located at the field limiting ring and the metal field
Between plate, and the Metal field plate only partly covers second polysilicon field plate.
3. the terminal according to claim 2 for semiconductor power device, which is characterized in that the second polysilicon field
Plate is located at same layer with first polysilicon field plate, and between second polysilicon field plate and first polysilicon field plate
Interval setting.
4. the terminal according to claim 2 for semiconductor power device, which is characterized in that the of the Metal field plate
A part of part covers second polysilicon field plate, and the first part of the Metal field plate is separate in the Metal field plate
The part of the junction of the Metal field plate and the field limiting ring.
5. the terminal according to claim 2 for semiconductor power device, which is characterized in that the Metal field plate covering
The half of second polysilicon field plate.
6. the terminal according to claim 1 for semiconductor power device, which is characterized in that the first polysilicon field
It is provided with field oxide between plate and the field limiting ring, the first via, first polysilicon are provided on the field oxide
Field plate is electrically connected by first via and the field limiting ring.
7. the terminal according to claim 6 for semiconductor power device, which is characterized in that the first polysilicon field
Between plate and the Metal field plate and the Metal field plate with do not covered by first polysilicon field plate and the field oxide
It is both provided with dielectric layer between the field limiting ring of lid, the second via is provided on the dielectric layer, the Metal field plate passes through described
Second via is electrically connected with the field limiting ring.
8. the terminal according to claim 7 for semiconductor power device, which is characterized in that also set on the dielectric layer
It is equipped with third via, first polysilicon field plate is electrically connected by the third via and the Metal field plate.
9. the terminal according to claim 6 for semiconductor power device, which is characterized in that second via and institute
State the same side that the first via is located at the field limiting ring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810873584.1A CN108767002B (en) | 2018-08-02 | 2018-08-02 | Terminal for semiconductor power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810873584.1A CN108767002B (en) | 2018-08-02 | 2018-08-02 | Terminal for semiconductor power device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108767002A true CN108767002A (en) | 2018-11-06 |
| CN108767002B CN108767002B (en) | 2024-03-26 |
Family
ID=63968866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810873584.1A Active CN108767002B (en) | 2018-08-02 | 2018-08-02 | Terminal for semiconductor power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108767002B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110854072A (en) * | 2020-01-07 | 2020-02-28 | 四川立泰电子有限公司 | Manufacturing process of low electromagnetic interference power device terminal structure |
| CN111554677A (en) * | 2020-05-06 | 2020-08-18 | 四川立泰电子有限公司 | Power device terminal structure with low electromagnetic interference |
| CN112271211A (en) * | 2020-11-02 | 2021-01-26 | 龙腾半导体股份有限公司 | Terminal structure of sectional type composite field plate |
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| CN208797006U (en) * | 2018-08-02 | 2019-04-26 | 盛廷微电子（深圳）有限公司 | A kind of terminal for semiconductor power device |
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| CN110854072A (en) * | 2020-01-07 | 2020-02-28 | 四川立泰电子有限公司 | Manufacturing process of low electromagnetic interference power device terminal structure |
| CN111554677A (en) * | 2020-05-06 | 2020-08-18 | 四川立泰电子有限公司 | Power device terminal structure with low electromagnetic interference |
| CN111554677B (en) * | 2020-05-06 | 2024-02-27 | 四川立泰电子有限公司 | Terminal structure of power device with low electromagnetic interference |
| CN112271211A (en) * | 2020-11-02 | 2021-01-26 | 龙腾半导体股份有限公司 | Terminal structure of sectional type composite field plate |
| CN112271211B (en) * | 2020-11-02 | 2024-01-09 | 龙腾半导体股份有限公司 | Terminal structure of sectional type composite field plate |
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