CN205159322U - MOSFET (metal -oxide -semiconductor field effect transistor) device - Google Patents
MOSFET (metal -oxide -semiconductor field effect transistor) device Download PDFInfo
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- CN205159322U CN205159322U CN201520955373.4U CN201520955373U CN205159322U CN 205159322 U CN205159322 U CN 205159322U CN 201520955373 U CN201520955373 U CN 201520955373U CN 205159322 U CN205159322 U CN 205159322U
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Abstract
The utility model relates to a metal oxide semiconductor field effect transistor (MOSFET), concretely relates to low -voltage metal oxide semiconductor field effect transistor, including a substrate, be equipped with the epitaxial layer on this substrate, be equipped with the oxide layer of ditch slot type on this epitaxial layer, pack polycrystalline silicon and form the polysilicon gate around the oxide layer of this ditch slot type, constitute the groove gate district, be equipped with boron phosphorus silicic acid layer in this oxide layer, this groove gate position is in the both sides of dopant well, the dopant well includes a plurality of first type dopant wells and a plurality of second type dopant well, and first type dopant well and second type dopant well contact each other, be equipped with grid metal level and source electrode metal level on the boron phosphorus silicic acid layer, this grid metal level passes boron phosphorus silicic acid layer and is connected with all polysilicon gates, constitutes the grid, this source electrode metal level passes boron phosphorus silicic acid layer and is connected with all first type dopant wells, constitutes the source electrode, grid and source electrode between be connected with zener diode, zener diode comprises a plurality of first type semiconductors and a plurality of second type semiconductor, zener diode is U type form, inlays between the dopant well to the by oxidation layer is insulating with the dopant well, the utility model discloses the impact that can protect the product not receive electric power or static simultaneously, can make the chip density maximize.
Description
Technical field
The utility model relates to a kind of metal oxide semiconductor field effect tube (MOSFET), is specifically related to low-voltage metal oxide semiconductor field effect tube.
Background technology
MOSFET (Metal-oxide-semiconductorfieldeffecttransistor, Metal-oxide-semicondutor field effect transistor) there is the advantages such as switching speed is fast, frequency performance good, input impedance is high, driving power is little, good temp characteristic, in the application of high frequency field widely.In technique, through improvement for many years, MOSFET product, from initial L-DMOS (transverse plane double diffusion) structure, progressively develops into VDMOS (fore-and-aft plane double diffusion) comparatively advanced at present and trenchMOS(groove grid) structure; But because MOSFET product size constantly reduces, the thickness of its grid oxic horizon, also in continuous decline, causes grid oxic horizon by ESD(static discharge) or the probability that punctures of system overvoltage also significantly improve.
From the beginning of this century, people increase its anti-static ability by introducing one group of Zener diode between the grid and source electrode of MOSFET; After this again through the part upgrading of zener diode structure, its anti-static ability is progressively strengthened.Zener diode builds separately after polysilicon gate is formed, and the existence of this diode makes MOSFET surface form certain difference in height.Under this configuration, reducing of cellular size becomes more difficult, and the lifting of cellular density is restricted.
Utility model content
The purpose of this utility model is for the deficiencies in the prior art, provides a kind of anti-static ability strong, the MOSFET element that cellular size is little, density is high.
To achieve these goals, the technical solution adopted in the utility model is:
A kind of MOSFET element, comprise a substrate, this substrate is provided with epitaxial loayer, and this epitaxial loayer is provided with the oxide layer of plough groove type, fills polysilicon and forms polysilicon gate, form groove grid region in the oxide layer of this plough groove type; This oxide layer is provided with boron phosphorus silicic acid layer; This groove grid region is positioned at the both sides of dopant well; Described dopant well comprises multiple first type dopant well and multiple Second-Type dopant well, and the first type dopant well and Second-Type dopant well contact with each other; Described boron phosphorus silicic acid layer is provided with gate metal layer and source metal; This gate metal layer is connected with all polysilicon gates through boron phosphorus silicic acid layer, forms grid; This source metal is connected with all first type dopant wells through boron phosphorus silicic acid layer, forms source electrode; Zener diode is connected with between described grid and source electrode; Described Zener diode is made up of multiple first type semiconductor and multiple Second-Type semiconductor; The U-shaped shape of described Zener diode, is embedded between dopant well, and is insulated by oxide layer and dopant well;
Further, described first type dopant well is N-type dopant well, and Second-Type dopant well is P type dopant well.
Further, the first type semiconductor of described Zener diode is N type semiconductor, and the Second-Type semiconductor of Zener diode is P type uniconductor;
Further, the N type semiconductor of described N-type dopant well and zener diode is formed by photoetching and arsenic doping technique.
Further, the P type semiconductor of described P type dopant well and zener diode is formed by boron ion doping technique.
Further, described substrate is N substrate.
Further, described epitaxial loayer is N-type epitaxy layer.
The beneficial effects of the utility model are:
The utility model is provided with a Zener diode between grid and source electrode, and this Zener diode is built-in, is configured under crystal column surface; This Zener diode can protect product by the impact of electric power or electrostatic, meanwhile, chip density can be made to maximize, and manufactures technique of the present utility model comparatively simply, can improving production efficiency reduce production cost.
Accompanying drawing explanation
Fig. 1 is cross sectional representation of the present utility model.
In figure: 1, N-type substrate 2, N-type epitaxy layer 3, oxide layer 4, P type dopant well 5, polysilicon gate 6, boron phosphorus silicic acid layer 7, gate metal layer 8, source metal 9, drain metal layer 10, N-type dopant well.
Embodiment
As shown in the figure, the utility model comprises drain metal layer 9, N-type substrate 1, N-type epitaxy layer 2, oxide layer 3, P type dopant well 4, polysilicon gate 5, N-type dopant well 10, boron phosphorus silicic acid layer 6, gate metal 7 and source metal 8 successively from lower floor to upper strata.
Described N-type epitaxy layer is made in described N-type substrate, forms one deck drain metal layer under this N-type substrate by metal deposition procedures, this N-type epitaxy layer utilizes Trench photolithography plate, forms groove and generate oxide layer through techniques such as photoetching/etchings.Different from general T rench photoetching, in this structure, Trench photolithography plate has been integrated in design and has been added new groove space, for forming built-in Zener diode in successive process.
By after the operation such as lower temperature deposition polysilicon (LPPOLY), poly photoetching/etching around described oxide layer, produce polysilicon gate; Described polysilicon gate and its surrounding oxidic layer form groove grid region; Both sides, groove grid region are doped well region, and this doped well region comprises multiple N-type dopant well and multiple P type dopant well, and N-type dopant well and P type dopant well contact with each other;
Described P type dopant well is formed through boron ion doping, form the P type semiconductor part belonging to Zener diode when forming P type dopant well simultaneously, described N-type dopant well utilizes NSD photolithography plate, through formation such as photoetching, arsenic ion injections, when forming N-type dopant well, form the N type semiconductor part belonging to Zener diode simultaneously.Oxide layer forms boron phosphorus silicic acid layer after carrying out boron phosphorus silicic acid (BPTEOS) deposition.
Above-mentioned boron phosphorus silicic acid layer forms gate metal layer, source metal by operations such as contact hole photoetching/etching work procedure, metal depositions, this gate metal layer does not contact with source metal, this gate metal layer is connected with polysilicon gate through boron phosphorus silicic acid layer, forms grid; Described source metal is connected with N-type dopant well through boron phosphorus silicic acid layer, forms source electrode.By finally completing after aluminium lamination photoetching and subsequent handling process after gate metal layer and source metal are formed.
The utility model only uses five layer photoetching plates (Trench photolithography plate, poly photolithography plate, NSD photolithography plate, contact hole photoetching, aluminium lamination photoetching) to complete, and decreases operation and improves production efficiency and reduce production cost.Zener diode of the present utility model can protect product not to be subject to the impact of electric power or electrostatic, meanwhile, chip density can be made to maximize.
Claims (7)
1. a MOSFET element, comprises a substrate, and this substrate is provided with epitaxial loayer, and this epitaxial loayer is provided with the oxide layer of plough groove type, fills polysilicon and forms polysilicon gate, form groove grid region in the oxide layer of this plough groove type; This oxide layer is provided with boron phosphorus silicic acid layer; This groove grid region is positioned at the both sides of dopant well; Described dopant well comprises multiple first type dopant well and multiple Second-Type dopant well, and the first type dopant well and Second-Type dopant well contact with each other; Described boron phosphorus silicic acid layer is provided with gate metal layer and source metal; This gate metal layer is connected with all polysilicon gates through boron phosphorus silicic acid layer, forms grid; This source metal is connected with all first type dopant wells through boron phosphorus silicic acid layer, forms source electrode; Zener diode is connected with between described grid and source electrode; Described Zener diode is made up of multiple first type semiconductor and multiple Second-Type semiconductor; The U-shaped shape of described Zener diode, is embedded between dopant well, and is insulated by oxide layer and dopant well.
2. a kind of MOSFET element according to claim 1, is characterized in that: described first type dopant well is N-type dopant well, and Second-Type dopant well is P type dopant well.
3. a kind of MOSFET element according to claim 1, is characterized in that: the first type semiconductor of Zener diode is N type semiconductor, and the Second-Type semiconductor of Zener diode is P type uniconductor.
4. a kind of MOSFET element according to claim 2, is characterized in that: the N type semiconductor part of described N-type dopant well and Zener diode is formed by photoetching and arsenic doping technique.
5. a kind of MOSFET element according to claim 2, is characterized in that: the P type semiconductor part of described P type dopant well and Zener diode is formed by boron ion doping technique.
6. a kind of MOSFET element according to claim 1, is characterized in that: described substrate is N-type substrate.
7. a kind of MOSFET element according to claim 1, is characterized in that: described epitaxial loayer is N-type epitaxy layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520955373.4U CN205159322U (en) | 2015-11-26 | 2015-11-26 | MOSFET (metal -oxide -semiconductor field effect transistor) device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520955373.4U CN205159322U (en) | 2015-11-26 | 2015-11-26 | MOSFET (metal -oxide -semiconductor field effect transistor) device |
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| Publication Number | Publication Date |
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| CN205159322U true CN205159322U (en) | 2016-04-13 |
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| CN201520955373.4U Active CN205159322U (en) | 2015-11-26 | 2015-11-26 | MOSFET (metal -oxide -semiconductor field effect transistor) device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024697A (en) * | 2016-07-12 | 2016-10-12 | 杭州士兰集成电路有限公司 | Trench power device and manufacturing method |
| CN106057681A (en) * | 2016-07-12 | 2016-10-26 | 杭州士兰集成电路有限公司 | Groove power device and manufacturing method thereof |
| CN106711235A (en) * | 2016-08-31 | 2017-05-24 | 佛山芯光半导体有限公司 | Novel polysilicon thin-film Zener diode and manufacturing method thereof |
| CN115172457A (en) * | 2022-09-06 | 2022-10-11 | 江苏应能微电子有限公司 | Gate-source electrode protection structure of silicon carbide semiconductor field effect transistor and preparation method |
| CN117878116A (en) * | 2024-03-12 | 2024-04-12 | 深圳市威兆半导体股份有限公司 | MOSFET device with electrostatic protection structure and preparation method thereof |
-
2015
- 2015-11-26 CN CN201520955373.4U patent/CN205159322U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024697A (en) * | 2016-07-12 | 2016-10-12 | 杭州士兰集成电路有限公司 | Trench power device and manufacturing method |
| CN106057681A (en) * | 2016-07-12 | 2016-10-26 | 杭州士兰集成电路有限公司 | Groove power device and manufacturing method thereof |
| CN106057681B (en) * | 2016-07-12 | 2023-03-31 | 杭州士兰集成电路有限公司 | Groove power device and manufacturing method |
| CN106024697B (en) * | 2016-07-12 | 2024-01-26 | 杭州士兰集成电路有限公司 | Trench power device and manufacturing method |
| CN106711235A (en) * | 2016-08-31 | 2017-05-24 | 佛山芯光半导体有限公司 | Novel polysilicon thin-film Zener diode and manufacturing method thereof |
| CN115172457A (en) * | 2022-09-06 | 2022-10-11 | 江苏应能微电子有限公司 | Gate-source electrode protection structure of silicon carbide semiconductor field effect transistor and preparation method |
| CN115172457B (en) * | 2022-09-06 | 2024-05-03 | 江苏应能微电子股份有限公司 | Gate-source protection structure of silicon carbide semiconductor field effect transistor and preparation method |
| CN117878116A (en) * | 2024-03-12 | 2024-04-12 | 深圳市威兆半导体股份有限公司 | MOSFET device with electrostatic protection structure and preparation method thereof |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Method of manufacturing grooves and protective rings of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device Effective date of registration: 20190730 Granted publication date: 20160413 Pledgee: Nanjing Bank Co., Ltd. Chengnan Branch Pledgor: The bright die semiconductor Co., Ltd in Nanjing Registration number: 2019320000381 |