CN103474427B - Integrated form one-way ultra-low capacitance TVS device and manufacture method thereof - Google Patents
Integrated form one-way ultra-low capacitance TVS device and manufacture method thereof Download PDFInfo
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Abstract
The invention provides a kind of integrated form one-way ultra-low capacitance TVS device and manufacture method thereof, method comprises: provide the first conductivity type substrate; First conductivity type substrate is formed the first conductive type epitaxial layer; The second conduction type buried regions is formed in first conductive type epitaxial layer; First conductive type epitaxial layer is formed the second conductive type epitaxial layer, form diode D2; Form the groove running through the second conductive type epitaxial layer, form first area, second area and the 3rd region; Form the first conduction type be connected with the first conductivity type substrate in first area to isolate; Form the second conductivity type implanted region isolating with the first conduction type and be connected in first area, form diode Z1; Form the first conductivity type implanted region in second area, form diode D1; Form the first metal wire connecting diode Z1 and diode D1, connect second metal wire of diode D1 and diode D2.Thus avoid encapsulating defect, improve device quality.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of integrated form one-way ultra-low capacitance TVS device and manufacture method thereof.
Background technology
A low di-cap is normally connected with a traditional voltage regulation type TVS diode by one-way ultra-low capacitance TVS device in the market, low di-cap parallel combination forms (see figure 1) with another one again, from the I-V curve of power Vcc GND over the ground, forward and reverse characteristic is still equivalent to a general-purpose diode, but the electric capacity of system line is well below the electric capacity of the single general T VS diode of identical voltage.
The one-way ultra-low capacitance TVS device combined, the capacitance C of its power Vcc GND over the ground
tcan be expressed as:
Here C
d1and C
d2all less, C
z1an order of magnitude larger than the above two, so after diode D1 and diode Z1 series connection, total series capacitance is equal to the electric capacity of diode D1 substantially.
When power Vcc adds positive potential, when ground GND adds negative potential: because diode D2 puncture voltage is higher, diode Z1 puncture voltage is lower, so diode Z1 takes the lead in puncturing, the reverse breakdown voltage of power Vcc GND over the ground can be expressed as:
V
BR=Vf
D1+V
Z1
Wherein, Vf
d1for the forward voltage drop of diode D1.
When power Vcc adds negative potential, when ground GND adds positive potential: because diode D1 puncture voltage is higher, electric current is preferentially through the forward of diode D2, and the forward voltage drop of power Vcc GND over the ground can be expressed as:
Vf=Vf
D2
The forward and reverse characteristic of the visible one-way ultra-low capacitance TVS device combined is equivalent to a general-purpose diode substantially, and its reverse breakdown voltage mainly controls by the puncture voltage of diode Z1; Electric capacity is mainly by C
d1and C
d2control, so in order to realize ultra-low capacitance, reality is exactly reduce C
d1and C
d2; Simultaneously the positive and negative direction ESD ability reality of power Vcc GND over the ground is also be equal to the forward ESD ability of D1, D2 two diodes respectively (reverse breakdown voltage of diode Z1 is lower, general between 3.3-7.0V, its reverse ESD ability is very high, can not consider).So in order to realize high ESD ability, reality is exactly improve the forward ESD ability of D1, D2 two diodes.
Because above-mentioned one-way ultra-low capacitance TVS device is combined by discrete device, there is the certain defect in encapsulation.Therefore, a kind of integrated form one-way ultra-low capacitance TVS device is provided to become this area problem demanding prompt solution.
Summary of the invention
The object of the present invention is to provide a kind of integrated form one-way ultra-low capacitance TVS device and manufacture method thereof, combined by discrete device to solve one-way ultra-low capacitance TVS device of the prior art, there is the problem of the certain defect in encapsulation.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of integrated form one-way ultra-low capacitance TVS device, the manufacture method of described integrated form one-way ultra-low capacitance TVS device comprises:
First conductivity type substrate is provided;
Described first conductivity type substrate forms the first conductive type epitaxial layer;
The second conduction type buried regions is formed in described first conductive type epitaxial layer;
Described first conductive type epitaxial layer forms the second conductive type epitaxial layer, and described first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Form groove, described groove runs through described second conductive type epitaxial layer, and in described second conductive type epitaxial layer, form first area, second area and the 3rd region;
In described first area, form the first conduction type isolation, and described first conduction type isolation is connected with described first conductivity type substrate;
In described first area, form the second conductivity type implanted region, described second conductivity type implanted region isolates with described first conduction type and is connected, and described second conductivity type implanted region and described first conduction type are isolated and formed diode Z1;
In described second area, form the first conductivity type implanted region, described first conductivity type implanted region and the second conductive type epitaxial layer form diode D1;
Form the first metal wire and the second metal wire, wherein, described first metal wire connects described diode Z1 and diode D1, and described second metal wire connects described diode D1 and diode D2.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the degree of depth of described groove is 10 μm ~ 20 μm, cross-sectional width is 1.5 μm ~ 3.0 μm.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, after trench formation, form the first conduction type isolation in described first area before, polysilicon is filled in the trench.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, form the second conductivity type implanted region in described first area while, in described second area and the 3rd region, all form the second conductivity type implanted region, the second conductivity type implanted region formed in described second area and the 3rd region is all as ohmic contact layer.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the second conductivity type implanted region formed in described second area is interdigitated electrode structure structure.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the first conductivity type implanted region formed in described second area is interdigitated electrode structure structure.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the comb of the second conductivity type implanted region of the interdigitated electrode structure structure formed in described second area is interlaced with the comb of the first conductivity type implanted region of the interdigitated electrode structure structure formed in described second area.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, described first conduction type is P type, described second conduction type is N-type; Or described first conduction type is N-type, described second conduction type is P type.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the resistivity of described first conductivity type substrate is 0.005 Ω .cm ~ 0.2 Ω .cm.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the resistivity of described first conductive type epitaxial layer is 2.0 Ω .cm ~ 4.0 Ω .cm, and the thickness of described first conductive type epitaxial layer is 6.0 μm ~ 14.0 μm.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, in described first conductive type epitaxial layer, form the second conduction type buried regions by following technique:
In described first conductive type epitaxial layer, inject antimony ion, the implantation dosage of described antimony ion is 2.0E15 ~ 6.0E15;
Perform annealing process to described antimony ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the resistivity of described second conductive type epitaxial layer is 25 Ω .cm ~ 35 Ω .cm, and the thickness of described second conductive type epitaxial layer is 6.0 μm ~ 12.0 μm.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, in described first area, form the first conduction type isolation by following technique:
In described first area, inject boron ion, the implantation dosage of described boron ion is 2.0E14 ~ 4.5E15;
Perform annealing process to described boron ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, in described first area, the second conductivity type implanted region is formed by following technique:
In described first area, inject phosphonium ion, the implantation dosage of described phosphonium ion is 1.0E15 ~ 1.0E16;
First time annealing process is performed to described phosphonium ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s;
Perform second time annealing process to described phosphonium ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the puncture voltage of described diode Z1 is 3.3V ~ 7.0V.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, in described second area, the first conductivity type implanted region is formed by following technique:
In described second area, inject boron ion, the implantation dosage of described boron ion is 1.0E15 ~ 1.0E16;
First time annealing process is performed to described boron ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s;
Perform second time annealing process to described boron ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, described first conductivity type substrate is held with being, described second metal wire is connected with power end.
The present invention also provides a kind of integrated form one-way ultra-low capacitance TVS device, and described integrated form one-way ultra-low capacitance TVS device comprises:
First conductivity type substrate;
Be formed at the first conductive type epitaxial layer in described first conductivity type substrate;
Be formed at the second conduction type buried regions in described first conductive type epitaxial layer;
Be formed at the second conductive type epitaxial layer on described first conductive type epitaxial layer, described first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Groove, described groove runs through described second conductive type epitaxial layer, and in described second conductive type epitaxial layer, define first area, second area and the 3rd region;
Be formed at the first conduction type isolation in described first area, described first conduction type isolation is connected with described first conductivity type substrate;
Be formed at the second conductivity type implanted region in described first area, described second conductivity type implanted region isolates with described first conduction type and is connected, and described second conductivity type implanted region and described first conduction type are isolated and formed diode Z1;
Be formed at the first conductivity type implanted region in described second area, described first conductivity type implanted region and the second conductive type epitaxial layer form diode D1; And
Connect first metal wire of described diode Z1 and diode D1, connect second metal wire of described diode D1 and diode D2.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the degree of depth of described groove is 10 μm ~ 20 μm, cross-sectional width is 1.5 μm ~ 3.0 μm.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, be filled with polysilicon in described groove, define isolation structure.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, all be formed with the second conductivity type implanted region in described second area and the 3rd region, the second conductivity type implanted region formed in described second area and the 3rd region is all as ohmic contact layer.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the second conductivity type implanted region formed in described second area is interdigitated electrode structure structure.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the first conductivity type implanted region formed in described second area is interdigitated electrode structure structure.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the comb of the second conductivity type implanted region of the interdigitated electrode structure structure formed in described second area is interlaced with the comb of the first conductivity type implanted region of the interdigitated electrode structure structure formed in described second area.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, described first conduction type is P type, described second conduction type is N-type; Or described first conduction type is N-type, described second conduction type is P type.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the resistivity of described first conductivity type substrate is 0.005 Ω .cm ~ 0.2 Ω .cm.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the resistivity of described first conductive type epitaxial layer is 2.0 Ω .cm ~ 4.0 Ω .cm, and the thickness of described first conductive type epitaxial layer is 6.0 μm ~ 14.0 μm.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the resistivity of described second conductive type epitaxial layer is 25 Ω .cm ~ 35 Ω .cm, and the thickness of described second conductive type epitaxial layer is 6.0 μm ~ 12.0 μm.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the puncture voltage of described diode Z1 is 3.3V ~ 7.0V.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, described first conductivity type substrate is held with being, described second metal wire is connected with power end.
In integrated form one-way ultra-low capacitance TVS device provided by the invention and manufacture method thereof, the one-way ultra-low capacitance TVS device formed is integrated structure, thus avoids the defect in encapsulation, improves device quality.
Accompanying drawing explanation
Fig. 1 is the one-way ultra-low capacitance TVS device circuit diagram combined;
Fig. 2 ~ Figure 12 is the generalized section of the device that the manufacture method of the integrated form one-way ultra-low capacitance TVS device of the embodiment of the present invention one is formed;
Figure 13 ~ Figure 23 is the generalized section of the device that the manufacture method of the integrated form one-way ultra-low capacitance TVS device of the embodiment of the present invention two is formed.
Embodiment
The integrated form one-way ultra-low capacitance TVS device proposed the present invention below in conjunction with the drawings and specific embodiments and manufacture method thereof are described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
[embodiment one]
Present embodiments provide a kind of manufacture method of integrated form one-way ultra-low capacitance TVS device, comprising:
S10: the first conductivity type substrate is provided;
S11: form the first conductive type epitaxial layer in described first conductivity type substrate;
S12: form the second conduction type buried regions in described first conductive type epitaxial layer;
S13: form the second conductive type epitaxial layer on described first conductive type epitaxial layer, described first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
S14: form groove, described groove runs through described second conductive type epitaxial layer, and forms first area, second area and the 3rd region in described second conductive type epitaxial layer;
S15: form the first conduction type isolation in described first area, and described first conduction type isolation is connected with described first conductivity type substrate;
S16: form the second conductivity type implanted region in described first area, described second conductivity type implanted region isolates with described first conduction type and is connected, and described second conductivity type implanted region and described first conduction type are isolated and formed diode Z1;
S17: form the first conductivity type implanted region in described second area, described first conductivity type implanted region and the second conductive type epitaxial layer form diode D1;
S18: form the first metal wire and the second metal wire, wherein, described first metal wire connects described diode Z1 and diode D1, and described second metal wire connects described diode D1 and diode D2.
Concrete, please refer to Fig. 2 ~ 12, the generalized section of the device that the manufacture method of its integrated form one-way ultra-low capacitance TVS device being the embodiment of the present invention one is formed.
As shown in Figure 2, provide the first conductivity type substrate 10, described first conductivity type substrate 10 can be P type substrate, also can be N-type substrate.In the present embodiment, described first conduction type is P type, and follow-up the second conduction type related to is N-type.In other embodiments of the application, also can be the first conduction type be N-type, the second conduction type be P type.The resistivity of described first conductivity type substrate 10 is 0.005 Ω .cm ~ 0.2 Ω .cm.
Then, as shown in Figure 3, described first conductivity type substrate 10 forms the first conductive type epitaxial layer 11, described first conductive type epitaxial layer 11 is P type epitaxial loayer, and it generates by chemical vapor deposition method.Preferably, the resistivity of described first conductive type epitaxial layer 11 is 2.0 Ω .cm ~ 4.0 Ω .cm, and the thickness of described first conductive type epitaxial layer 11 is 6.0 μm ~ 14.0 μm.
As shown in Figure 4, in described first conductive type epitaxial layer 11, form the second conduction type buried regions 12, described second conduction type buried regions 12 is n type buried layer.Concrete, form described second conduction type buried regions 12 by following technique: in described first conductive type epitaxial layer 11, inject antimony ion, the implantation dosage of described antimony ion is 2.0E15 ~ 6.0E15; Perform annealing process to described antimony ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.
As shown in Figure 5, described first conductive type epitaxial layer 11 forms the second conductive type epitaxial layer 13, described second conductive type epitaxial layer 13 is N-type epitaxy layer, and described first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13 form diode D2.Preferably, the resistivity of described second conductive type epitaxial layer 13 is 25 Ω .cm ~ 35 Ω .cm, and the thickness of described second conductive type epitaxial layer 13 is 6.0 μm ~ 12.0 μm.Wherein, the capacitance size of described diode D2 is achieved by the area and/or resistivity adjusting described first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13, repeats no more this application.
Then, as shown in Figure 6, form groove 14, described groove 14 runs through described second conductive type epitaxial layer 13, and forms first area A, second area B and the 3rd region C in described second conductive type epitaxial layer 13.Preferably, the degree of depth of described groove 14 is 10 μm ~ 20 μm, cross-sectional width is 1.5 μm ~ 3.0 μm.In the present embodiment, adopt groove to isolate, not only technique is simple, does not have ghost effect, especially multichannel structure between each diode also can guaranteeing follow-up formation, thus the reliability that improve formed integrated form one-way ultra-low capacitance TVS device.In addition, described groove 14 belongs to deep groove structure, and the junction area of diode D2 formed thus only has the contact zone, bottom of the first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13, so area is less, corresponding electric capacity is also less.
Then, as shown in Figure 7, in described groove 14, fill polysilicon, form isolation structure 15, namely described isolation structure 15 runs through described second conductive type epitaxial layer 13.
Then, as shown in Figure 8, form the first conduction type isolation 16 in described first area A, described first conduction type isolation 16 is the isolation of P type, and described first conduction type isolation 16 is connected with described first conductivity type substrate 10.Concrete, form the first conduction type isolation 16 by following technique: in described first area A, inject boron ion, the implantation dosage of described boron ion is 2.0E14 ~ 4.5E15; Perform annealing process to described boron ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.
As shown in Figure 9, the second conductivity type implanted region 17a is formed in described first area A, described second conductivity type implanted region 17a is N-type injection region, described second conductivity type implanted region 17a isolates 16 with described first conduction type and is connected, and described second conductivity type implanted region 17a and described first conduction type are isolated 16 and formed diode Z1.Further, described second conductivity type implanted region 17a surrounds described first conduction type isolation 16, thus avoids diode Z1 to leak electricity and guarantee the uniformity of diode Z1 voltage.Concrete, described second conductivity type implanted region 17a is formed by following technique: in described first area A, inject phosphonium ion, and the implantation dosage of described phosphonium ion is 1.0E15 ~ 1.0E16; First time annealing process is performed to described phosphonium ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s; Perform second time annealing process to described phosphonium ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.The diode Z1 formed by above-mentioned technique is the low pressure diode of 3.3V ~ 7.0V.Wherein, annealing process also can be called high temperature rapid thermal annealing technique for the first time, its objective is the phosphorus impurities activating all injections, while guaranteeing to form good ohmic contact, also reduces the reverse leakage current of diode Z1; Second time annealing process also can be called low temperature furnace anneal process, its objective is the junction depth and puncture voltage that control diode Z1, guarantees that puncture voltage is at about 3.3V-7.0V.
In the present embodiment, form the second conductivity type implanted region 17a in described first area A while, the second conductivity type implanted region is all formed in described second area B and the 3rd region C, namely in described second area B, form the second conductivity type implanted region 17b, in the 3rd region C, form the second conductivity type implanted region 17c, described second conductivity type implanted region 17b and the second conductivity type implanted region 17c is all as ohmic contact layer.
Then, as shown in Figure 10, form the first conductivity type implanted region 18 in described second area B, described first conductivity type implanted region 18 and the second conductive type epitaxial layer 13 form diode D1.Concrete, form the first conductivity type implanted region 18 by following technique: in described second area B, inject boron ion, the implantation dosage of described boron ion is 1.0E15 ~ 1.0E16; First time annealing process is performed to described boron ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s; Perform second time annealing process to described boron ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.Wherein, annealing process also can be called high temperature rapid thermal annealing technique for the first time, its objective is the boron impurity activating all injections, guarantees to form good ohmic contact; Second time annealing process also can be called low temperature furnace anneal process, its objective is the junction depth controlling diode D1, guarantees that junction depth is at 0.5 μm about-1.0 μm.
Then, as shown in figure 12, form the first metal wire 20a and the second metal wire 20b, wherein, described first metal wire 20a connects described diode Z1 and diode D1, and described second metal wire 20b connects described diode D1 and diode D2.Concrete, can with reference to Figure 11, described second conductive type epitaxial layer 13 forms dielectric layer 19, and described dielectric layer 19 exposes diode Z1, diode D1 and diode D2; Then, with reference to Figure 12, by deposited metal, the first metal wire 20a and the second metal wire 20b can be formed.
In the present embodiment, described first conductivity type substrate 10 is held with being, described second metal wire 20b is connected with power end.Namely the first conductivity type substrate 10 is directly as the electrode of ground connection GND, thus do not need to draw ground connection GND electrode, so not only can reduce the size of chip, meet the encapsulation of more small size, during encapsulation, the first conductivity type substrate 10 is directly drawn as GND electrode in addition, can reduce by 1 wires, greatly reduce packaging cost.
Please continue to refer to Figure 12, define following integrated form one-way ultra-low capacitance TVS device by the manufacture method of above-mentioned integrated form one-way ultra-low capacitance TVS device, specifically comprise:
First conductivity type substrate 10;
Be formed at the first conductive type epitaxial layer 11 in described first conductivity type substrate 10;
Be formed at the second conduction type buried regions 12 in described first conductive type epitaxial layer 11;
Be formed at the second conductive type epitaxial layer 13 on described first conductive type epitaxial layer 11, described first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13 form diode D2;
Groove, described groove runs through described second conductive type epitaxial layer 13, and defines first area A, second area B and the 3rd region C in described second conductive type epitaxial layer 13;
Be formed at the first conduction type isolation 16 in described first area A, described first conduction type isolation 16 is connected with described first conductivity type substrate 10;
Be formed at the second conductivity type implanted region 17a in described first area A, described second conductivity type implanted region 17a isolates 16 with described first conduction type and is connected, and described second conductivity type implanted region 17a and described first conduction type are isolated 16 and formed diode Z1;
Be formed at the first conductivity type implanted region 18 in described second area B, described first conductivity type implanted region 18 and the second conductive type epitaxial layer 13 form diode D1; And
Connect the first metal wire 20a of described diode Z1 and diode D1, connect the second metal wire 20b of described diode D1 and diode D2.
In the integrated form one-way ultra-low capacitance TVS device provided at the present embodiment and manufacture method thereof, the one-way ultra-low capacitance TVS device formed is integrated structure, thus avoids the defect in encapsulation, improves device quality.
[embodiment two]
Please refer to Figure 13 ~ Figure 23, the generalized section of the device that the manufacture method of its integrated form one-way ultra-low capacitance TVS device being the embodiment of the present invention two is formed.
With the difference of embodiment one, the present embodiment two is that the second conductivity type implanted region formed in described second area is interdigitated electrode structure structure; Meanwhile, the first conductivity type implanted region formed in described second area is also interdigitated electrode structure structure.Further, the comb of the second conductivity type implanted region of the interdigitated electrode structure structure formed in described second area is interlaced with the comb of the first conductivity type implanted region of the interdigitated electrode structure structure formed in described second area.Wherein, the comb quantity of the second conductivity type implanted region of the interdigitated electrode structure structure formed in described second area and the comb quantity of the first conductivity type implanted region of interdigitated electrode structure structure formed in described second area are determined according to the electric capacity of diode D1 and ESD Capability Requirement.The benefit adopting comb structure is electric current lateral flow, and ESD determines primarily of the girth of comb, and electric capacity is determined by the area of comb.Because the area of comb structure is less, and girth is comparatively large, so can guarantee high ESD and low electric capacity.
Concrete, as shown in figure 13, provide the first conductivity type substrate 30, described first conductivity type substrate 30 can be P type substrate, also can be N-type substrate.In the present embodiment, described first conduction type is P type, and follow-up the second conduction type related to is N-type.In other embodiments of the application, also can be the first conduction type be N-type, the second conduction type be P type.The resistivity of described first conductivity type substrate 30 is 0.005 Ω .cm ~ 0.2 Ω .cm.
Then, as shown in figure 14, described first conductivity type substrate 30 forms the first conductive type epitaxial layer 31, described first conductive type epitaxial layer 31 is P type epitaxial loayer, and it generates by chemical vapor deposition method.Preferably, the resistivity of described first conductive type epitaxial layer 31 is 2.0 Ω .cm ~ 4.0 Ω .cm, and the thickness of described first conductive type epitaxial layer 31 is 6.0 μm ~ 14.0 μm.
As shown in figure 15, in described first conductive type epitaxial layer 31, form the second conduction type buried regions 32, described second conduction type buried regions 32 is n type buried layer.Concrete, form described second conduction type buried regions 32 by following technique: in described first conductive type epitaxial layer 31, inject antimony ion, the implantation dosage of described antimony ion is 2.0E15 ~ 6.0E15; Perform annealing process to described antimony ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.
As shown in figure 16, described first conductive type epitaxial layer 31 forms the second conductive type epitaxial layer 33, described second conductive type epitaxial layer 33 is N-type epitaxy layer, and described first conductive type epitaxial layer 31 and the second conductive type epitaxial layer 33 form diode D2.Preferably, the resistivity of described second conductive type epitaxial layer 33 is 25 Ω .cm ~ 35 Ω .cm, and the thickness of described second conductive type epitaxial layer 33 is 6.0 μm ~ 12.0 μm.Wherein, the capacitance size of described diode D2 is achieved by the area and/or resistivity adjusting described first conductive type epitaxial layer 31 and the second conductive type epitaxial layer 33, repeats no more this application.
Then, as shown in figure 17, form groove 34, described groove 34 runs through described second conductive type epitaxial layer 33, and forms first area D, second area E and the 3rd region F in described second conductive type epitaxial layer 33.Preferably, the degree of depth of described groove 34 is 10 μm ~ 20 μm, cross-sectional width is 1.5 μm ~ 3.0 μm.In the present embodiment, adopt groove to isolate, not only technique is simple, does not have ghost effect, especially multichannel structure between each diode also can guaranteeing follow-up formation, thus the reliability that improve formed integrated form one-way ultra-low capacitance TVS device.In addition, described groove 34 belongs to deep groove structure, and the junction area of diode D2 formed thus only has the contact zone, bottom of the first conductive type epitaxial layer 31 and the second conductive type epitaxial layer 33, so area is less, corresponding electric capacity is also less.
Then, as shown in figure 18, in described groove 34, fill polysilicon, form isolation structure 35, namely described isolation structure 35 runs through described second conductive type epitaxial layer 33.
Then, as shown in figure 19, form the first conduction type isolation 36 in described first area D, described first conduction type isolation 36 is the isolation of P type, and described first conduction type isolation 36 is connected with described first conductivity type substrate 30.Concrete, form the first conduction type isolation 36 by following technique: in described first area D, inject boron ion, the implantation dosage of described boron ion is 2.0E14 ~ 4.5E15; Perform annealing process to described boron ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.
As shown in figure 20, the second conductivity type implanted region 37a is formed in described first area D, described second conductivity type implanted region 37a is N-type injection region, described second conductivity type implanted region 37a isolates 36 with described first conduction type and is connected, and described second conductivity type implanted region 37a and described first conduction type are isolated 36 and formed diode Z1.Further, described second conductivity type implanted region 37a surrounds described first conduction type isolation 36, thus avoids diode Z1 to leak electricity and guarantee the uniformity of diode Z1 voltage.Concrete, described second conductivity type implanted region 37a is formed by following technique: in described first area D, inject phosphonium ion, and the implantation dosage of described phosphonium ion is 1.0E15 ~ 1.0E16; First time annealing process is performed to described phosphonium ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s; Perform second time annealing process to described phosphonium ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.The diode Z1 formed by above-mentioned technique is the low pressure diode of 3.3V ~ 7.0V.Wherein, annealing process also can be called high temperature rapid thermal annealing technique for the first time, its objective is the phosphorus impurities activating all injections, while guaranteeing to form good ohmic contact, also reduces the reverse leakage current of diode Z1; Second time annealing process also can be called low temperature furnace anneal process, its objective is the junction depth and puncture voltage that control diode Z1, guarantees that puncture voltage is at about 3.3V-7.0V.
In the present embodiment, form the second conductivity type implanted region 37a in described first area D while, in described second area E and the 3rd region F, all form the second conductivity type implanted region.Wherein, the second conductivity type implanted region formed in described second area E is interdigitated electrode structure structure, and the second conductivity type implanted region namely formed in described second area E comprises comb 37b, 37c, 37d, 37e; In the 3rd region F, form the second conductivity type implanted region 37f, described comb 37b, 37c, 37d, 37e and the second conductivity type implanted region 37f are all as ohmic contact layer.
Then, as shown in figure 21, in described second area E, form the first conductivity type implanted region, described first conductivity type implanted region and the second conductive type epitaxial layer 33 form diode D1.In the present embodiment, the first conductivity type implanted region formed in described second area E is also interdigitated electrode structure structure, and the first conductivity type implanted region namely formed in described second area E comprises comb 38a, 38b, 38c.
Concrete, form the first conductivity type implanted region by following technique: in described second area E, inject boron ion, the implantation dosage of described boron ion is 1.0E15 ~ 1.0E16; First time annealing process is performed to described boron ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s; Perform second time annealing process to described boron ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.Wherein, annealing process also can be called high temperature rapid thermal annealing technique for the first time, its objective is the boron impurity activating all injections, guarantees to form good ohmic contact; Second time annealing process also can be called low temperature furnace anneal process, its objective is the junction depth controlling diode D1, guarantees that junction depth is at 0.5 μm about-1.0 μm.
Further, the comb of the second conductivity type implanted region of the interdigitated electrode structure structure formed in described second area E is interlaced with the comb of the first conductivity type implanted region of the interdigitated electrode structure structure formed in described second area E.Namely comb 37b, 37c, 37d, 37e and comb 38a, 38b, 38c staggered, be easy to the lateral flow of electric current thus.
Then, as shown in figure 23, form the first metal wire 40a and the second metal wire 40b, wherein, described first metal wire 40a connects described diode Z1 and diode D1, and described second metal wire 40b connects described diode D1 and diode D2.Concrete, can with reference to Figure 22, described second conductive type epitaxial layer 33 forms dielectric layer 39, and described dielectric layer 39 exposes diode Z1, diode D1 and diode D2; Then, with reference to Figure 23, by deposited metal, the first metal wire 40a and the second metal wire 40b can be formed.
In the present embodiment, described first conductivity type substrate 30 is held with being, described second metal wire 40b is connected with power end.Namely the first conductivity type substrate 30 is directly as the electrode of ground connection GND, thus do not need to draw ground connection GND electrode, so not only can reduce the size of chip, meet the encapsulation of more small size, during encapsulation, the first conductivity type substrate 30 is directly drawn as GND electrode in addition, can reduce by 1 wires, greatly reduce packaging cost.
Please continue to refer to Figure 23, define following integrated form one-way ultra-low capacitance TVS device by the manufacture method of above-mentioned integrated form one-way ultra-low capacitance TVS device, specifically comprise:
First conductivity type substrate 30;
Be formed at the first conductive type epitaxial layer 31 in described first conductivity type substrate 30;
Be formed at the second conduction type buried regions 32 in described first conductive type epitaxial layer 31;
Be formed at the second conductive type epitaxial layer 33 on described first conductive type epitaxial layer 31, described first conductive type epitaxial layer 31 and the second conductive type epitaxial layer 33 form diode D2;
Groove, described groove runs through described second conductive type epitaxial layer 33, and defines first area D, second area E and the 3rd region F in described second conductive type epitaxial layer 33;
Be formed at the first conduction type isolation 36 in described first area D, described first conduction type isolation 36 is connected with described first conductivity type substrate 30;
Be formed at the second conductivity type implanted region 37a in described first area D, described second conductivity type implanted region 37a isolates 36 with described first conduction type and is connected, and described second conductivity type implanted region 37a and described first conduction type are isolated 36 and formed diode Z1;
Be formed at the first conductivity type implanted region in described second area E, described first conductivity type implanted region and the second conductive type epitaxial layer 33 form diode D1; And
Connect the first metal wire 40a of described diode Z1 and diode D1, connect the second metal wire 40b of described diode D1 and diode D2.
Wherein, the second conductivity type implanted region formed in described second area E is interdigitated electrode structure structure; Meanwhile, the first conductivity type implanted region formed in described second area E is also interdigitated electrode structure structure.
In the integrated form one-way ultra-low capacitance TVS device provided at the present embodiment and manufacture method thereof, the one-way ultra-low capacitance TVS device formed is integrated structure, thus avoids the defect in encapsulation, improves device quality.
Foregoing description is only the description to present pre-ferred embodiments, and any restriction not to the scope of the invention, this structure may also extend into the one-way low-capacitance product of multiple passage in addition.Any change that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (30)
1. a manufacture method for integrated form one-way ultra-low capacitance TVS device, is characterized in that, comprising:
First conductivity type substrate is provided;
Described first conductivity type substrate forms the first conductive type epitaxial layer;
The second conduction type buried regions is formed in described first conductive type epitaxial layer;
Described first conductive type epitaxial layer forms the second conductive type epitaxial layer, and described first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Form groove, described groove runs through described second conductive type epitaxial layer, and in described second conductive type epitaxial layer, form first area, second area and the 3rd region;
In described first area, form the first conduction type isolation, and described first conduction type isolation is connected with described first conductivity type substrate;
In described first area, form the second conductivity type implanted region, described second conductivity type implanted region isolates with described first conduction type and is connected, and described second conductivity type implanted region and described first conduction type are isolated and formed diode Z1;
In described second area, form the first conductivity type implanted region, described first conductivity type implanted region and the second conductive type epitaxial layer form diode D1;
Form the first metal wire and the second metal wire, wherein, described first metal wire connects described diode Z1 and diode D1, and described second metal wire connects described diode D1 and diode D2.
2. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 1, is characterized in that, the degree of depth of described groove is 10 μm ~ 20 μm, cross-sectional width is 1.5 μm ~ 3.0 μm.
3. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 2, is characterized in that, after trench formation, before forming the first conduction type isolation, fills polysilicon in the trench in described first area.
4. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 1, it is characterized in that, form the second conductivity type implanted region in described first area while, in described second area and the 3rd region, all form the second conductivity type implanted region, the second conductivity type implanted region formed in described second area and the 3rd region is all as ohmic contact layer.
5. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 4, it is characterized in that, the second conductivity type implanted region formed in described second area is interdigitated electrode structure structure.
6. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 5, it is characterized in that, the first conductivity type implanted region formed in described second area is interdigitated electrode structure structure.
7. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 6, it is characterized in that, the comb of the second conductivity type implanted region of the interdigitated electrode structure structure formed in described second area is interlaced with the comb of the first conductivity type implanted region of the interdigitated electrode structure structure formed in described second area.
8. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 1, is characterized in that, described first conduction type is P type, described second conduction type is N-type; Or described first conduction type is N-type, described second conduction type is P type.
9. the manufacture method of the integrated form one-way ultra-low capacitance TVS device according to any one of claim 1 ~ 8, is characterized in that, the resistivity of described first conductivity type substrate is 0.005 Ω .cm ~ 0.2 Ω .cm.
10. the manufacture method of the integrated form one-way ultra-low capacitance TVS device according to any one of claim 1 ~ 8, it is characterized in that, the resistivity of described first conductive type epitaxial layer is 2.0 Ω .cm ~ 4.0 Ω .cm, and the thickness of described first conductive type epitaxial layer is 6.0 μm ~ 14.0 μm.
The manufacture method of 11. integrated form one-way ultra-low capacitance TVS device according to any one of claim 1 ~ 8, is characterized in that, form the second conduction type buried regions by following technique in described first conductive type epitaxial layer:
In described first conductive type epitaxial layer, inject antimony ion, the implantation dosage of described antimony ion is 2.0E15 ~ 6.0E15;
Perform annealing process to described antimony ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.
The manufacture method of 12. integrated form one-way ultra-low capacitance TVS device according to any one of claim 1 ~ 8, it is characterized in that, the resistivity of described second conductive type epitaxial layer is 25 Ω .cm ~ 35 Ω .cm, and the thickness of described second conductive type epitaxial layer is 6.0 μm ~ 12.0 μm.
The manufacture method of 13. integrated form one-way ultra-low capacitance TVS device according to any one of claim 1 ~ 8, is characterized in that, forms the first conduction type isolation by following technique in described first area:
In described first area, inject boron ion, the implantation dosage of described boron ion is 2.0E14 ~ 4.5E15;
Perform annealing process to described boron ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.
The manufacture method of 14. integrated form one-way ultra-low capacitance TVS device according to any one of claim 1 ~ 8, is characterized in that, form the second conductivity type implanted region by following technique in described first area:
In described first area, inject phosphonium ion, the implantation dosage of described phosphonium ion is 1.0E15 ~ 1.0E16;
First time annealing process is performed to described phosphonium ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s;
Perform second time annealing process to described phosphonium ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.
The manufacture method of 15. integrated form one-way ultra-low capacitance TVS device as claimed in claim 14, is characterized in that, the puncture voltage of described diode Z1 is 3.3V ~ 7.0V.
The manufacture method of 16. integrated form one-way ultra-low capacitance TVS device according to any one of claim 1 ~ 8, is characterized in that, form the first conductivity type implanted region by following technique in described second area:
In described second area, inject boron ion, the implantation dosage of described boron ion is 1.0E15 ~ 1.0E16;
First time annealing process is performed to described boron ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s;
Perform second time annealing process to described boron ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.
The manufacture method of 17. integrated form one-way ultra-low capacitance TVS device according to any one of claim 1 ~ 8, it is characterized in that, described first conductivity type substrate is held with being, described second metal wire is connected with power end.
18. 1 kinds of integrated form one-way ultra-low capacitance TVS device, is characterized in that, comprising:
First conductivity type substrate;
Be formed at the first conductive type epitaxial layer in described first conductivity type substrate;
Be formed at the second conduction type buried regions in described first conductive type epitaxial layer;
Be formed at the second conductive type epitaxial layer on described first conductive type epitaxial layer, described first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Groove, described groove runs through described second conductive type epitaxial layer, and in described second conductive type epitaxial layer, define first area, second area and the 3rd region;
Be formed at the first conduction type isolation in described first area, described first conduction type isolation is connected with described first conductivity type substrate;
Be formed at the second conductivity type implanted region in described first area, described second conductivity type implanted region isolates with described first conduction type and is connected, and described second conductivity type implanted region and described first conduction type are isolated and formed diode Z1;
Be formed at the first conductivity type implanted region in described second area, described first conductivity type implanted region and the second conductive type epitaxial layer form diode D1; And
Connect first metal wire of described diode Z1 and diode D1, connect second metal wire of described diode D1 and diode D2.
19. integrated form one-way ultra-low capacitance TVS device as claimed in claim 18, is characterized in that, the degree of depth of described groove is 10 μm ~ 20 μm, cross-sectional width is 1.5 μm ~ 3.0 μm.
20. integrated form one-way ultra-low capacitance TVS device as claimed in claim 19, is characterized in that, be filled with polysilicon, define isolation structure in described groove.
21. integrated form one-way ultra-low capacitance TVS device as claimed in claim 18, it is characterized in that, all be formed with the second conductivity type implanted region in described second area and the 3rd region, the second conductivity type implanted region formed in described second area and the 3rd region is all as ohmic contact layer.
22. integrated form one-way ultra-low capacitance TVS device as claimed in claim 21, it is characterized in that, the second conductivity type implanted region formed in described second area is interdigitated electrode structure structure.
23. integrated form one-way ultra-low capacitance TVS device as claimed in claim 22, it is characterized in that, the first conductivity type implanted region formed in described second area is interdigitated electrode structure structure.
24. integrated form one-way ultra-low capacitance TVS device as claimed in claim 23, it is characterized in that, the comb of the second conductivity type implanted region of the interdigitated electrode structure structure formed in described second area is interlaced with the comb of the first conductivity type implanted region of the interdigitated electrode structure structure formed in described second area.
25. integrated form one-way ultra-low capacitance TVS device as claimed in claim 18, is characterized in that, described first conduction type is P type, described second conduction type is N-type; Or described first conduction type is N-type, described second conduction type is P type.
26. integrated form one-way ultra-low capacitance TVS device according to any one of claim 18 ~ 25, it is characterized in that, the resistivity of described first conductivity type substrate is 0.005 Ω .cm ~ 0.2 Ω .cm.
27. integrated form one-way ultra-low capacitance TVS device according to any one of claim 18 ~ 25, it is characterized in that, the resistivity of described first conductive type epitaxial layer is 2.0 Ω .cm ~ 4.0 Ω .cm, and the thickness of described first conductive type epitaxial layer is 6.0 μm ~ 14.0 μm.
28. integrated form one-way ultra-low capacitance TVS device according to any one of claim 18 ~ 25, it is characterized in that, the resistivity of described second conductive type epitaxial layer is 25 Ω .cm ~ 35 Ω .cm, and the thickness of described second conductive type epitaxial layer is 6.0 μm ~ 12.0 μm.
29. integrated form one-way ultra-low capacitance TVS device according to any one of claim 18 ~ 25, it is characterized in that, the puncture voltage of described diode Z1 is 3.3V ~ 7.0V.
30. integrated form one-way ultra-low capacitance TVS device according to any one of claim 18 ~ 25, it is characterized in that, described first conductivity type substrate is held with being, described second metal wire is connected with power end.
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| CN106783844B (en) * | 2017-01-25 | 2023-09-01 | 杭州士兰集成电路有限公司 | Unidirectional low-capacitance TVS device and manufacturing method thereof |
| CN107170738B (en) * | 2017-05-22 | 2019-07-19 | 富芯微电子有限公司 | A kind of unidirectional TVS device of low capacitor and its manufacturing method |
| CN107919355B (en) * | 2017-08-14 | 2023-09-19 | 上海领矽半导体有限公司 | Ultralow-residual-voltage low-capacity transient voltage suppressor and manufacturing method thereof |
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