CN103474427A - Integrated type one-way ultra-low capacitance TVS device and manufacturing method thereof - Google Patents
Integrated type one-way ultra-low capacitance TVS device and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides an integrated type one-way ultra-low capacitance TVS device and a manufacturing method thereof. The method comprises the step of providing a first electric conduction type substrate, the step of forming a first electric conduction type epitaxial layer on the first electric conduction type substrate, the step of forming a second electric conduction type buried layer in the first electric conduction type epitaxial layer, the step of forming a second electric conduction type epitaxial layer on the first electric conduction type epitaxial layer to form a diode D2, the step of forming a groove penetrating through the second electric conduction type epitaxial layer to form a first area, a second area and a third area, the step of forming first electric conduction type isolation connected with the first electric conduction type substrate in the first area, the step of forming a second electric conduction type injection area connected with the first electric conduction type isolation in the first area to form a diode Z1, the step of forming a first electric conduction type injection area in the second area to form a diode D1, and the step of forming a first metal wire connecting the diode Z1 and the diode D1 and forming a second metal wire connecting the diode D1 and the diode D2. Accordingly, the packaging defects are overcome, and the quality of the device is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of integrated form one-way ultra-low capacitance TVS device and manufacture method thereof.
Background technology
The one-way ultra-low capacitance TVS device is normally connected a low di-cap with a traditional voltage regulation type TVS diode in the market, form (see figure 1) with the low di-cap parallel combination of another one again, from the power Vcc I-V curve of GND over the ground, forward and reverse characteristic still is equivalent to a general-purpose diode, but the electric capacity of system line is well below the electric capacity of the single general T VS diode of identical voltage.
The one-way ultra-low capacitance TVS device combined, its power Vcc is the capacitance C of GND over the ground
tcan be expressed as:
Here C
d1and C
d2all less, C
z1than the above two large orders of magnitude, so, after diode D1 and diode Z1 series connection, total series capacitance is equal to the electric capacity of diode D1 substantially.
When power Vcc adds positive potential, when ground GND adds negative potential: because diode D2 puncture voltage is higher, diode Z1 puncture voltage is lower, so diode Z1 takes the lead in puncturing, the power Vcc reverse breakdown voltage of GND over the ground can be expressed as:
V
BR=Vf
D1+V
Z1
Wherein, Vf
d1forward voltage drop for diode D1.
When power Vcc adds negative potential, when ground GND adds positive potential: because diode D1 puncture voltage is higher, electric current preferentially passes through the forward of diode D2, and the power Vcc forward voltage drop of GND over the ground can be expressed as:
Vf=Vf
D2
The visible forward and reverse characteristic of one-way ultra-low capacitance TVS device combined is equivalent to a general-purpose diode substantially, and its reverse breakdown voltage is controlled by the puncture voltage of diode Z1 mainly; Electric capacity mainly is subject to C
d1and C
d2control, so, in order to realize ultra-low capacitance, reality is exactly to reduce C
d1and C
d2; Simultaneously power Vcc over the ground the positive and negative direction ESD ability reality of GND be also to be equal to respectively the forward ESD ability of D1, two diodes of D2 (reverse breakdown voltage of diode Z1 is lower, generally between 3.3-7.0V, its reverse ESD ability is very high, can not consider).So, in order to realize high ESD ability, reality is exactly to improve the forward ESD ability of D1, two diodes of D2.
Because above-mentioned one-way ultra-low capacitance TVS device is combined by discrete device, there is the certain defect in encapsulation.Therefore, provide a kind of integrated form one-way ultra-low capacitance TVS device to become this area problem demanding prompt solution.
Summary of the invention
The object of the present invention is to provide a kind of integrated form one-way ultra-low capacitance TVS device and manufacture method thereof, combined by discrete device to solve one-way ultra-low capacitance TVS device of the prior art, have the problem of the certain defect in encapsulation.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of integrated form one-way ultra-low capacitance TVS device, the manufacture method of described integrated form one-way ultra-low capacitance TVS device comprises:
The first conductivity type substrate is provided;
Form the first conductive type epitaxial layer on described the first conductivity type substrate;
Form the second conduction type buried regions in described the first conductive type epitaxial layer;
Form the second conductive type epitaxial layer on described the first conductive type epitaxial layer, described the first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Form groove, described groove runs through described the second conductive type epitaxial layer, and form first area in described the second conductive type epitaxial layer, second area and the 3rd zone;
Form the first conduction type isolation in described first area, and described the first conduction type isolation is connected with described the first conductivity type substrate;
Form the second conduction type injection region in described first area, described the second conduction type injection region is connected with described the first conduction type isolation, and described the second conduction type injection region and described the first conduction type isolation form diode Z1;
Form the first conduction type injection region in described second area, described the first conduction type injection region and the second conductive type epitaxial layer form diode D1;
Form the first metal wire and the second metal wire, wherein, described the first metal wire connects described diode Z1 and diode D1, and described the second metal wire connects described diode D1 and diode D2.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the degree of depth of described groove is that 10 μ m～20 μ m, cross-sectional width are 1.5 μ m～3.0 μ m.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, after forming groove, form the first conduction type isolation in described first area before, in described groove, fill polysilicon.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, when in described first area, forming the second conduction type injection region, all form the second conduction type injection region in described second area and the 3rd zone, the second conduction type injection region formed in described second area and the 3rd zone is all as ohmic contact layer.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the second conduction type injection region formed in described second area is the interdigitated electrode structure structure.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the first conduction type injection region formed in described second area is the interdigitated electrode structure structure.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the broach of the second conduction type injection region of the interdigitated electrode structure structure formed in described second area is interlaced with the broach of the first conduction type injection region of the interdigitated electrode structure structure formed in described second area.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, described the first conduction type is that P type, described the second conduction type are N-type; Perhaps described the first conduction type is that N-type, described the second conduction type are the P type.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the resistivity of described the first conductivity type substrate is 0.005 Ω .cm～0.2 Ω .cm.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the resistivity of described the first conductive type epitaxial layer is 2.0 Ω .cm～4.0 Ω .cm, and the thickness of described the first conductive type epitaxial layer is 6.0 μ m～14.0 μ m.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, form the second conduction type buried regions by following technique in described the first conductive type epitaxial layer:
Inject antimony ion in described the first conductive type epitaxial layer, the implantation dosage of described antimony ion is 2.0E15～6.0E15;
Described antimony ion is carried out to annealing process, and the temperature of described annealing process is 1200 ℃～1250 ℃; The time of described annealing process is 2.0h～6.0h.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the resistivity of described the second conductive type epitaxial layer is 25 Ω .cm～35 Ω .cm, and the thickness of described the second conductive type epitaxial layer is 6.0 μ m～12.0 μ m.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, form the first conduction type isolation by following technique in described first area:
B Implanted ion in described first area, the implantation dosage of described boron ion is 2.0E14～4.5E15;
Described boron ion is carried out to annealing process, and the temperature of described annealing process is 1200 ℃～1250 ℃; The time of described annealing process is 2.0h～6.0h.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, form the second conduction type injection region by following technique in described first area:
Inject phosphonium ion in described first area, the implantation dosage of described phosphonium ion is 1.0E15～1.0E16;
Described phosphonium ion is carried out to annealing process for the first time, and the temperature of described annealing process for the first time is 1100 ℃～1200 ℃; The time of described annealing process for the first time is 10s～20s;
Described phosphonium ion is carried out to annealing process for the second time, and the temperature of described annealing process for the second time is 800 ℃～900 ℃; The time of described annealing process for the second time is 30min～60min.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, the puncture voltage of described diode Z1 is 3.3V～7.0V.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, form the first conduction type injection region by following technique in described second area:
B Implanted ion in described second area, the implantation dosage of described boron ion is 1.0E15～1.0E16;
Described boron ion is carried out to annealing process for the first time, and the temperature of described annealing process for the first time is 1100 ℃～1200 ℃; The time of described annealing process for the first time is 10s～20s;
Described boron ion is carried out to annealing process for the second time, and the temperature of described annealing process for the second time is 800 ℃～900 ℃; The time of described annealing process for the second time is 30min～60min.
Optionally, in the manufacture method of described integrated form one-way ultra-low capacitance TVS device, described the first conductivity type substrate is held with being, and described the second metal wire is connected with power end.
The present invention also provides a kind of integrated form one-way ultra-low capacitance TVS device, and described integrated form one-way ultra-low capacitance TVS device comprises:
The first conductivity type substrate;
Be formed at the first conductive type epitaxial layer on described the first conductivity type substrate;
Be formed at the second conduction type buried regions in described the first conductive type epitaxial layer;
Be formed at the second conductive type epitaxial layer on described the first conductive type epitaxial layer, described the first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Groove, described groove runs through described the second conductive type epitaxial layer, and formed first area in described the second conductive type epitaxial layer, second area and the 3rd zone;
Be formed at the first conduction type isolation in described first area, described the first conduction type isolation is connected with described the first conductivity type substrate;
Be formed at the second conduction type injection region in described first area, described the second conduction type injection region is connected with described the first conduction type isolation, and described the second conduction type injection region and described the first conduction type isolation form diode Z1;
Be formed at the first conduction type injection region in described second area, described the first conduction type injection region and the second conductive type epitaxial layer form diode D1; And
The first metal wire that connects described diode Z1 and diode D1, connect the second metal wire of described diode D1 and diode D2.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the degree of depth of described groove is that 10 μ m～20 μ m, cross-sectional width are 1.5 μ m～3.0 μ m.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, in described groove, be filled with polysilicon, formed isolation structure.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, all be formed with the second conduction type injection region in described second area and the 3rd zone, the second conduction type injection region formed in described second area and the 3rd zone is all as ohmic contact layer.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the second conduction type injection region formed in described second area is the interdigitated electrode structure structure.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the first conduction type injection region formed in described second area is the interdigitated electrode structure structure.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the broach of the second conduction type injection region of the interdigitated electrode structure structure formed in described second area is interlaced with the broach of the first conduction type injection region of the interdigitated electrode structure structure formed in described second area.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, described the first conduction type is that P type, described the second conduction type are N-type; Perhaps described the first conduction type is that N-type, described the second conduction type are the P type.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the resistivity of described the first conductivity type substrate is 0.005 Ω .cm～0.2 Ω .cm.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the resistivity of described the first conductive type epitaxial layer is 2.0 Ω .cm～4.0 Ω .cm, and the thickness of described the first conductive type epitaxial layer is 6.0 μ m～14.0 μ m.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the resistivity of described the second conductive type epitaxial layer is 25 Ω .cm～35 Ω .cm, and the thickness of described the second conductive type epitaxial layer is 6.0 μ m～12.0 μ m.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, the puncture voltage of described diode Z1 is 3.3V～7.0V.
Optionally, in described integrated form one-way ultra-low capacitance TVS device, described the first conductivity type substrate is held with being, and described the second metal wire is connected with power end.
In integrated form one-way ultra-low capacitance TVS device provided by the invention and manufacture method thereof, formed one-way ultra-low capacitance TVS device is integrated structure, thereby has avoided the defect in the encapsulation, has improved device quality.
The accompanying drawing explanation
Fig. 1 is the one-way ultra-low capacitance TVS device circuit diagram combined;
Fig. 2～Figure 12 is the generalized section of the formed device of manufacture method of the integrated form one-way ultra-low capacitance TVS device of the embodiment of the present invention one;
Figure 13～Figure 23 is the generalized section of the formed device of manufacture method of the integrated form one-way ultra-low capacitance TVS device of the embodiment of the present invention two.
Embodiment
The integrated form one-way ultra-low capacitance TVS device and the manufacture method thereof that the present invention are proposed below in conjunction with the drawings and specific embodiments are described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the present invention lucidly.
[embodiment mono-]
The present embodiment provides a kind of manufacture method of integrated form one-way ultra-low capacitance TVS device, comprising:
S10: the first conductivity type substrate is provided;
S11: form the first conductive type epitaxial layer on described the first conductivity type substrate;
S12: form the second conduction type buried regions in described the first conductive type epitaxial layer;
S13: form the second conductive type epitaxial layer on described the first conductive type epitaxial layer, described the first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
S14: form groove, described groove runs through described the second conductive type epitaxial layer, and form first area in described the second conductive type epitaxial layer, second area and the 3rd zone;
S15: form the first conduction type isolation in described first area, and described the first conduction type isolation is connected with described the first conductivity type substrate;
S16: form the second conduction type injection region in described first area, described the second conduction type injection region is connected with described the first conduction type isolation, and described the second conduction type injection region and described the first conduction type isolation form diode Z1;
S17: form the first conduction type injection region in described second area, described the first conduction type injection region and the second conductive type epitaxial layer form diode D1;
S18: form the first metal wire and the second metal wire, wherein, described the first metal wire connects described diode Z1 and diode D1, and described the second metal wire connects described diode D1 and diode D2.
Concrete, please refer to Fig. 2～12, the generalized section of the formed device of manufacture method of the integrated form one-way ultra-low capacitance TVS device that it is the embodiment of the present invention one.
As shown in Figure 2, provide the first conductivity type substrate 10, described the first conductivity type substrate 10 can be P type substrate, can be also the N-type substrate.In the present embodiment, described the first conduction type is the P type, and follow-up the second conduction type related to is N-type.In other embodiment of the application, can be also that the first conduction type is N-type, the second conduction type is the P type.The resistivity of described the first conductivity type substrate 10 is 0.005 Ω .cm～0.2 Ω .cm.
Then, as shown in Figure 3, form the first conductive type epitaxial layer 11 on described the first conductivity type substrate 10, described the first conductive type epitaxial layer 11 is P type epitaxial loayer, and it can generate by chemical vapor deposition method.Preferably, the resistivity of described the first conductive type epitaxial layer 11 is 2.0 Ω .cm～4.0 Ω .cm, and the thickness of described the first conductive type epitaxial layer 11 is 6.0 μ m～14.0 μ m.
As shown in Figure 4, form the second conduction type buried regions 12 in described the first conductive type epitaxial layer 11, described the second conduction type buried regions 12 is n type buried layer.Concrete, can form described the second conduction type buried regions 12 by following technique: inject antimony ion in described the first conductive type epitaxial layer 11, the implantation dosage of described antimony ion is 2.0E15～6.0E15; Described antimony ion is carried out to annealing process, and the temperature of described annealing process is 1200 ℃～1250 ℃; The time of described annealing process is 2.0h～6.0h.
As shown in Figure 5, form the second conductive type epitaxial layer 13 on described the first conductive type epitaxial layer 11, described the second conductive type epitaxial layer 13 is the N-type epitaxial loayer, and described the first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13 form diode D2.Preferably, the resistivity of described the second conductive type epitaxial layer 13 is 25 Ω .cm～35 Ω .cm, and the thickness of described the second conductive type epitaxial layer 13 is 6.0 μ m～12.0 μ m.Wherein, the large I of the capacitance of described diode D2 is achieved by area and/or the resistivity of adjusting described the first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13, and this application is repeated no more.
Then, as shown in Figure 6, form groove 14, described groove 14 runs through described the second conductive type epitaxial layer 13, and forms first area A, second area B and the 3rd regional C in described the second conductive type epitaxial layer 13.Preferably, the degree of depth of described groove 14 is that 10 μ m～20 μ m, cross-sectional width are 1.5 μ m～3.0 μ m.In the present embodiment, adopt groove to be isolated, not only technique is simple, and also can guarantee does not have ghost effect between each diode of follow-up formation, especially multichannel structure, thus improved the reliability of formed integrated form one-way ultra-low capacitance TVS device.In addition, described groove 14 belongs to deep groove structure, and the junction area of formed diode D2 only has the contact zone, bottom of the first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13 thus, so area is less, corresponding electric capacity is also less.
Then, as shown in Figure 7, in described groove 14, fill polysilicon, form isolation structure 15, described isolation structure 15 runs through described the second conductive type epitaxial layer 13.
Then, as shown in Figure 8, form the first conduction type isolation 16 in described first area A, described the first conduction type isolation 16 is the isolation of P type, and described the first conduction type isolation 16 is connected with described the first conductivity type substrate 10.Concrete, can form the first conduction type isolation 16 by following technique: B Implanted ion in described first area A, the implantation dosage of described boron ion is 2.0E14～4.5E15; Described boron ion is carried out to annealing process, and the temperature of described annealing process is 1200 ℃～1250 ℃; The time of described annealing process is 2.0h～6.0h.
As shown in Figure 9, form the second conduction type injection region 17a in described first area A, described the second 17aWeiNXing injection region, conduction type injection region, described the second conduction type injection region 17a is connected with described the first conduction type isolation 16, and described the second conduction type injection region 17a and described the first conduction type isolation 16 form diode Z1.Further, described the second conduction type injection region 17a surrounds described the first conduction type isolation 16, thus the uniformity of avoiding diode Z1 electric leakage and guaranteeing diode Z1 voltage.Concrete, described the second conduction type injection region 17a can form by following technique: inject phosphonium ion in described first area A, the implantation dosage of described phosphonium ion is 1.0E15～1.0E16; Described phosphonium ion is carried out to annealing process for the first time, and the temperature of described annealing process for the first time is 1100 ℃～1200 ℃; The time of described annealing process for the first time is 10s～20s; Described phosphonium ion is carried out to annealing process for the second time, and the temperature of described annealing process for the second time is 800 ℃～900 ℃; The time of described annealing process for the second time is 30min～60min.The low pressure diode that is 3.3V～7.0V by the formed diode Z1 of above-mentioned technique.Wherein, annealing process also can be called high temperature rapid thermal annealing technique for the first time, its objective is the phosphorus impurities that activates all injections, when guaranteeing to form the good ohmic contact, also reduces the reverse leakage current of diode Z1; Annealing process also can be called low temperature boiler tube annealing process for the second time, its objective is junction depth and the puncture voltage of controlling diode Z1, guarantees that puncture voltage is in the 3.3V-7.0V left and right.
In the present embodiment, when in described first area A, forming the second conduction type injection region 17a, all form the second conduction type injection region in described second area B and the 3rd regional C, form the second conduction type injection region 17b in described second area B, form the second conduction type injection region 17c in the 3rd regional C, described the second conduction type injection region 17b and the second conduction type injection region 17c are all as ohmic contact layer.
Then, as shown in figure 10, form the first conduction type injection region 18 in described second area B, described the first conduction type injection region 18 and the second conductive type epitaxial layer 13 form diode D1.Concrete, form the first conduction type injection region 18 by following technique: B Implanted ion in described second area B, the implantation dosage of described boron ion is 1.0E15～1.0E16; Described boron ion is carried out to annealing process for the first time, and the temperature of described annealing process for the first time is 1100 ℃～1200 ℃; The time of described annealing process for the first time is 10s～20s; Described boron ion is carried out to annealing process for the second time, and the temperature of described annealing process for the second time is 800 ℃～900 ℃; The time of described annealing process for the second time is 30min～60min.Wherein, annealing process also can be called high temperature rapid thermal annealing technique for the first time, its objective is the boron impurity that activates all injections, guarantees to form good ohmic contact; Annealing process also can be called low temperature boiler tube annealing process for the second time, its objective is the junction depth of controlling diode D1, guarantees that junction depth is in 0.5 μ m-1.0 μ m left and right.
Then, as shown in figure 12, form the first metal wire 20a and the second metal wire 20b, wherein, described the first metal wire 20a connects described diode Z1 and diode D1, and described the second metal wire 20b connects described diode D1 and diode D2.Concrete, can form dielectric layer 19 on described the second conductive type epitaxial layer 13 with reference to Figure 11, described dielectric layer 19 exposes diode Z1, diode D1 and diode D2; Then, can, with reference to Figure 12, by deposited metal, form the first metal wire 20a and the second metal wire 20b.
In the present embodiment, described the first conductivity type substrate 10 is held with being, and described the second metal wire 20b is connected with power end.The first conductivity type substrate 10 is directly as the electrode of ground connection GND, thereby do not need to draw ground connection GND electrode, so not only can dwindle the size of chip, meet the more encapsulation of small size, while encapsulating in addition, the first conductivity type substrate 10 is directly drawn as the GND electrode, can reduce by 1 wires, greatly reduce packaging cost.
Please continue to refer to Figure 12, the manufacture method by above-mentioned integrated form one-way ultra-low capacitance TVS device has formed following integrated form one-way ultra-low capacitance TVS device, specifically comprises:
The first conductivity type substrate 10;
Be formed at the first conductive type epitaxial layer 11 on described the first conductivity type substrate 10;
Be formed at the second conduction type buried regions 12 in described the first conductive type epitaxial layer 11;
Be formed at the second conductive type epitaxial layer 13 on described the first conductive type epitaxial layer 11, described the first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13 form diode D2;
Groove, described groove runs through described the second conductive type epitaxial layer 13, and has formed first area A, second area B and the 3rd regional C in described the second conductive type epitaxial layer 13;
Be formed at the first conduction type isolation 16 in described first area A, described the first conduction type isolation 16 is connected with described the first conductivity type substrate 10;
Be formed at the second conduction type injection region 17a in described first area A, described the second conduction type injection region 17a is connected with described the first conduction type isolation 16, and described the second conduction type injection region 17a and described the first conduction type isolation 16 form diode Z1;
Be formed at the first conduction type injection region 18 in described second area B, described the first conduction type injection region 18 and the second conductive type epitaxial layer 13 form diode D1; And
The the first metal wire 20a that connects described diode Z1 and diode D1, connect the second metal wire 20b of described diode D1 and diode D2.
In the integrated form one-way ultra-low capacitance TVS device and manufacture method thereof provided at the present embodiment, formed one-way ultra-low capacitance TVS device is integrated structure, thereby has avoided the defect in the encapsulation, has improved device quality.
[embodiment bis-]
Please refer to Figure 13～Figure 23, the generalized section of the formed device of manufacture method of the integrated form one-way ultra-low capacitance TVS device that it is the embodiment of the present invention two.
The present embodiment two is that with the difference of embodiment mono-the second conduction type injection region formed in described second area is the interdigitated electrode structure structure; Simultaneously, the first conduction type injection region formed in described second area is also the interdigitated electrode structure structure.The broach of the second conduction type injection region of the interdigitated electrode structure structure further, formed in described second area is interlaced with the broach of the first conduction type injection region of the interdigitated electrode structure structure formed in described second area.The broach quantity of the second conduction type injection region of the interdigitated electrode structure structure wherein, formed in described second area reaches the broach quantity of the first conduction type injection region of the interdigitated electrode structure structure formed in described second area and determines according to electric capacity and the ESD Capability Requirement of diode D1.Adopting the benefit of comb structure is the electric current lateral flow, and ESD is mainly determined by the girth of broach, and electric capacity is by the area definition of broach.Because the area of comb structure is less, and girth is larger, so can guarantee high ESD and low electric capacity.
Concrete, as shown in figure 13, providing the first conductivity type substrate 30, described the first conductivity type substrate 30 can be P type substrate, can be also the N-type substrate.In the present embodiment, described the first conduction type is the P type, and follow-up the second conduction type related to is N-type.In other embodiment of the application, can be also that the first conduction type is N-type, the second conduction type is the P type.The resistivity of described the first conductivity type substrate 30 is 0.005 Ω .cm～0.2 Ω .cm.
Then, as shown in figure 14, form the first conductive type epitaxial layer 31 on described the first conductivity type substrate 30, described the first conductive type epitaxial layer 31 is P type epitaxial loayer, and it can generate by chemical vapor deposition method.Preferably, the resistivity of described the first conductive type epitaxial layer 31 is 2.0 Ω .cm～4.0 Ω .cm, and the thickness of described the first conductive type epitaxial layer 31 is 6.0 μ m～14.0 μ m.
As shown in figure 15, form the second conduction type buried regions 32 in described the first conductive type epitaxial layer 31, described the second conduction type buried regions 32 is n type buried layer.Concrete, can form described the second conduction type buried regions 32 by following technique: inject antimony ion in described the first conductive type epitaxial layer 31, the implantation dosage of described antimony ion is 2.0E15～6.0E15; Described antimony ion is carried out to annealing process, and the temperature of described annealing process is 1200 ℃～1250 ℃; The time of described annealing process is 2.0h～6.0h.
As shown in figure 16, form the second conductive type epitaxial layer 33 on described the first conductive type epitaxial layer 31, described the second conductive type epitaxial layer 33 is the N-type epitaxial loayer, and described the first conductive type epitaxial layer 31 and the second conductive type epitaxial layer 33 form diode D2.Preferably, the resistivity of described the second conductive type epitaxial layer 33 is 25 Ω .cm～35 Ω .cm, and the thickness of described the second conductive type epitaxial layer 33 is 6.0 μ m～12.0 μ m.Wherein, the large I of the capacitance of described diode D2 is achieved by area and/or the resistivity of adjusting described the first conductive type epitaxial layer 31 and the second conductive type epitaxial layer 33, and this application is repeated no more.
Then, as shown in figure 17, form groove 34, described groove 34 runs through described the second conductive type epitaxial layer 33, and forms first area D, second area E and the 3rd regional F in described the second conductive type epitaxial layer 33.Preferably, the degree of depth of described groove 34 is that 10 μ m～20 μ m, cross-sectional width are 1.5 μ m～3.0 μ m.In the present embodiment, adopt groove to be isolated, not only technique is simple, and also can guarantee does not have ghost effect between each diode of follow-up formation, especially multichannel structure, thus improved the reliability of formed integrated form one-way ultra-low capacitance TVS device.In addition, described groove 34 belongs to deep groove structure, and the junction area of formed diode D2 only has the contact zone, bottom of the first conductive type epitaxial layer 31 and the second conductive type epitaxial layer 33 thus, so area is less, corresponding electric capacity is also less.
Then, as shown in figure 18, in described groove 34, fill polysilicon, form isolation structure 35, described isolation structure 35 runs through described the second conductive type epitaxial layer 33.
Then, as shown in figure 19, form the first conduction type isolation 36 in described first area D, described the first conduction type isolation 36 is the isolation of P type, and described the first conduction type isolation 36 is connected with described the first conductivity type substrate 30.Concrete, can form the first conduction type isolation 36 by following technique: B Implanted ion in described first area D, the implantation dosage of described boron ion is 2.0E14～4.5E15; Described boron ion is carried out to annealing process, and the temperature of described annealing process is 1200 ℃～1250 ℃; The time of described annealing process is 2.0h～6.0h.
As shown in figure 20, form the second conduction type injection region 37a in described first area D, described the second 37aWeiNXing injection region, conduction type injection region, described the second conduction type injection region 37a is connected with described the first conduction type isolation 36, and described the second conduction type injection region 37a and described the first conduction type isolation 36 form diode Z1.Further, described the second conduction type injection region 37a surrounds described the first conduction type isolation 36, thus the uniformity of avoiding diode Z1 electric leakage and guaranteeing diode Z1 voltage.Concrete, described the second conduction type injection region 37a can form by following technique: inject phosphonium ion in described first area D, the implantation dosage of described phosphonium ion is 1.0E15～1.0E16; Described phosphonium ion is carried out to annealing process for the first time, and the temperature of described annealing process for the first time is 1100 ℃～1200 ℃; The time of described annealing process for the first time is 10s～20s; Described phosphonium ion is carried out to annealing process for the second time, and the temperature of described annealing process for the second time is 800 ℃～900 ℃; The time of described annealing process for the second time is 30min～60min.The low pressure diode that is 3.3V～7.0V by the formed diode Z1 of above-mentioned technique.Wherein, annealing process also can be called high temperature rapid thermal annealing technique for the first time, its objective is the phosphorus impurities that activates all injections, when guaranteeing to form the good ohmic contact, also reduces the reverse leakage current of diode Z1; Annealing process also can be called low temperature boiler tube annealing process for the second time, its objective is junction depth and the puncture voltage of controlling diode Z1, guarantees that puncture voltage is in the 3.3V-7.0V left and right.
In the present embodiment, when in described first area D, forming the second conduction type injection region 37a, in described second area E and the 3rd regional F, all form the second conduction type injection region.Wherein, the second conduction type injection region formed in described second area E is the interdigitated electrode structure structure, and the second conduction type injection region formed in described second area E comprises broach 37b, 37c, 37d, 37e; Form the second conduction type injection region 37f in the 3rd regional F, described broach 37b, 37c, 37d, 37e and the second conduction type injection region 37f are all as ohmic contact layer.
Then, as shown in figure 21, form the first conduction type injection region in described second area E, described the first conduction type injection region and the second conductive type epitaxial layer 33 form diode D1.In the present embodiment, the first conduction type injection region formed in described second area E is also the interdigitated electrode structure structure, and the first conduction type injection region formed in described second area E comprises broach 38a, 38b, 38c.
Concrete, form the first conduction type injection region by following technique: B Implanted ion in described second area E, the implantation dosage of described boron ion is 1.0E15～1.0E16; Described boron ion is carried out to annealing process for the first time, and the temperature of described annealing process for the first time is 1100 ℃～1200 ℃; The time of described annealing process for the first time is 10s～20s; Described boron ion is carried out to annealing process for the second time, and the temperature of described annealing process for the second time is 800 ℃～900 ℃; The time of described annealing process for the second time is 30min～60min.Wherein, annealing process also can be called high temperature rapid thermal annealing technique for the first time, its objective is the boron impurity that activates all injections, guarantees to form good ohmic contact; Annealing process also can be called low temperature boiler tube annealing process for the second time, its objective is the junction depth of controlling diode D1, guarantees that junction depth is in 0.5 μ m-1.0 μ m left and right.
The broach of the second conduction type injection region of the interdigitated electrode structure structure further, formed in described second area E is interlaced with the broach of the first conduction type injection region of the interdigitated electrode structure structure formed in described second area E.Be that broach 37b, 37c, 37d, 37e and broach 38a, 38b, 38c are staggered, be easy to thus the lateral flow of electric current.
Then, as shown in figure 23, form the first metal wire 40a and the second metal wire 40b, wherein, described the first metal wire 40a connects described diode Z1 and diode D1, and described the second metal wire 40b connects described diode D1 and diode D2.Concrete, can form dielectric layer 39 on described the second conductive type epitaxial layer 33 with reference to Figure 22, described dielectric layer 39 exposes diode Z1, diode D1 and diode D2; Then, can, with reference to Figure 23, by deposited metal, form the first metal wire 40a and the second metal wire 40b.
In the present embodiment, described the first conductivity type substrate 30 is held with being, and described the second metal wire 40b is connected with power end.The first conductivity type substrate 30 is directly as the electrode of ground connection GND, thereby do not need to draw ground connection GND electrode, so not only can dwindle the size of chip, meet the more encapsulation of small size, while encapsulating in addition, the first conductivity type substrate 30 is directly drawn as the GND electrode, can reduce by 1 wires, greatly reduce packaging cost.
Please continue to refer to Figure 23, the manufacture method by above-mentioned integrated form one-way ultra-low capacitance TVS device has formed following integrated form one-way ultra-low capacitance TVS device, specifically comprises:
The first conductivity type substrate 30;
Be formed at the first conductive type epitaxial layer 31 on described the first conductivity type substrate 30;
Be formed at the second conduction type buried regions 32 in described the first conductive type epitaxial layer 31;
Be formed at the second conductive type epitaxial layer 33 on described the first conductive type epitaxial layer 31, described the first conductive type epitaxial layer 31 and the second conductive type epitaxial layer 33 form diode D2;
Groove, described groove runs through described the second conductive type epitaxial layer 33, and has formed first area D, second area E and the 3rd regional F in described the second conductive type epitaxial layer 33;
Be formed at the first conduction type isolation 36 in described first area D, described the first conduction type isolation 36 is connected with described the first conductivity type substrate 30;
Be formed at the second conduction type injection region 37a in described first area D, described the second conduction type injection region 37a is connected with described the first conduction type isolation 36, and described the second conduction type injection region 37a and described the first conduction type isolation 36 form diode Z1;
Be formed at the first conduction type injection region in described second area E, described the first conduction type injection region and the second conductive type epitaxial layer 33 form diode D1; And
The the first metal wire 40a that connects described diode Z1 and diode D1, connect the second metal wire 40b of described diode D1 and diode D2.
Wherein, the second conduction type injection region formed in described second area E is the interdigitated electrode structure structure; Simultaneously, the first conduction type injection region formed in described second area E is also the interdigitated electrode structure structure.
In the integrated form one-way ultra-low capacitance TVS device and manufacture method thereof provided at the present embodiment, formed one-way ultra-low capacitance TVS device is integrated structure, thereby has avoided the defect in the encapsulation, has improved device quality.
Foregoing description is only the description to preferred embodiment of the present invention, and not, to any restriction of the scope of the invention, this structure may also extend into the one-way low-capacitance product of a plurality of passages in addition.Any change, modification that the those of ordinary skill in field of the present invention is done according to above-mentioned disclosure, all belong to the protection range of claims.
Claims (30)
1. the manufacture method of an integrated form one-way ultra-low capacitance TVS device, is characterized in that, comprising:
The first conductivity type substrate is provided;
Form the first conductive type epitaxial layer on described the first conductivity type substrate;
Form the second conduction type buried regions in described the first conductive type epitaxial layer;
Form the second conductive type epitaxial layer on described the first conductive type epitaxial layer, described the first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Form groove, described groove runs through described the second conductive type epitaxial layer, and form first area in described the second conductive type epitaxial layer, second area and the 3rd zone;
Form the first conduction type isolation in described first area, and described the first conduction type isolation is connected with described the first conductivity type substrate;
Form the second conduction type injection region in described first area, described the second conduction type injection region is connected with described the first conduction type isolation, and described the second conduction type injection region and described the first conduction type isolation form diode Z1;
Form the first conduction type injection region in described second area, described the first conduction type injection region and the second conductive type epitaxial layer form diode D1;
Form the first metal wire and the second metal wire, wherein, described the first metal wire connects described diode Z1 and diode D1, and described the second metal wire connects described diode D1 and diode D2.
2. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 1, is characterized in that, the degree of depth of described groove is that 10 μ m～20 μ m, cross-sectional width are 1.5 μ m～3.0 μ m.
3. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 2, is characterized in that, after forming groove, form the first conduction type isolation in described first area before, in described groove, fills polysilicon.
4. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 1, it is characterized in that, when in described first area, forming the second conduction type injection region, all form the second conduction type injection region in described second area and the 3rd zone, the second conduction type injection region formed in described second area and the 3rd zone is all as ohmic contact layer.
5. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 4, is characterized in that, the second conduction type injection region formed in described second area is the interdigitated electrode structure structure.
6. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 5, is characterized in that, the first conduction type injection region formed in described second area is the interdigitated electrode structure structure.
7. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 6, it is characterized in that, the broach of the second conduction type injection region of the interdigitated electrode structure structure formed in described second area is interlaced with the broach of the first conduction type injection region of the interdigitated electrode structure structure formed in described second area.
8. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 1, is characterized in that, described the first conduction type is that P type, described the second conduction type are N-type; Perhaps described the first conduction type is that N-type, described the second conduction type are the P type.
9. the manufacture method of integrated form one-way ultra-low capacitance TVS device as described as any one in claim 1～8, is characterized in that, the resistivity of described the first conductivity type substrate is 0.005 Ω .cm～0.2 Ω .cm.
10. the manufacture method of integrated form one-way ultra-low capacitance TVS device as described as any one in claim 1～8, it is characterized in that, the resistivity of described the first conductive type epitaxial layer is 2.0 Ω .cm～4.0 Ω .cm, and the thickness of described the first conductive type epitaxial layer is 6.0 μ m～14.0 μ m.
11. the manufacture method of integrated form one-way ultra-low capacitance TVS device as described as any one in claim 1～8, is characterized in that, forms the second conduction type buried regions in described the first conductive type epitaxial layer by following technique:
Inject antimony ion in described the first conductive type epitaxial layer, the implantation dosage of described antimony ion is 2.0E15～6.0E15;
Described antimony ion is carried out to annealing process, and the temperature of described annealing process is 1200 ℃～1250 ℃; The time of described annealing process is 2.0h～6.0h.
12. the manufacture method of integrated form one-way ultra-low capacitance TVS device as described as any one in claim 1～8, it is characterized in that, the resistivity of described the second conductive type epitaxial layer is 25 Ω .cm～35 Ω .cm, and the thickness of described the second conductive type epitaxial layer is 6.0 μ m～12.0 μ m.
13. the manufacture method of integrated form one-way ultra-low capacitance TVS device as described as any one in claim 1～8, is characterized in that, forms the first conduction type isolation in described first area by following technique:
B Implanted ion in described first area, the implantation dosage of described boron ion is 2.0E14～4.5E15;
Described boron ion is carried out to annealing process, and the temperature of described annealing process is 1200 ℃～1250 ℃; The time of described annealing process is 2.0h～6.0h.
14. the manufacture method of integrated form one-way ultra-low capacitance TVS device as described as any one in claim 1～8, is characterized in that, forms the second conduction type injection region in described first area by following technique:
Inject phosphonium ion in described first area, the implantation dosage of described phosphonium ion is 1.0E15～1.0E16;
Described phosphonium ion is carried out to annealing process for the first time, and the temperature of described annealing process for the first time is 1100 ℃～1200 ℃; The time of described annealing process for the first time is 10s～20s;
Described phosphonium ion is carried out to annealing process for the second time, and the temperature of described annealing process for the second time is 800 ℃～900 ℃; The time of described annealing process for the second time is 30min～60min.
15. the manufacture method of integrated form one-way ultra-low capacitance TVS device as claimed in claim 14, is characterized in that, the puncture voltage of described diode Z1 is 3.3V～7.0V.
16. the manufacture method of integrated form one-way ultra-low capacitance TVS device as described as any one in claim 1～8, is characterized in that, forms the first conduction type injection region in described second area by following technique:
B Implanted ion in described second area, the implantation dosage of described boron ion is 1.0E15～1.0E16;
Described boron ion is carried out to annealing process for the first time, and the temperature of described annealing process for the first time is 1100 ℃～1200 ℃; The time of described annealing process for the first time is 10s～20s;
Described boron ion is carried out to annealing process for the second time, and the temperature of described annealing process for the second time is 800 ℃～900 ℃; The time of described annealing process for the second time is 30min～60min.
17. the manufacture method of integrated form one-way ultra-low capacitance TVS device as described as any one in claim 1～8 is characterized in that described the first conductivity type substrate is held with being, described the second metal wire is connected with power end.
18. an integrated form one-way ultra-low capacitance TVS device, is characterized in that, comprising:
The first conductivity type substrate;
Be formed at the first conductive type epitaxial layer on described the first conductivity type substrate;
Be formed at the second conduction type buried regions in described the first conductive type epitaxial layer;
Be formed at the second conductive type epitaxial layer on described the first conductive type epitaxial layer, described the first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Groove, described groove runs through described the second conductive type epitaxial layer, and formed first area in described the second conductive type epitaxial layer, second area and the 3rd zone;
Be formed at the first conduction type isolation in described first area, described the first conduction type isolation is connected with described the first conductivity type substrate;
Be formed at the second conduction type injection region in described first area, described the second conduction type injection region is connected with described the first conduction type isolation, and described the second conduction type injection region and described the first conduction type isolation form diode Z1;
Be formed at the first conduction type injection region in described second area, described the first conduction type injection region and the second conductive type epitaxial layer form diode D1; And
The first metal wire that connects described diode Z1 and diode D1, connect the second metal wire of described diode D1 and diode D2.
19. integrated form one-way ultra-low capacitance TVS device as claimed in claim 18, is characterized in that, the degree of depth of described groove is that 10 μ m～20 μ m, cross-sectional width are 1.5 μ m～3.0 μ m.
20. integrated form one-way ultra-low capacitance TVS device as claimed in claim 19, is characterized in that, in described groove, is filled with polysilicon, formed isolation structure.
21. integrated form one-way ultra-low capacitance TVS device as claimed in claim 18, it is characterized in that, all be formed with the second conduction type injection region in described second area and the 3rd zone, the second conduction type injection region formed in described second area and the 3rd zone is all as ohmic contact layer.
22. integrated form one-way ultra-low capacitance TVS device as claimed in claim 21, is characterized in that, the second conduction type injection region formed in described second area is the interdigitated electrode structure structure.
23. integrated form one-way ultra-low capacitance TVS device as claimed in claim 22, is characterized in that, the first conduction type injection region formed in described second area is the interdigitated electrode structure structure.
24. integrated form one-way ultra-low capacitance TVS device as claimed in claim 23, it is characterized in that, the broach of the second conduction type injection region of the interdigitated electrode structure structure formed in described second area is interlaced with the broach of the first conduction type injection region of the interdigitated electrode structure structure formed in described second area.
25. integrated form one-way ultra-low capacitance TVS device as claimed in claim 18, is characterized in that, described the first conduction type is that P type, described the second conduction type are N-type; Perhaps described the first conduction type is that N-type, described the second conduction type are the P type.
26. integrated form one-way ultra-low capacitance TVS device as described as any one in claim 18～25, is characterized in that, the resistivity of described the first conductivity type substrate is 0.005 Ω .cm～0.2 Ω .cm.
27. integrated form one-way ultra-low capacitance TVS device as described as any one in claim 18～25, it is characterized in that, the resistivity of described the first conductive type epitaxial layer is 2.0 Ω .cm～4.0 Ω .cm, and the thickness of described the first conductive type epitaxial layer is 6.0 μ m～14.0 μ m.
28. integrated form one-way ultra-low capacitance TVS device as described as any one in claim 18～25, it is characterized in that, the resistivity of described the second conductive type epitaxial layer is 25 Ω .cm～35 Ω .cm, and the thickness of described the second conductive type epitaxial layer is 6.0 μ m～12.0 μ m.
29. integrated form one-way ultra-low capacitance TVS device as described as any one in claim 18～25 is characterized in that the puncture voltage of described diode Z1 is 3.3V～7.0V.
30. integrated form one-way ultra-low capacitance TVS device as described as any one in claim 18～25 is characterized in that described the first conductivity type substrate is held with being, described the second metal wire is connected with power end.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465723A (en) * | 2014-12-30 | 2015-03-25 | 北京燕东微电子有限公司 | Low-capacitance transient voltage restraint device and manufacturing method thereof |
| CN106783844A (en) * | 2017-01-25 | 2017-05-31 | 杭州士兰集成电路有限公司 | One-way low-capacitance TVS device and its manufacture method |
| CN107170738A (en) * | 2017-05-22 | 2017-09-15 | 安徽富芯微电子有限公司 | A kind of unidirectional TVS device of low electric capacity and its manufacture method |
| CN107919355A (en) * | 2017-08-14 | 2018-04-17 | 上海领矽半导体有限公司 | Ultra-low residual pressure is low to hold Transient Voltage Suppressor and its manufacture method |
| CN108110000A (en) * | 2017-12-29 | 2018-06-01 | 杭州士兰集成电路有限公司 | One-way low-capacitance TVS device and its manufacturing method |
Families Citing this family (1)
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| CN107204361B (en) * | 2017-05-22 | 2019-10-08 | 富芯微电子有限公司 | A kind of low-capacitance bidirectional TVS device and its manufacturing method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040135141A1 (en) * | 2003-01-09 | 2004-07-15 | International Business Machines Corporation | Electrostatic Discharge Protection Networks For Triple Well Semiconductor Devices |
| CN101853853A (en) * | 2009-03-31 | 2010-10-06 | 万国半导体有限公司 | The semiconductor controlled rectifier that has low electric capacity and forward drop and exhaust is as the Transient Voltage Suppressor of steering diode |
| CN101930975A (en) * | 2008-10-01 | 2010-12-29 | 万国半导体有限公司 | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (tvs) |
| US20110127577A1 (en) * | 2006-11-30 | 2011-06-02 | Madhur Bobde | Latch-up free vertical TVS diode array structure using trench isolation |
| CN102142370A (en) * | 2010-12-20 | 2011-08-03 | 杭州士兰集成电路有限公司 | Preparation method of diode chip on P+ substrate and structure of diode chip |
| CN102437156A (en) * | 2011-12-13 | 2012-05-02 | 杭州士兰集成电路有限公司 | Ultralow capacitance transient voltage suppression device and manufacturing method thereof |
| CN203445118U (en) * | 2013-09-16 | 2014-02-19 | 杭州士兰集成电路有限公司 | Integrated one-way ultra-low capacitance TVS device |
-
2013
- 2013-09-16 CN CN201310422745.2A patent/CN103474427B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040135141A1 (en) * | 2003-01-09 | 2004-07-15 | International Business Machines Corporation | Electrostatic Discharge Protection Networks For Triple Well Semiconductor Devices |
| US20110127577A1 (en) * | 2006-11-30 | 2011-06-02 | Madhur Bobde | Latch-up free vertical TVS diode array structure using trench isolation |
| CN101930975A (en) * | 2008-10-01 | 2010-12-29 | 万国半导体有限公司 | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (tvs) |
| CN101853853A (en) * | 2009-03-31 | 2010-10-06 | 万国半导体有限公司 | The semiconductor controlled rectifier that has low electric capacity and forward drop and exhaust is as the Transient Voltage Suppressor of steering diode |
| CN102142370A (en) * | 2010-12-20 | 2011-08-03 | 杭州士兰集成电路有限公司 | Preparation method of diode chip on P+ substrate and structure of diode chip |
| CN102437156A (en) * | 2011-12-13 | 2012-05-02 | 杭州士兰集成电路有限公司 | Ultralow capacitance transient voltage suppression device and manufacturing method thereof |
| CN203445118U (en) * | 2013-09-16 | 2014-02-19 | 杭州士兰集成电路有限公司 | Integrated one-way ultra-low capacitance TVS device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465723A (en) * | 2014-12-30 | 2015-03-25 | 北京燕东微电子有限公司 | Low-capacitance transient voltage restraint device and manufacturing method thereof |
| CN104465723B (en) * | 2014-12-30 | 2017-12-19 | 北京燕东微电子有限公司 | A kind of low capacitor transient stage voltage suppressor device and preparation method thereof |
| CN106783844A (en) * | 2017-01-25 | 2017-05-31 | 杭州士兰集成电路有限公司 | One-way low-capacitance TVS device and its manufacture method |
| CN106783844B (en) * | 2017-01-25 | 2023-09-01 | 杭州士兰集成电路有限公司 | Unidirectional low-capacitance TVS device and manufacturing method thereof |
| CN107170738A (en) * | 2017-05-22 | 2017-09-15 | 安徽富芯微电子有限公司 | A kind of unidirectional TVS device of low electric capacity and its manufacture method |
| CN107919355A (en) * | 2017-08-14 | 2018-04-17 | 上海领矽半导体有限公司 | Ultra-low residual pressure is low to hold Transient Voltage Suppressor and its manufacture method |
| CN107919355B (en) * | 2017-08-14 | 2023-09-19 | 上海领矽半导体有限公司 | Ultralow-residual-voltage low-capacity transient voltage suppressor and manufacturing method thereof |
| CN108110000A (en) * | 2017-12-29 | 2018-06-01 | 杭州士兰集成电路有限公司 | One-way low-capacitance TVS device and its manufacturing method |
| CN108110000B (en) * | 2017-12-29 | 2023-07-21 | 杭州士兰集成电路有限公司 | Unidirectional low-capacitance TVS device and manufacturing method thereof |
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