CN208111441U - Bidirectional low-capacitance TVS device - Google Patents
Bidirectional low-capacitance TVS device Download PDFInfo
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- CN208111441U CN208111441U CN201721895957.2U CN201721895957U CN208111441U CN 208111441 U CN208111441 U CN 208111441U CN 201721895957 U CN201721895957 U CN 201721895957U CN 208111441 U CN208111441 U CN 208111441U
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Abstract
A kind of bidirectional low-capacitance TVS device is disclosed, including：First conductivity type substrate；First conductive type epitaxial layer disposed thereon；The first conduction type buried layer, the second conduction type buried layer being located therein；The second conductive type epitaxial layer on the first conductive type epitaxial layer forms first area and second area through multiple isolation structures of the second conductive type epitaxial layer；The second conduction type well region in second area；The first conductivity type implanted region in first area and the second conduction type well region.Further, the first general-purpose diode and the first zener diode lontitudinal series that are formed in bidirectional low-capacitance TVS device and the second general-purpose diode and the second zener diode lontitudinal series, reduce the volume of bidirectional low-capacitance TVS device, capacitor can significantly be reduced, making the capacitor of power Vcc GND over the ground can achieve less than 0.9pF, and forward and reverse ESD ability can reach greater than 15kV.
Description
Technical field
The utility model relates to technical field of manufacturing semiconductors, in particular to a kind of bidirectional low-capacitance TVS device.
Background technique
Integrated bidirectional low-capacitance TVS device usually will be by the first general-purpose diode D1 and the first pressure stabilizing currently on the market
The connect first branch to be formed and the second general-purpose diode D2 of diode Z1 connects to be formed second with the second zener diode Z2
Branch circuit parallel connection combines to be formed (see Fig. 1), and from the point of view of power Vcc over the ground I~V curve of GND, positive and negative characteristic is still equivalent to one
A general-purpose diode, but the corresponding capacitor of equivalent circuit is well below the single general T VS diode of identical voltage.
Integrated bidirectional low-capacitance VTS device, the capacitance C of power Vcc GND over the groundTIt can be expressed as：
Wherein, CD1For the capacitor of the first general-purpose diode D1, CD1For the capacitor of the second general-purpose diode D2, CZ1It is first
The capacitor of zener diode Z1, CZ2For the capacitor of the second zener diode Z2.Here CD1And CD2It is all smaller, CZ1And CZ2Than preceding
The two is order of magnitude greater, thus the first general-purpose diode D1 connect with the first zener diode Z1 after first capacitor substantially etc.
It is same as the capacitor of the first general-purpose diode D1；Second general-purpose diode D2 connect with the second zener diode Z2 after the second capacitor
It is essentially identical to the capacitor of the second general-purpose diode D2.The capacitor of i.e. entire equivalent circuit is essentially identical to the first general-purpose diode
The sum of the capacitor of the capacitor of D1 and the second general-purpose diode D2.
When power Vcc plus positive potential, when ground GND adds negative potential：Since the second general-purpose diode D2 breakdown voltage is higher, the
One zener diode Z1 breakdown voltage is lower, so the first zener diode Z1 takes the lead in puncturing, power Vcc GND's over the ground is reversed
Breakdown voltage can be expressed as：
VBR=VfD1+VZ1
Wherein, VfD1For the forward voltage drop of the first general-purpose diode D1；VZ1 is the voltage of the first zener diode Z1.
When power Vcc plus negative potential, when ground GND adds positive potential：Since the second general-purpose diode D2 breakdown voltage is higher, the
Two zener diode Z2 breakdown voltages are lower, so the two the first zener diode Z1 take the lead in puncturing, power Vcc GND over the ground
Breakdown reverse voltage can be expressed as：
VBR=VfD2+VZ2
Wherein, VfD2For the forward voltage drop of the second general-purpose diode D2；VZ2 is the voltage of the second zener diode Z2.
It can be seen that the forward and reverse characteristic of bidirectional low-capacitance TVS device being composed substantially corresponds to common two-way two pole
Pipe, breakdown reverse voltage are mainly controlled by the breakdown voltage of the first zener diode Z1 and the second zener diode Z2；Capacitor
Mainly by CD1And CD2Control, so being actually exactly to reduce C to realize low capacitorD1And CD2；Power Vcc GND over the ground simultaneously
Practical positive and negative direction static discharge (Electrostatic Discharge, ESD) ability is also to be respectively equivalent to D1, D2 two
(breakdown reverse voltage of the first zener diode Z1 and the second zener diode Z2 are lower, generally for the positive ESD ability of diode
Between 3.3~7.0V, reversed ESD ability is very high, can not consider).So reality is just in order to realize high ESD ability
It is the positive ESD ability for improving two diodes of D1, D2.
The reason of bidirectional low-capacitance TVS device developed at present is limited by device architecture at that time and properties of product, chip ruler
It is very little relatively large, it is greater than 260 μm of 260 μ m, is unable to satisfy the compact package of DFN0603 etc.
Utility model content
In view of the above problems, two-way to reduce the purpose of this utility model is to provide a kind of bidirectional low-capacitance TVS device
The volume of low-capacitance TVS device.
It is according to the present utility model in a first aspect, providing a kind of bidirectional low-capacitance TVS device and including：
First conductivity type substrate；First conductive type epitaxial layer, first conductive type epitaxial layer are formed in described
In first conductivity type substrate；First conduction type buried layer, the first conduction type buried layer are formed in first conductive-type
In type epitaxial layer；Second conduction type buried layer, the second conduction type buried layer are formed on the first conduction type buried layer；
Second conductive type epitaxial layer, the second conduction type buried layer are formed on first conductive type epitaxial layer；It is multiple every
From structure, the multiple isolation structure runs through second conductive type epitaxial layer, and the multiple isolation structure is by described second
Conductive type epitaxial layer is divided into multiple regions, and the multiple region includes first area and second area；Second conductive type of trap
Area, the second conduction type well region are formed in the second area；First conductivity type implanted region, first conductive-type
Type injection region is formed in the first area and the second conduction type well region.
Preferably, the bidirectional low-capacitance TVS device further includes：Metal wire, in first area described in the metal wire
The first conductivity type implanted region in first conductivity type implanted region and the second area.
Preferably, the metal wire connects to power supply, and first conductivity type substrate is connected to ground.
Preferably, first conduction type is p-type, and second conduction type is N-type；Alternatively, described first is conductive
Type is N-type, and second conduction type is p-type.
Preferably, first conductivity type substrate is attached most importance to doped structure, and first conductive type epitaxial layer is gently to mix
Miscellaneous structure, the first conduction type buried layer are attached most importance to doped structure, and the second conduction type buried layer is attached most importance to doped structure, described
Second conductive type epitaxial layer is light-dope structure, and the second conduction type well region is attached most importance to doped structure, and described first is conductive
Type implanted region is attached most importance to doped structure.
Preferably, first conductivity type substrate is attached most importance to doped structure, and first conductive type epitaxial layer is gently to mix
Miscellaneous structure, the first conduction type buried layer are light-dope structure, and the second conduction type buried layer is attached most importance to doped structure, described
Second conductive type epitaxial layer is light-dope structure, and the second conduction type well region is attached most importance to doped structure, and described first is conductive
Type implanted region is attached most importance to doped structure.
Preferably, the resistivity of first conductivity type substrate is 0.005 Ω of Ω .cm~0.008 .cm.
Preferably, the resistivity of first conductive type epitaxial layer be the 2.0 Ω .cm of Ω .cm~4.0,6.0 μm of thickness~
14.0μm。
Preferably, the resistivity of second conductive type epitaxial layer 28 be the 25 Ω .cm of Ω .cm~35,6.0 μm of thickness~
12.0μm。
Preferably, the first conduction type buried layer includes that first injected in first conductive type epitaxial layer is led
Electric types of ion, the implantation dosage of first conductive type ion are 2.0E15~6.0E15.
Preferably, the first conduction type buried layer includes that first injected in first conductive type epitaxial layer is led
Electric types of ion, the implantation dosage of first conductive type ion are 1.0E14~8.0E14.
Preferably, the second conduction type buried layer includes the second conduction injected on the first conduction type buried layer
Types of ion, the implantation dosage of second conductive type ion are 6.0E15~1.0E16.
Preferably, the isolation structure includes groove and the polysilicon for filling groove, wherein the multiple groove runs through
Second conductive type epitaxial layer, the multiple groove extend in the first conductive type epitaxial layer, and the multiple groove will
Second conductive type epitaxial layer is divided into first area and second area.
Preferably, the depth of the groove is 10 μm~20 μm, and width is 1.5 μm~3 μm；The polysilicon with a thickness of
2.0 μm~3.5 μm.
Preferably, the second conduction type well region include the second conduction type for being injected in the second area from
Son, the implantation dosage of second conductive type ion are 5.0E14~1.0E14.
Preferably, first conductivity type implanted region include the first conduction type for being injected in the first area from
Son, the implantation dosage of first conductive type ion are 1.0E15~1.0E16.
Preferably, the first conductivity type implanted region in the first area and the second conductive type epitaxial layer constitute first
General-purpose diode；The first conduction type buried layer and the second conduction type buried layer in the first area constitute two pole of the first pressure stabilizing
Pipe；The second conductive type epitaxial layer and the first conductive type epitaxial layer in the second area constitute the second general-purpose diode；
The first conductivity type implanted region and the second conduction type well region in the second area constitute the second zener diode.
Preferably, when the power supply adds positive potential, adds negative potential describedly, reverse breakdown of the power supply to the ground
Voltage is：VBR=VfD1+VZ1, wherein VBRIt is the power supply to the breakdown reverse voltage on the ground；VfD1For the first common two pole
The forward voltage drop of pipe D1, VZ1For the voltage of the first zener diode.
Preferably, when the power supply adds negative potential, adds positive potential describedly, reverse breakdown of the power supply to the ground
Voltage is：VBR=VfD2+VZ2, wherein VfD2For the forward voltage drop of the second general-purpose diode D2, VZ2For the second zener diode
Voltage.
Bidirectional low-capacitance TVS device provided by the utility model forms bidirectional low-capacitance TVS by semiconductor integrated technique
Device is it is possible thereby to improve the reliability of bidirectional low-capacitance TVS device.
Further, the first general-purpose diode and the first zener diode formed in bidirectional low-capacitance TVS device is vertical
To series connection and the second general-purpose diode and the second zener diode lontitudinal series, the volume of bidirectional low-capacitance TVS device is reduced.
Bidirectional low-capacitance TVS device compared to the prior art can significantly reduce capacitor, make power Vcc GND over the ground
Capacitor can achieve less than 0.9pF, forward and reverse ESD ability can reach greater than 15kV.
Detailed description of the invention
By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model
, feature and advantage will be apparent from, in the accompanying drawings：
Fig. 1 shows the circuit diagram of existing bidirectional low-capacitance TVS device；
The manufacturing method that Fig. 2 to Figure 12 shows the bidirectional low-capacitance TVS device of an embodiment of the present invention is formed
Structure diagrammatic cross-section.
Specific embodiment
Hereinafter reference will be made to the drawings is more fully described the various embodiments of the utility model.In various figures, identical
Element is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not drawn to draw
System.
With reference to the accompanying drawings and examples, specific embodiment of the present utility model is described in further detail.
Fig. 2 to Figure 12 is please referred to, the manufacturing method for the bidirectional low-capacitance TVS device of the utility model embodiment is formed
Structure diagrammatic cross-section.More specifically, Fig. 2 to Figure 12 describes the shape of the bidirectional low-capacitance TVS device comprising SCR structure
At method.
In the embodiment of the present application, the manufacturing method of the bidirectional low-capacitance TVS device includes the following steps：
Step S10：First conductivity type substrate is provided；
Step S12：The first conductive type epitaxial layer is formed, it is conductive that first conductive type epitaxial layer is located at described first
In type substrates；
Step S14：The first conduction type buried layer is formed, the first conduction type buried layer is located at first conduction type
In epitaxial layer；
Step S16：The second conduction type buried layer is formed, the second conduction type buried layer is located at first wire type
On buried layer；
Step S18：The second conductive type epitaxial layer is formed, it is conductive that second conductive type epitaxial layer is located at described first
On type epitaxial layer；
Step S20：Multiple isolation structures are formed, the multiple isolation structure runs through second conductive type epitaxial layer,
Second conductive type epitaxial layer is divided into multiple regions by the multiple isolation structure, and the multiple region includes first area
And second area, the multiple isolation structure extend to first conductive type epitaxial layer；
Step S22：The second conduction type well region is formed, second conductive type of trap area is located in the second area；
Step S24：The first conductivity type implanted region is formed, first conductivity type implanted region is located at the first area
In the second area；
Step S26：Form metal wire, the metal wire connect the first conductivity type implanted region in the first area and
The first conductivity type implanted region in the second area；
Step S28：The metal wire is connected to power supply, first conductivity type substrate is connected to ground.
The first general-purpose diode D1 and the first zener diode Z1 will be formed in the first area as a result,；Institute
It states and forms the second general-purpose diode D2 and the second zener diode Z2 in second area.Specifically, in the first area
First conductivity type implanted region and the second conductive type epitaxial layer constitute the first general-purpose diode D1；In the first area
One conduction type buried layer and the second conduction type buried layer constitute the first zener diode Z1；Second in the second area is conductive
Type epitaxial layer and the first conductive type epitaxial layer constitute the second general-purpose diode D2；The first conductive-type in the second area
Type injection region and the second conduction type well region constitute the second zener diode Z2.
Wherein, first conduction type can be p-type, and second conduction type is N-type；Alternatively, described first leads
Electric type can be N-type, and second conduction type is p-type.It in the present embodiment, can be P with first conduction type
Type, second conduction type are further described for N-type.Wherein, the P-type conduction type can by doping boron ion or
Gallium ion etc. realizes that the N-type conduction type can be realized by doping phosphonium ion or antimony ion etc..
Firstly, as shown in Fig. 2, the first conductivity type substrate 20 is provided, here, namely first conductivity type substrate 20
For P type substrate.In the other embodiments of the application, first conductivity type substrate 20 or N-type substrate.
Preferably, the resistivity of first conductivity type substrate 20 is 0.005 Ω of Ω .cm~0.008 .cm.Preferably,
First conductivity type substrate 20 is attached most importance to doped structure, it is possible thereby to by between first conductivity type substrate 20 as connecing
The electrode of ground GND not only can reduce the size of chip, meet smaller without drawing ground connection GND electrode from front
The encapsulation of volume, and the multichannel product that thus structure extends can also be suitble to a variety of different packing forms, in addition encapsulate
The first conductivity type substrate of Shi Suoshu 20 is drawn directly as ground connection GND electrode, can be reduced to avoid the routing being grounded when encapsulating
Packaging cost.
Then, as shown in figure 3, forming the first conductive type epitaxial layer 22, institute in first conductivity type substrate 20
Stating the first conductive type epitaxial layer 22 is p-type epitaxial layer, can be generated by chemical vapor deposition method.In the present embodiment,
First conductive type epitaxial layer is light-dope structure, i.e., described in the doping concentration ratio of described first conductive type epitaxial layer 22
The doping concentration of first conductivity type substrate 20 is low.Preferably, the resistivity of first conductive type epitaxial layer 22 is 2.0
The Ω .cm of Ω .cm~4.0, with a thickness of 6.0 μm~14.0 μm.
As shown in figure 4, the first conduction type buried layer 24 is formed in first conductive type epitaxial layer 22, described first
Conduction type buried layer is p type buried layer.In the present embodiment, the first conduction type buried layer 24 is attached most importance to doped structure.Specifically,
The first conduction type buried layer 24 can be formed by following technique；First is injected in first conductive type epitaxial layer 22
Conductive type ion is herein boron ion, and the implantation dosage of the boron ion is 2.0E15~6.0E15；The boron ion is held
Row annealing process, the temperature of annealing process are 1100 DEG C~1250 DEG C；The time of annealing process is 2.0~6.0h.
Red in a preferred embodiment, the first conduction type buried layer 24 is light-dope structure.Specifically, can lead to
It crosses following technique and forms the first conduction type buried layer 24；Injection first is conductive in first conductive type epitaxial layer 22
Types of ion is herein boron ion, and the implantation dosage of the boron ion is 1.0E14~8.0E14；Boron ion execution is moved back
Fire process, the temperature of annealing process are 1100 DEG C~1250 DEG C；The time of annealing process is 2.0~6.0h.
As shown in figure 5, forming the second conduction type buried layer 26 on the first conduction type buried layer 24；Described second leads
Electric type buried layer is n type buried layer.In the present embodiment, the second conduction type buried layer 26 is attached most importance to doped structure.Specifically, may be used
The second conduction type buried layer 26 is formed by following technique；Injection first is conductive on the first conduction type buried layer 24
Types of ion is herein antimony ion, and the implantation dosage of the phosphonium ion is 6.0E15~1.0E16；Phosphonium ion execution is moved back
Fire process, the temperature of annealing process are 1000 DEG C~1150 DEG C；The time of annealing process is 2.0~4.0h.Described first is conductive
Type buried layer 24 and the second conduction type buried layer 26 constitute the first zener diode Z1, the first conduction type buried layer 24
Attach most importance to doped structure when, the first zener diode Z1 be 3.3~7.0V diode；The first conduction type buried layer 24 is light
When doped structure, the diode of first Z1 7.0V~18V of zener diode.
As shown in fig. 6, the second conductive type epitaxial layer 28 is formed on first conductive type epitaxial layer 22, described
Two conductive type epitaxial layers 28 are N-type epitaxy layer, can be generated by chemical vapor deposition method.In the present embodiment, described
Second conductive type epitaxial layer is light-dope structure, i.e., the doping concentration of described second conductive type epitaxial layer 28 is than described second
The doping concentration of conduction type buried layer 26 is low.Preferably, the resistivity of second conductive type epitaxial layer 28 be 25 Ω .cm~
35 Ω .cm, with a thickness of 6.0 μm~12.0 μm.
Then, as shown in figure 8, forming multiple isolation structures 32, the multiple isolation structure 32 is conductive through described second
Type epitaxial layer 28, the isolation structure 30 extend to first conductive type epitaxial layer 22, the multiple isolation structure 32
Second conductive type epitaxial layer 28 is divided for multiple regions, the multiple region includes first area 28a and second area
28b, wherein the second conductive type epitaxial layer and first conductive type epitaxial layer 22 in the second area 28b are constituted
Second general-purpose diode D2.Here, outside the second conductive type epitaxial layer of the second area 28b and first conduction type
The concentration for prolonging layer 22 is all very light, as long as doing certain selection to the second general-purpose diode D2 area, that is, can ensure that described second
The ultra-low capacitance of general-purpose diode D2 and high ESD ability.
In the embodiment of the present application, forming multiple isolation structures 32 includes：Forming multiple grooves 30 (can be accordingly with reference to figure
7), the multiple groove 30 is through second conductive type epitaxial layer 28 and the first conductive type epitaxial layer 22 (here, institute
Multiple grooves 30 are stated to also extend in the first conductivity type substrate 20), the multiple groove 30 will be outside second conduction type
Prolong layer 28 to divide for first area 28a and second area 28b；Polysilicon is filled in each groove 30, multiple isolation can be obtained
Structure 32.
Preferably, the depth of the groove 30 is 10 μm~20 μm, and width is 1.5 μm~3 μm.The thickness of the polysilicon
It is 2.0 μm~3.5 μm.In the present embodiment, it is isolated using groove, not only simple process, also can ensure that and be subsequently formed
There is no the structure of ghost effect, especially multichannel between each diode, to improve the reliable of bidirectional low-capacitance TVS device
Property.
Then, as shown in figure 9, forming the second conduction type well region 34 in the second area 28b.Implement in the application
In example, the second conduction type well region is attached most importance to doped structure.
Specifically, the second conduction type well region is formed in the second area 28b by the following method：Described second
Inject the second conductive type ion in the 28b of region, be herein phosphonium ion, the implantation dosage of the phosphonium ion be 5.0E14~
1.0E14 executes annealing process to the phosphonium ion, and the temperature of annealing process is 900 DEG C~1050 DEG C；The time of annealing process
For 30~60min.Wherein, which may insure to form good ohmic contact.
Then, as shown in Figure 10, the first conductivity type implanted region is formed in the first area and the second area.
Here, first in the first conductivity type implanted region 36a and the second area 28b in the respectively described first area 28a
Conductivity type implanted region 36b.The first conductivity type implanted region 36a and the second conduction type extension in the first area 28a
Layer 28 constitutes the first conductivity type implanted region 36b and the second conductive-type in the first general-purpose diode D1, the second area 28b
Type well region 34 constitutes the second zener diode Z1.
Specifically, the first conductivity type implanted region is formed in first area and the second area by the following method：
The first conductive type ion is injected in the first area 28a and the second area 28b, is herein boron ion, the boron
The implantation dosage of ion is 1.0E15~1.0E16, executes annealing process to the boron ion, the temperature of annealing process is 800 DEG C
~900 DEG C；The time of annealing process is 30~60min.
In the embodiment of the present application, first conductivity type implanted region is attached most importance to doped structure.Here, the first area
The concentration of the second conductive type epitaxial layer in 28a is very light, as long as the first conductivity type implanted region in the first area 28a
The area of 36a does certain selection, that is, can ensure that the first general-purpose diode D1 ultra-low capacitance and high ESD ability.
Due to the first general-purpose diode D1 in the first area 28a and the first zener diode Z1 lontitudinal series and
The second general-purpose diode D2 and the second zener diode Z1 lontitudinal series in the second area 28b are saved area, are made two-way
The area control of low-capacitance TVS chip is within 220 μm of 220 μ m.
Then, as shown in figure 12, metal wire 40 is formed, the metal wire 40 connects the first general-purpose diode D1 and the
Two zener diode Z2.Specifically, it can refer to Figure 11, form dielectric layer 38, institute on second conductive type epitaxial layer 28
It states dielectric layer 38 and exposes the first general-purpose diode D1 and the second zener diode Z2；Then, it can refer to Figure 12, by evaporating or splashing
Metal layer is penetrated, metal wire 40 is formed.Normally, the material of the metal layer is aluminium, and thickness can be 2.0 μm.
In the present embodiment, the metal wire 40 is connect with power Vcc, first conductivity type substrate 20 and ground
GND connection.Electrode between i.e. described first conductivity type substrate 20 as ground connection GND connects without the extraction from front
Ground GND electrode, not only can reduce the size of chip, meet the encapsulation of smaller volume, when in addition encapsulating described in first lead
Electric type substrates 20 are drawn directly as ground connection GND electrode, it is possible to reduce 1 wires, greatly reduction packaging cost.It is preferred that
The capacitor on ground, power Vcc GND over the ground can achieve less than 0.9pF, and forward and reverse ESD ability can reach greater than 15kV.
Further, it can also be formed passivation layer (being not shown in Figure 12).The passivation layer covers second conduction type
Epitaxial layer 28.The structure in bidirectional low-capacitance TVS device is protected by the passivation layer, to improve the bidirectional low-capacitance
The quality and reliability of TVS device.Normally, the material of the passivation layer is silicon nitride, and thickness can be 1.0 μm.
Please continue to refer to Figure 12, following two-way low electricity is formd by the manufacturing method of above-mentioned bidirectional low-capacitance TVS device
Hold TVS device, specifically includes：
First conductivity type substrate 20；
First conductive type epitaxial layer 22, first conductive type epitaxial layer 22 are formed in the first conduction type lining
On bottom 20；
First conduction type buried layer 24, the first conduction type buried layer 24 are formed in first conductive type epitaxial layer
In 22；
Second conduction type buried layer 26, the second conduction type buried layer 26 are formed in the first conduction type buried layer 24
On；
Second conductive type epitaxial layer 28, the second conduction type buried layer 28 are formed in the first conduction type extension
On layer 22；
Multiple isolation structures 32, the multiple isolation structure 32 is through second conductive type epitaxial layer 28 and described
First conductive type epitaxial layer 22, the multiple isolation structure 32 divide second conductive type epitaxial layer 28 for multiple areas
Domain, the multiple region include first area 28a and second area 28b, wherein second in the second area 28b is conductive
Type epitaxial layer 28 and first conductive type epitaxial layer 22 constitute the second general-purpose diode D2；
Second conduction type well region, the second conduction type well region 34 are formed in second area 28b.
First conductivity type implanted region, first conductivity type implanted region are formed in the first area 28a and described
In second area 28b.Here, the first conductivity type implanted region 36a and secondth area in the respectively described first area 28a
The first conductivity type implanted region 36b in the 28b of domain.The first conductivity type implanted region 36a and second in the first area 28a
Conductive type epitaxial layer 28 constitutes the first conductivity type implanted region 36b in the first general-purpose diode D1, the second area 28b
The second zener diode Z1 is constituted with the second conduction type well region 34.
Metal wire 40, the metal wire 40 connect the first conductivity type implanted region 36a and institute in the first area 28a
State the first conductivity type implanted region 36b in second area 28b.The i.e. described metal wire 40 connects the first general-purpose diode D1
With the second zener diode Z2.
Wherein, the metal wire 40 is connect with power Vcc, and first conductivity type substrate 20 is connect with ground GND.
Here, the resistivity of first conductivity type substrate 20 is 0.005 Ω of Ω .cm~0.008 .cm.Described first
The resistivity of conductive type epitaxial layer 22 is 2.0 Ω of Ω .cm~4.0 .cm.The resistivity of second conductive type epitaxial layer 28
For 25 Ω of Ω .cm~35 .cm.The isolation structure 32 includes the polysilicon of groove and the filling groove.
To sum up, in bidirectional low-capacitance TVS device provided by the embodiment of the utility model, work is integrated by semiconductor
Skill forms bidirectional low-capacitance TVS device it is possible thereby to improve the reliability of bidirectional low-capacitance TVS device.Further, two-way
The first general-purpose diode and the first zener diode lontitudinal series that are formed in low-capacitance TVS device and the second general-purpose diode
With the second zener diode lontitudinal series, the volume of bidirectional low-capacitance TVS device is reduced.Two-way low electricity compared to the prior art
Capacitor can significantly be reduced by holding TVS device, can achieve the capacitor of power Vcc GND over the ground less than 0.9pF, forward and reverse
ESD ability can reach greater than 15kV.
It is as described above according to the embodiments of the present invention, these embodiments details all there is no detailed descriptionthe,
Also not limiting the utility model is only the specific embodiment.Obviously, as described above, many modification and change can be made
Change.These embodiments are chosen and specifically described to this specification, is in order to preferably explain the principles of the present invention and actually to answer
With so that skilled artisan be enable to utilize the utility model and repairing on the basis of the utility model well
Change use.The utility model is limited only by the claims and their full scope and equivalents.
Claims (18)
1. a kind of bidirectional low-capacitance TVS device, which is characterized in that including：
First conductivity type substrate；
First conductive type epitaxial layer, first conductive type epitaxial layer are formed in first conductivity type substrate；
First conduction type buried layer, the first conduction type buried layer are formed in first conductive type epitaxial layer；
Second conduction type buried layer, the second conduction type buried layer are formed on the first conduction type buried layer；
Second conductive type epitaxial layer, second conductive type epitaxial layer are formed on first conductive type epitaxial layer；
Multiple isolation structures, the multiple isolation structure run through second conductive type epitaxial layer, the multiple isolation structure
Second conductive type epitaxial layer is divided into multiple regions, the multiple region includes first area and second area；
Second conduction type well region, the second conduction type well region are formed in the second area；
First conductivity type implanted region, first conductivity type implanted region are formed in the first area and second conduction
In type well region.
2. bidirectional low-capacitance TVS device according to claim 1, which is characterized in that further include：
Metal wire, the metal wire connect in the first conductivity type implanted region and the second area in the first area
First conductivity type implanted region.
3. bidirectional low-capacitance TVS device according to claim 2, which is characterized in that the metal wire connects to power supply, institute
The first conductivity type substrate is stated to be connected to ground.
4. bidirectional low-capacitance TVS device according to any one of claim 1-3, which is characterized in that described first is conductive
Type is p-type, and second conduction type is N-type；Alternatively, first conduction type is N-type, second conduction type is
P-type.
5. bidirectional low-capacitance TVS device according to claim 4, which is characterized in that first conductivity type substrate is
Heavy doping structure, first conductive type epitaxial layer are light-dope structure, and the first conduction type buried layer is heavy doping knot
Structure, the second conduction type buried layer are attached most importance to doped structure, and second conductive type epitaxial layer is light-dope structure, and described the
Two conduction type well regions are attached most importance to doped structure, and first conductivity type implanted region is attached most importance to doped structure.
6. bidirectional low-capacitance TVS device according to claim 4, which is characterized in that first conductivity type substrate is
Heavy doping structure, first conductive type epitaxial layer are light-dope structure, and the first conduction type buried layer is that knot is lightly doped
Structure, the second conduction type buried layer are attached most importance to doped structure, and second conductive type epitaxial layer is light-dope structure, and described the
Two conduction type well regions are attached most importance to doped structure, and first conductivity type implanted region is attached most importance to doped structure.
7. bidirectional low-capacitance TVS device according to claim 4, which is characterized in that first conductivity type substrate
Resistivity is 0.005 Ω of Ω .cm~0.008 .cm.
8. bidirectional low-capacitance TVS device according to claim 4, which is characterized in that first conductive type epitaxial layer
Resistivity be the 2.0 Ω .cm of Ω .cm~4.0,6.0 μm~14.0 μm of thickness.
9. bidirectional low-capacitance TVS device according to claim 4, which is characterized in that second conductive type epitaxial layer
Resistivity be the 25 Ω .cm of Ω .cm~35,6.0 μm~12.0 μm of thickness.
10. bidirectional low-capacitance TVS device according to claim 5 or 6, which is characterized in that first conduction type buries
Layer includes the first conductive type ion injected in first conductive type epitaxial layer.
11. bidirectional low-capacitance TVS device according to claim 5 or 6, which is characterized in that second conduction type buries
Layer includes the second conductive type ion injected on the first conduction type buried layer.
12. bidirectional low-capacitance TVS device according to claim 5 or 6, which is characterized in that the isolation structure includes more
The polysilicon of a groove and the multiple grooves of filling, wherein the multiple groove runs through second conductive type epitaxial layer, institute
It states multiple grooves to extend in the first conductive type epitaxial layer, second conductive type epitaxial layer is divided by the multiple groove
First area and second area.
13. bidirectional low-capacitance TVS device according to claim 12, which is characterized in that the depth of the groove is 10 μm
~20 μm, width is 1.5 μm~3 μm；The polysilicon with a thickness of 2.0 μm~3.5 μm.
14. bidirectional low-capacitance TVS device according to claim 5 or 6, which is characterized in that second conductive type of trap
Area includes the second conductive type ion injected in the second region.
15. bidirectional low-capacitance TVS device according to claim 5 or 6, which is characterized in that the first conduction type note
Entering area includes the first conductive type ion injected in the first area.
16. bidirectional low-capacitance TVS device according to claim 3, which is characterized in that first in the first area
Conductivity type implanted region and the second conductive type epitaxial layer constitute the first general-purpose diode；First in the first area is conductive
Type buried layer and the second conduction type buried layer constitute the first zener diode；The second conduction type extension in the second area
Layer constitutes the second general-purpose diode with the first conductive type epitaxial layer；The first conductivity type implanted region in the second area with
The second conduction type well region constitutes the second zener diode.
17. bidirectional low-capacitance TVS device according to claim 16, which is characterized in that when the power supply adds positive potential, institute
When adding negative potential with stating, the power supply is to the breakdown reverse voltage on the ground：VBR=VfD1+VZ1, wherein VBRFor the power supply
To the breakdown reverse voltage on the ground；VfD1For the forward voltage drop of the first general-purpose diode D1, VZ1For the first zener diode
Voltage.
18. bidirectional low-capacitance TVS device according to claim 16, which is characterized in that when the power supply adds negative potential, institute
When adding positive potential with stating, the power supply is to the breakdown reverse voltage on the ground：VBR=VfD2+VZ2, wherein VfD2It is common for second
The forward voltage drop of diode D2, VZ2For the voltage of the second zener diode.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110379800A (en) * | 2019-07-31 | 2019-10-25 | 中国振华集团永光电子有限公司（国营第八七三厂） | A kind of two-way low junction capacity TVS diode of ceramic paster encapsulation |
| CN111463291A (en) * | 2019-01-18 | 2020-07-28 | 徐州市晨创电子科技有限公司 | Bidirectional TVS diode and preparation method thereof |
-
2017
- 2017-12-29 CN CN201721895957.2U patent/CN208111441U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111463291A (en) * | 2019-01-18 | 2020-07-28 | 徐州市晨创电子科技有限公司 | Bidirectional TVS diode and preparation method thereof |
| CN110379800A (en) * | 2019-07-31 | 2019-10-25 | 中国振华集团永光电子有限公司（国营第八七三厂） | A kind of two-way low junction capacity TVS diode of ceramic paster encapsulation |
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