CN104124276B - Super junction device and manufacturing method thereof - Google Patents

Super junction device and manufacturing method thereof Download PDF

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CN104124276B
CN104124276B CN201410392143.1A CN201410392143A CN104124276B CN 104124276 B CN104124276 B CN 104124276B CN 201410392143 A CN201410392143 A CN 201410392143A CN 104124276 B CN104124276 B CN 104124276B
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CN104124276A (en
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肖胜安
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Shenzhen Shangyangtong Technology Co ltd
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Shenzhen Sanrise Tech Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

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Abstract

The invention discloses a super junction semiconductor device and a manufacturing method thereof. The impurity concentrations of the same type in the adjacent two sections of P-N thin layers which are alternately arranged can be equal or unequal; the arrangement mode of the P-N thin layers in one step length of the alternately arranged P-N thin layers of one section of the two adjacent sections of alternately arranged P-N thin layers can be the same as or different from the arrangement mode of the P-N thin layers in one step length of the alternately arranged P-N thin layers of the other section adjacent to the alternately arranged P-N thin layers; the total amount of the P-type impurities and the total amount of the N-type impurities of the P-N thin layers which are alternately arranged at the same section can be equal or unequal; the invention can reduce the processing difficulty of the alternately arranged P-N thin layers, improve the consistency of the device performance, and improve the current impact resistance, the voltage impact resistance and the flexibility of the device design. The invention also discloses a manufacturing process of the device.

Description

Super junction device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a structure of a super junction high-voltage device and a manufacturing method of the super junction high-voltage device.
Background
A super-junction Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) adopts a novel voltage-resistant layer structure, and a series of alternately arranged P-type Semiconductor thin layers and N-type Semiconductor thin layers are utilized to deplete the P-type Semiconductor thin layers and the N-type Semiconductor thin layers under low voltage in a cut-off state, so that mutual charge compensation is realized, high reverse breakdown voltage can be realized for the P-type Semiconductor thin layers and the N-type Semiconductor thin layers under high doping concentration, low on-resistance and high breakdown voltage can be obtained at the same time, and the theoretical limit of the traditional power MOSFET is broken. In US patent US5216275, the above alternating P-type and N-type semiconductor thin layers are connected to an N + substrate; in US6630698B1, the intermediate thin layers of P-type and N-type semiconductors may be spaced from the N + substrate by more than 0.
In the prior art, one of the formation of the P-type semiconductor thin layer and the N-type semiconductor thin layer is to repeat the process for a plurality of times to obtain the P-type semiconductor thin layer and the N-type semiconductor thin layer with required thicknesses by epitaxial growth and then photoetching and implantation, and the process is generally repeated for more than 5 times in the MOSFET with the voltage of more than 600V, so that the production cost is high and the production period is long. The other method is that after one type of epitaxy with required thickness is grown at one time, the etching of a groove is carried out, and then the groove is filled with silicon of the opposite type; after the groove structure is adopted, the doping concentration of the P/N thin layers, namely the P type semiconductor thin layers and the N type semiconductor thin layers in the P type semiconductor thin layers and the N type semiconductor thin layers which are alternately arranged in the longitudinal direction is easy to control, and the additional longitudinal electric field is brought because the doping concentration of the P type semiconductor thin layers and the N type semiconductor thin layers or one of the P type semiconductor thin layers and the N type semiconductor thin layers in the thin layers is changed in the longitudinal direction due to multiple epitaxial processes, so that the device can obtain good leakage characteristics and high breakdown voltage. The method has the effects of simplifying the process flow and improving the stability, but has great process difficulty.
Fig. 1 is a schematic top view of a conventional super junction device. The device comprises a region 1, a region 2 and a region 3, wherein the region 1 is a current flow region of the super junction device, and the current flow region comprises a plurality of current flow region grooves which are arranged in parallel. And the region 2 and the region 3 form a terminal protection structure of the super junction device, do not provide current when the super junction device is switched on, and bear voltage from the region 1 to the outermost end of the super junction device in a reverse cut-off state. Said 2 and 3 regions both surround the periphery of said current flow region, wherein said 2 region is adjacent to said 1 region, said 2 region comprises at least one P-type ring 24, and at least one trench ring 23, said P-type ring 24 covers at least one of said trench rings 23; the 3-region includes at least one trench ring 23 and a channel stop ring 21. The trench ring 23 has a square structure, and an additional trench 22 is formed at each of four corners of the trench ring 23, and the additional trench 22 is used for charge balance compensation.
Fig. 2 is a schematic cross-sectional view of a conventional super junction device, which is a cross-sectional view taken along direction AA' shown in fig. 1. An N-type silicon epitaxial layer 2 is formed on an N + silicon substrate, a plurality of grooves 41 are formed in the N-type silicon epitaxial layer 2, and the grooves 41 comprise a current flowing area groove 25, a groove ring 23 and an accessory groove 22 shown in FIG. 1; the trenches 41 are filled with P-type silicon 51, the P-type silicon 51 and the N-type epitaxial layer form an alternating arrangement of P-type silicon thin layers and N-type epitaxial layer thin layers, and one P-type silicon 51 and an adjacent N-type epitaxial layer (the N-type epitaxial layer disposed between two adjacent trenches) form a repeating unit of the alternating arrangement of P-N thin layers, which is referred to as a step size. A P-type well 62 is formed in the P-type silicon 51 and the N-type epitaxial layer of the trench 41 in the 1 region, i.e., the upper portion of the current flow region trench 25, while the P-type well 24 is formed in the P-type silicon 51 and the N-type epitaxial layer of the first trench 41 in the 2 region, i.e., the upper portion of the first trench ring 23, adjacent to the 1 region; the number of P-type rings 24 is at least one, and the P-type rings are generally connected together with the P-type wells. A source region 6 formed by N + ion implantation is formed in the P-type well, and the channel stop ring 21 is formed on the upper part of the N-type epitaxial layer on the outermost side of the region 3. The region 1 further comprises a P + ohmic contact region 63 formed by P + ion implantation, a gate oxide 4, a polysilicon gate 5, an interlayer dielectric film 7, a contact hole 8, a source electrode and a gate electrode (two electrodes after patterning of metal 9), and a drain electrode 10 is formed at the bottom of the N + silicon substrate. When the super junction device is turned on, current can reach a drain electrode from a source electrode through a channel and the N-type epitaxial layer thin layer, and the P-type silicon thin layer in the current flowing region groove 25 and the N-type epitaxial layer thin layer form a depletion region together to bear voltage in a reverse cut-off state.
An innermost field plate 43 is formed on the top of the epitaxial layer 2 in the region 2, the innermost field plate 43 is a metal field plate formed by surface metal, the innermost field plate is isolated from the epitaxial layer 2 by the terminal dielectric layer, the inner side end of the innermost field plate 43 is formed on the outermost polysilicon gate 5 and forms contact, the innermost field plate 43 is connected with the gate, and the terminal dielectric layer is formed by a first dielectric layer 66 and a second dielectric layer 69. A plurality of mutually isolated outer field plates are formed on the top of the epitaxial layer 2 in the region 3, the outer field plates are metal field plates, and the outermost field plates are isolated from the epitaxial layer 2 through the dielectric layer I66; the 3 region can be provided with or without a P-shaped ring; the outermost end of the 3 region is provided with the channel stop ring 21 which is composed of an N + doped ring. And the 2 region and the 3 region both belong to the terminal protection structure region, do not provide current when the super junction device is switched on, and are used for bearing voltage from the 1 region to the outermost end of the super junction device in a reverse cut-off state.
Taking a reverse breakdown voltage 600-1000V super junction NMOSFET, the thickness of the required P-N thin layer is 35-70 microns, taking the width of the trench 41 as 5 microns (generally between 2-7 microns) as an example, the aspect ratio of the trench 41 is 7-12. The trench which is deep and has a high aspect ratio needs to complete defect-free epitaxial filling at one time, the process difficulty is very high, meanwhile, the trench with the depth of 35-70 microns is etched at one time, the difficulty is high, and the uniformity of the trench cannot meet the requirement of the performance consistency of a device easily: assuming that the uniformity of the etching depth on the same silicon wafer is controlled within 5% (the uniformity is the maximum value of the depth difference in the silicon wafer divided by the sum of the maximum depth and the minimum depth in the silicon wafer), the variation range of the depth reaches 3.5-7 microns, and the difference of the brought reverse breakdown voltage is 30-100 volts or even more than 100 volts, so the realization process of the existing device structure has great difficulty and the non-uniformity of the device is great.
In the above prior art of trench filling, since the P-N thin layer is formed by one trench etching and filling, the trenches in the termination region (regions 2 and 3) are generally designed as the trenches in the charge flow region, which limits the flexibility of device design.
Disclosure of Invention
The invention aims to solve the technical problem of providing a novel structure of a high-voltage super-junction semiconductor device, and further provides a manufacturing method of the technical method of the structure of the super-junction semiconductor device, so that the difficulty of a P-N thin layer forming process can be effectively reduced, the uniformity of the P-N thin layer is improved, the performance of the device is improved, and the flexibility of the design of the device is increased.
In order to solve the technical problem, the invention provides a super-junction semiconductor device structure, wherein the alternately arranged P-N thin layers are formed by at least two alternately arranged P-N thin layers in the direction vertical to the surface of the device; between the adjacent alternately arranged P-N thin layers of different sections, the width of the P thin layer in the alternately arranged P-N thin layers of one section can be equal to or unequal to the width of the P thin layer in the alternately arranged P-N thin layers of the other section adjacent to the P thin layer; the width of the N thin layers in the P-N thin layers which are alternately arranged in one section can be equal to or unequal to the width of the N thin layers in the P-N thin layers which are alternately arranged in the other section adjacent to the one section; the arrangement mode of the P-N thin layers in one step length in the P-N thin layers which are alternately arranged in one section can be the same as or different from the arrangement mode of the P-N thin layers in one step length in the P-N thin layers which are alternately arranged in the other section adjacent to the P-N thin layers; the concentration of the P-type impurities in the P thin layers in one section of the alternately arranged P-N thin layers can be equal to or unequal to the concentration of the P-type impurities in the P thin layers in the other section of the alternately arranged P-N thin layers adjacent to the P-type impurities; the concentration of the N-type impurities in the N thin layers in one section of the P-N thin layers which are alternately arranged can be equal to or unequal to the concentration of the N-type impurities in the N thin layers in the other section of the P-N thin layers which are alternately arranged adjacent to the N thin layers;
in a further refinement, between adjacent alternating P-N layers of different segments, the width of the P layer of one segment of alternating P-N layers is greater than the width of the P layer of another segment of alternating P-N layers adjacent thereto that is located closer to the front surface of the device than it is.
In a further improvement, the thickness of the alternating P-N layers closest to the back surface of the device is less than or equal to 20 microns.
In a further improvement, the concentration of N type impurities in the N layers of one of the alternating P-N layers closest to the back surface of the device is less than the concentration of N type impurities in the N layers of the adjacent alternating P-N layers located closer to the front surface of the device than the other.
The further improvement is that the P type impurities in the P thin layer of a section of alternately arranged P-N thin layers closest to the back surface of the device are less than the total amount of the N type impurities in the N thin layer; the P type impurity in the P thin layer is larger than the total amount of the N type impurity in the N thin layer.
In a further refinement, the width of the P layers of one of the alternating P-N layers closest to the back surface of the device is less than the width of the P layers of the adjacent alternating P-N layers located closer to the front surface of the device than the P layers of the other of the alternating P-N layers.
In a further improvement, the concentration of N type impurities in the N layers of one of the alternating P-N layers closest to the back surface of the device is greater than the concentration of N type impurities in the N layers of the adjacent alternating P-N layers located closer to the front surface of the device than the other alternating P-N layers.
A further improvement is that the arrangement of P-N layers in one step in one alternating segment of P-N layers closest to the back surface of the device is different from the arrangement of P-N layers in one step in an alternating segment of P-N layers adjacent to it and located closer to the front surface of the device than it is.
The first manufacturing method for realizing the super junction device structure provided by the invention comprises the following process steps:
step one, growing a first epitaxial layer of a first type of semiconductor on a high-concentration first type of semiconductor substrate;
step two, forming a first groove with a certain height-width ratio on the first epitaxial layer through photoetching;
filling first silicon of a second type of semiconductor into the first groove;
and step four, obtaining the first section of alternately arranged P-N thin layers by utilizing chemical mechanical grinding.
Step five, the method comprises the following sub-steps:
1. growing a second epitaxial layer of the first type of semiconductor on the first section of the alternately arranged P-N thin layers;
2. forming a second groove by adopting a photoetching process, wherein the bottom of the second groove is contacted with or penetrates through the top of the first groove;
3. filling second silicon of a second type of semiconductor into the second trench;
4. chemical mechanical grinding is adopted to obtain a second section of alternately arranged P-N thin layers which are superposed on the first section of alternately arranged P-N thin layers
And then, repeatedly implementing the sub-steps 1, 2, 3 and 4 of the step five until the thickness of the P-N thin layer meets the requirement of the reverse breakdown voltage of the device.
The second manufacturing method for realizing the super junction device structure provided by the invention comprises the following process steps:
step one, growing a first epitaxial layer with high resistivity on a first type of high-concentration semiconductor substrate;
and step two, forming a first type semiconductor thin layer on the epitaxial layer through photoetching and first type semiconductor ion implantation.
And step three, forming a second type semiconductor thin layer on the epitaxial layer through photoetching and second various types of semiconductor ion implantation. The first type semiconductor thin layers and the second type semiconductor thin layers are alternately arranged in a chip current flowing area to form a first section of alternately arranged P-N thin layers.
Step four, the method comprises the following sub-steps:
1. carrying out second epitaxial layer growth of the first type of semiconductor on the first section of alternately arranged P-N thin layers formed in the first to third steps;
2. forming a first groove by adopting a photoetching process, wherein the bottom of the first groove is contacted with or penetrates through the top of the P-type thin layers on the P-N thin layers which are alternately arranged on the first section and are formed in the first to third steps;
3. filling silicon of a second type of semiconductor into the first trench;
4. and obtaining a second section of alternately arranged P-N thin layers which are superposed on the first section of alternately arranged P-N thin layers by adopting chemical mechanical grinding.
And then, repeatedly implementing the sub-steps 1, 2, 3 and 4 of the step four until the thickness of the P-N thin layer meets the requirement of the reverse breakdown voltage of the device.
The first and second manufacturing methods for realizing the super junction device structure further comprise the following steps:
step 1, forming a well of a second type of semiconductor on the surface of the P-N thin layer through photoetching and injection;
and 2, forming gate oxide on the surface of the P-N thin layer through thermal oxidation, then depositing polycrystalline silicon or amorphous silicon of the first type of semiconductor, and forming a gate region through photoetching.
Step 3, performing ion implantation of a source region of the first type of semiconductor through photoetching and ion implantation to form a source region;
step 4, growing an interlayer film on the surface of the front side of the silicon wafer;
step 5, carrying out contact hole photoetching;
step 6, utilizing impurity ion implantation of the high-energy second type semiconductor to realize ohmic connection between metal in the contact hole and the second type semiconductor well;
step 7, forming a source electrode and a polysilicon gate wire on the surface of the front surface of the silicon wafer through metal growth, photoetching and etching;
and 8, thinning the back of the silicon wafer and metalizing the back to form the drain electrode.
The invention adopts at least two sections of alternately arranged P-N thin layer structures, reduces the thickness of each alternately arranged P-N thin layer, reduces the height-width ratio, reduces the process difficulty of the alternately arranged P-N thin layers, improves the uniformity of the P-N thin layers and improves the consistency of the device performance.
The invention adopts at least two sections of alternately arranged P-N thin layer structures, and can independently design the structure of each section of P-N thin layer under the condition of integrally considering the charge balance of the P-N thin layer, thereby facilitating the design of the device structure.
The invention adopts at least two sections of alternately arranged P-N thin layer structures, can enable the reverse breakdown point of the device to occur in the current flowing region but not in the terminal region of the device by optimizing the distribution of impurities in the P-N thin layers, can improve the voltage resistance and the current overshoot resistance of the device, and improves the reliability of the device.
The invention adopts at least two sections of alternately arranged P-N thin layer structures, and can conveniently adopt the alternately arranged P-N thin layers different from the current flowing region in the terminal region of the device, thereby facilitating the design of the terminal structure of the device.
Drawings
The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
FIG. 1 is a schematic top view of a prior art super junction device
FIG. 2 is a schematic cross-sectional view of a prior art super junction device
FIGS. 3-7 are schematic diagrams of embodiments of the present invention
FIG. 3 is a schematic diagram of a device structure of a current flowing region according to a first embodiment of the invention
FIG. 4 is a schematic diagram of a device structure of a current flow region according to a second embodiment of the present invention
FIG. 5 is a schematic diagram of a device structure in a current flow region according to a third embodiment of the present invention
FIG. 6 is a schematic diagram of a device structure of a current flowing region according to a fourth embodiment of the present invention
FIG. 7 is a schematic diagram of a device structure in a current flow region according to a fifth embodiment of the present invention
Detailed Description
In the following embodiments, a super junction NMOSFET device with a drain-source reverse breakdown voltage of 700 v is used as an example for specific description, so that the first type of semiconductor is an N-type semiconductor and the second type of semiconductor is a P-type semiconductor.
Example one
Referring to fig. 3, a schematic diagram of a charge flow region device structure according to a first embodiment of the present invention is shown. An N-type silicon epitaxial layer 1 is formed on an N-type silicon substrate 01 with low resistivity, the resistivity of the N-type silicon substrate 01 is 0.001-0.005 ohm-cm, the thickness is 0.2-750 micrometers, the resistivity of the N-type silicon epitaxial layer 1 is 1-5 ohm-cm (phosphorus or arsenic is doped, the concentration is 4.83E 15-8.95E 14 atoms/cubic cm), and the N-type silicon epitaxial layer 1 can be composed of epitaxial layers with different resistivities or can be an epitaxial layer with single resistivity. In the N-type silicon epitaxial layer 1, there are first P-N thin layers arranged alternately, the thickness T1 of the first P-N thin layers arranged alternately is 15 micrometers, wherein 33 is a P-type thin layer in the first P-N thin layers, each P-type thin layer 33 has a width of 5 micrometers and a resistivity of 2.83 ohm-cm (boron doping, impurity concentration of 4.83E15 atomic number/cubic cm), 43 is an N-type thin layer in the first P-N thin layers arranged alternately, each N-type thin layer 43 has a width of 5 micrometers and a resistivity of 1 ohm-cm (phosphorus doping, impurity concentration of 4.83E15 atomic number/cubic cm), and one P-type thin layer 33 and an adjacent N-type thin layer 43 constitute a step. And a second section of alternately arranged P-N thin layers is arranged above the first section of alternately arranged P-N, the thickness T2 of the second section of alternately arranged P-N thin layers is 25 micrometers, wherein 34 is a P type thin layer in the second section of alternately arranged P-N thin layers, each P type thin layer 34 is 5 micrometers in width and 2.83 ohms per centimeter (boron doping, impurity concentration of 4.83E15 atomic number/cubic centimeter), 44 is an N type thin layer in the second section of alternately arranged P-N thin layers, each N type thin layer 44 is 5 micrometers in width and 1 ohm per centimeter (phosphorus doping, impurity concentration of 4.83E15 atomic number/cubic centimeter), and one P type thin layer 34 and an adjacent N type thin layer 44 form a step length. The thickness of an N-type silicon epitaxial layer 1 between the bottom of the first section of alternately arranged P-N thin layers and the N-type silicon substrate 01 with low resistivity is 2-10 micrometers, and the resistivity is 1-5 ohm.
The width of the P thin layer and the N thin layer and the impurity concentration in the P thin layer and the N thin layer are selected, the total amount of P type impurities in the P thin layer of each P-N middle thin layer which is alternately arranged is equal to the total amount of N type impurities in the N thin layer, perfect charge balance is realized, and therefore the device can obtain the highest reverse breakdown voltage. In the actual device design and manufacture, the widths of the P thin layer and the N thin layer and the impurity concentration in the P thin layer and the N thin layer are changed within a certain range, and as long as the absolute value of the difference between the total amount of P type impurities in the P thin layer and the total amount of N type impurities in the N thin layer in the whole P-N thin layer (the sum of two P-N thin layers which are alternately arranged) is less than or equal to 15% of the total amount of P type impurities in the P thin layer and less than or equal to 15% of the total amount of N type impurities in the N thin layer, higher reverse breakdown voltage can still be obtained.
And a P-type well 62 is formed at the upper part of the thin layers in the P-N alternately arranged in the second section, namely in an epitaxial region close to the front surface of the device. A source region 6 formed by N + ion implantation is formed in the P-well 62. On the front side of the silicon, there are gate oxide 4, polysilicon gate 5, interlayer dielectric film 7, contact hole 8 and source and gate metal 9, and also includes a P + ohmic contact region formed by P + ion implantation (obtained by implanting boron after the formation of the contact hole, not shown), and a drain 10 (back metal) on the bottom of the low resistivity silicon substrate 01 (called the back of the silicon wafer, or the back of the device). The characteristics of the components of these devices are consistent with the corresponding parts of the prior art, and the process thereof is not described herein.
In the above embodiment, the P-type thin layers 34 in the second segment of alternating P-N middle thin layers must be connected with the P-type thin layers 33 in the first segment of alternating P-N middle thin layers, and may be partially or completely overlapped. If both the P-type thin layer 34 and the P-type thin layer 33 are implemented by epitaxial filling of the trench, only the P-type thin layer 34 in the overlapped portion is remained, so that when the impurity concentration of the second P-type thin layer 34 is equal to that of the first P-type thin layer 33, the total impurity amount of the P-type thin layers in the whole alternately arranged P-N thin layers is not affected by the depth of the trench of the second P-type thin layer 34 as long as the second P-type thin layer 34 is ensured to be connected with the first P-type thin layer 33.
In the device of this example, the thickness of the P-N thin layer is 40 microns and the trench width is 5 microns, assuming that the etch depth uniformity is controlled to within 5% on the same wafer (uniformity is the maximum value of the depth difference in the wafer divided by the sum of the maximum and minimum depths in the wafer). Then, with the existing process with only one P-N layer, the target depth of the trench is 40 microns, and the depth difference in a silicon wafer will reach 4 microns, resulting in a reverse breakdown voltage difference of 40-80 volts. In this embodiment, the thickness of the first P-N layer is 15 microns, the difference of the depths in a silicon wafer is at most 1.5 microns, the thickness of the second P-N layer is 25 microns, as long as it is ensured that the layers in the second P-N layer are in direct contact with the P layer of the first P-N layer on the whole silicon wafer (the etching depth of the trench of the second P-N layer can be properly deepened), the depth change of the P layer of the second P-N layer has no influence on the device structure (the overlapping region of the P layer of the second P-N layer and the P layer of the first P-N layer is to etch the P layer of the overlapping region of the second P-N layer, and the refilling is good, and has no influence on the device), so the thickness change of the P-type layer of the whole device is equal to the change of the P layer of the first P-N layer, the maximum difference in silicon is 1.5 microns, with a difference in reverse breakdown voltage of 15-30 volts, a significant improvement over the prior art.
In the embodiment, the aspect ratio of the P thin layer of the first section of P-N thin layer is 3, and the aspect ratio of the P thin layer of the second P-N thin layer is 5, which are both obviously reduced compared with the aspect ratio of 8 in the prior art, so that the process difficulty of trench etching and trench epitaxial filling is also reduced.
The first embodiment is further improved in that the alternately arranged P-N thin layers of the device can be composed of three or more than three alternately arranged P-N thin layers, and the thickness of each P-N thin layer is further reduced, so that the difficulty of the manufacturing process of the device is reduced, the uniformity of the thickness of the P-type thin layers is improved, and the uniformity of the reverse breakdown voltage of the device is improved.
A further improvement of the first embodiment is that, between adjacent P-N layers of different segments, the width of the P layer in the P-N layers of one segment may not be equal to the width of the P layer in the P-N layers of another segment adjacent thereto, which facilitates the design of the device.
A further improvement of the first embodiment is that the arrangement of the P-N layers in one step of one segment of the alternating P-N layers may be different from the arrangement of the P-N layers in one step of the adjacent segment of the alternating P-N layers, which facilitates the design of the device.
A further improvement of the first embodiment is that the concentration of P-type impurities in the P layers of one of the alternating P-N layers may not be equal to the concentration of P-type impurities in the P layers of another adjacent alternating P-N layer, for example, the concentration of P-type impurities in the first segment may be lower or higher than the concentration of P-type impurities in the second segment, improving device performance and facilitating device design.
A further improvement of the first embodiment is that the concentration of the N type impurity in the N thin layer of one of the alternately arranged P-N thin layers may not be equal to the concentration of the N type impurity in the N thin layer of another adjacent one of the alternately arranged P-N thin layers, for example, the concentration of the N type impurity in the first section may be lower or higher than the concentration of the N type impurity in the second section, a lower concentration of the N type impurity in the first section may increase the reverse breakdown voltage of the device, and a higher concentration of the N type impurity in the first section may increase the current surge resistance and voltage surge resistance of the device, thereby improving the performance of the device and facilitating the design of the device.
A further improvement over the first embodiment is that the thickness of the alternating P-N layers closest to the back surface of the device, i.e., the first alternating P-N layers, is less than or equal to 20 microns, which reduces the uniformity of the P layer thickness throughout the alternating P-N layers, thereby improving the uniformity of device performance.
A further improvement to embodiment one is that the concentration of N type impurities in one of the alternating P-N layers closest to the back surface of the device, i.e., the first alternating P-N layer, is less than the concentration of N type impurities in an adjacent N layer of a second alternating P-N layer located closer to the front surface of the device, e.g., the concentration of N type impurities in an N layer of the first alternating P-N layer is 3.97E15 atoms/cubic centimeter (1.2 ohm-centimeter), the concentration of N type impurities in an N layer of the second alternating P-N layer is 4.83E15 atoms/cubic centimeter (1 ohm-centimeter), the concentration of P type impurities in the corresponding P layer is equal to the concentration of N type impurities in an N layer of the same segment, therefore, the influence of the thickness of the P thin layers (the depth of the etched groove) in the first section of the P-N thin layers which are alternately arranged is further reduced, and the uniformity of the reverse breakdown voltage of the device is further improved.
A further improvement to embodiment one is that the P layers of the first alternating P-N layers have an impurity concentration of 4.35E15 atoms/cc and the N layers of the first alternating P-N layers have an impurity concentration of 4.83E15 atoms/cc, such that the total amount of P type impurities in the P layers of the first alternating P-N layers (the section closest to the back surface of the device) is less than the total amount of N type impurities in the N layers; the impurity concentration of the P thin layers in the second section of the P-N thin layers which are alternately arranged is 5.31E15 atomic numbers/cubic centimeter, and the impurity concentration of the N thin layers in the second section of the P-N thin layers which are alternately arranged is 4.83E15 atomic numbers/cubic centimeter, so that the P type impurities in the P thin layers of the second section of the P-N thin layers which are alternately arranged (the section which is closer to the front surface of the device) are larger than the total amount of the N type impurities in the N thin layers. Therefore, the voltage resistance and the current overshoot resistance of the device are further improved, and the reliability of the device is improved.
Example two
Fig. 4 is a schematic diagram of a charge flow region device according to a second embodiment of the present invention, in which the P-N layers of the alternating P-N layers of fig. 4 have a width greater than that of the P-N layers of the alternating P-N layers of the second segment, unlike the first embodiment: the width of the P thin layer 33 in the first section of alternately arranged P-N thin layers is 6 microns, the concentration of P type impurities is 3.22E15 atomicity/cubic centimeter, the width of the N thin layer 43 is 4 microns, and the concentration of N type impurities is 4.83E15 atomicity/cubic centimeter; the width of the P thin layer 34 in the P-N thin layers arranged alternately in the second section is 5 micrometers, and the concentration of P-type impurities is 4.83E15 atomic numbers/cubic centimeter; the width of the N thin layer 44 was 5 microns and the N-type impurity concentration was 4.83E15 atomic numbers per cubic centimeter. Because the width of the P thin layer in the first section of alternately arranged P-N thin layers is larger than that of the P thin layer in the second section of alternately arranged P-N thin layers, even if the width of the groove is changed to a certain extent in the manufacturing of the P thin layer in the second section of alternately arranged P-N thin layers, the position of the P thin layer in the first section of alternately arranged P-N thin layers has a certain deviation, and the P thin layer in the second section of alternately arranged P-N thin layers can fall on the P thin layer in the first section of alternately arranged P-N thin layers as long as the sum of the change amounts is not more than 0.5 micrometer, so that the stability of the process is further improved, and the uniformity of the performance of the device is improved.
The improvement of the first embodiment can also be implemented in the second embodiment, as long as the total amount of the N-type impurities and the total amount of the P-type impurities of the P-N thin layers alternately arranged in the first and second segments can meet the requirement of charge balance, and the design of the concentration of each impurity can be optimized according to the requirements of device performance and reliability.
EXAMPLE III
Fig. 5 is a schematic diagram of a third embodiment of a charge flow region device, in which the alternating P-N layers in fig. 5 are different from the first embodiment in that the width of the P layers in the first segment of the alternating P-N layers is smaller than the width of the P layers in the second segment of the alternating P-N layers: the width of the P layer 33 in the first alternating P-N layer (the alternating P-N layer closest to the back surface of the device) was 4.5 microns, the P layer 33 impurity concentration was 4.83E15 atoms/cc, the width of the N layer 43 was 5.5 microns, and the N layer 43 impurity concentration was 5.07E15 atoms/cc; the width of the P layers 34 in the second alternating P-N layers (the alternating P-N layers adjacent to the first segment and near the front surface of the device) is 5 microns, the impurity concentration of the P layers 34 is 4.83E15 atoms/cc, the width of the N layers 44 is 5 microns, the impurity concentration of the N layers 44 is 4.83E15 atoms/cc, that is, the width of the P layer of the first alternately arranged P-N layers is smaller than the width of the P layer of the second alternately arranged P-N layers adjacent thereto and located closer to the front surface of the device, and the concentration of the N type impurity in the N layer of the first alternately arranged P-N layers is greater than the concentration of the N type impurity in the N layer of the second alternately arranged P-N layers adjacent thereto and located closer to the front surface of the device. Therefore, the total amount of N-type impurities in the N thin layers of the P-N thin layers which are alternately arranged at the first section (the section closest to the surface of the back surface of the device) is larger than the total amount of P-type impurities in the P thin layers at the same section, an N-type impurity area which is close to the back surface of the device and is not exhausted is increased, or partial N impurities in the P-N thin layers which are close to the back surface of the device and the middle-sized impurities in the P-N thin layers which are alternately arranged at the second section are mutually exhausted, so that the voltage resistance and the current overshoot resistance of the device are further improved, and the reliability of.
The improvement of the first embodiment can also be implemented in the third embodiment, as long as the total amount of the N-type impurities and the total amount of the P-type impurities of the P-N thin layers alternately arranged in the first and second segments can meet the requirement of charge balance, and the design of the concentration of each impurity can be optimized according to the requirements of device performance and reliability.
Example four
Fig. 6 is a schematic diagram of a charge flow region device structure according to a fourth embodiment of the present invention, wherein the alternating P-N layers of fig. 6 differ from the first embodiment in that the P-N layers of one step of the alternating P-N layers 35 of the segment closest to the back surface of the device differ from the P-N layers of one step of the alternating P-N layers 36 of the adjacent segment located closer to the front surface of the device. As shown in fig. 6, in the first P-N thin layer 35, a step size includes P thin layers a-N thin layers b-P thin layers c-N thin layers d, where a is 1.5 micrometers, b is 2 micrometers, d is 5 micrometers, the P-type impurity concentration of the P thin layers is 1.01E16 atomicity/cubic centimeter, the N-type impurity concentration of the N thin layers is 4.83E15 atomicity/cubic centimeter, the total amount of the P-type impurities is less than the total amount of the N-type impurities, and in the second P-N thin layer 36 located above the P thin layers, a step size includes P thin layers E-N thin layers f, where E is 5 micrometers, and f is 5 micrometers. The P-type impurity concentration of the P thin layer is 5.31E 15-4.83E 15 atoms/cubic centimeter, the N-type impurity concentration of the N thin layer is 4.83E15 atoms/cubic centimeter, and the total amount of the P-type impurities is larger than or equal to that of the N-type impurities.
Through the improvement, a local high electric field is generated in the first section of alternately arranged P-N thin layers 35 close to the back surface of the silicon wafer, so that a reverse breakdown generating point of a device is easy to appear in the first section of alternately arranged P-N thin layers, electrons and holes are aligned when breakdown occurs, the electrons are quickly extracted to the back surface of the silicon wafer, and in the process of extracting the holes to the front surface, the electrons and the holes are neutralized by negatively charged space charges in the second section of alternately arranged P-N thin layers 36, so that the maximum electric field in the second section of alternately arranged P-N thin layers is reduced, and the voltage overshoot resistance and the current overshoot resistance of the device are improved.
A further improvement on any of the first to fourth embodiments is that, with reference to the structure of fig. 2, only the second P-N layers are alternately arranged in the termination region, and the first P-N layers are not alternately arranged, so that the reverse breakdown point of the device is more likely to occur in the first P-N layers alternately arranged in the current flowing region, thereby improving the voltage overshoot resistance and the current overshoot resistance of the device.
For all of the above embodiments one through four, and modifications thereof, the alternating P-N layers may be formed using process steps that may include:
step one, growing an N-type first epitaxial layer on a high-concentration N-type substrate 01;
step two, forming a first groove with a certain height-width ratio on the first epitaxial layer through photoetching; a dielectric film can be grown on the surface of the first epitaxial layer before photoetching, so that after etching, some dielectric film can be reserved to be used as a barrier layer for chemical mechanical polishing later. The surface of the epitaxial layer can be directly used as a protective layer for etching the groove without growing a dielectric film.
Filling P-type first silicon into the groove, wherein the P-type first silicon can be a P-type epitaxial layer; the P-type first silicon may be formed using a low pressure chemical vapor deposition or a low pressure epitaxial process.
And step four, obtaining the first section of alternately arranged P-N thin layers by utilizing chemical mechanical grinding. If the dielectric film is used as a barrier layer for chemical mechanical polishing, the dielectric film needs to be removed after polishing.
Step five, the method comprises the following sub-steps:
1. growing N-type second epitaxial layers on the first sections of the P-N thin layers which are alternately arranged;
2. forming a second groove by adopting a photoetching process, wherein the bottom of the second groove is in contact with or penetrates through the top of the P thin layers of the P-N thin layers which are alternately arranged at the first section; it is necessary to ensure that the bottom of the second trench contacts or penetrates the top of the P thin layer of the first segment of the alternating P-N thin layers at all positions in the silicon wafer, so that the etching amount of the second trench etching process can be increased properly.
3. Filling second silicon of the P-type semiconductor into the second trench; the second silicon of the P-type semiconductor may be a P-type epitaxial layer. The P-type second silicon may be formed using a low pressure chemical vapor deposition or a low pressure epitaxial process.
4. And obtaining a second section of alternately arranged P-N thin layers which are superposed on the first section of alternately arranged P-N thin layers by adopting a chemical mechanical grinding process.
Thus, two alternating P-N layers are obtained.
Compared with the prior art, the structure of the two alternately arranged P-N thin layers is adopted, so that the difficulty of the process is reduced, and the uniformity of the depth of the groove is improved, so that the uniformity of the thickness of the P thin layers in the whole alternately arranged P-N thin layers is improved, and the uniformity of the reverse breakdown voltage of the device is improved.
The further improvement of the process steps is that after the process steps are completed, the steps 1, 2, 3 and 4 of the step five are repeatedly carried out until the thickness of the P-N thin layer meets the requirement of reverse breakdown voltage of the device, so that the thickness of the P-N thin layer which is alternately arranged at each section is further reduced, and the difficulty of the process is reduced.
EXAMPLE five
Fig. 7 is a schematic diagram of a charge flow region device according to a fifth embodiment of the present invention, wherein the alternating P-N layers of fig. 7 are formed by an epitaxial process, photolithography and ion implantation, unlike the first embodiment, in a section of the alternating P-N layers closest to the back surface of the device.
The manufacturing process of the fifth embodiment comprises the following process steps:
step one, performing zero-time N-type epitaxial layer growth with lower resistivity (such as 1-5 ohm. cm) on a high-concentration N-type semiconductor substrate 01, and then growing a first epitaxial layer with high resistivity, wherein the first epitaxial layer 38 can be of an N type, and the resistivity can be more than 50 times of the resistivity of the zero-time N-type epitaxial layer;
the thickness of the zero-order N-type epitaxial layer of lower resistivity (e.g., 1-5 ohm. cm) is 2-10 microns.
And step two, forming an N-type thin layer region on the first epitaxial layer through photoetching and N-type semiconductor ion implantation, such as phosphorus ion implantation.
And thirdly, forming a P-type thin layer region on the first epitaxial layer through photoetching and P-type semiconductor ion implantation, such as boron implantation.
The ions implanted in the above second and third steps are activated and diffused in a high temperature process thereafter to form a first stage of alternately arranged P-N thin layers consisting of P-type thin layers 37 and N-type thin layers 38. The first alternating P-N layers have a resistivity of about 1-5 ohm-cm for N layers and a thickness of about 6-8 microns for P-N layers.
Step four, the method comprises the following sub-steps:
1. and growing a second epitaxial layer of the N-type semiconductor on the P-N thin layers which are formed in the first to third steps and are alternately arranged on the first section, wherein the thickness of the second epitaxial layer of the N-type semiconductor is 32-34 micrometers, and the resistivity is 1-5 ohm.
2. Forming a first groove by adopting a photoetching process, wherein the bottom of the first groove is contacted with or penetrates through the top of the P-type thin layers on the P-N thin layers which are alternately arranged on the first section and are formed in the first to third steps; the depth of the first trench is greater than the thickness of the second epitaxial layer of the N-type semiconductor, for example 35-36 microns, so that the bottom of the first trench is contacted or penetrated through all positions in the silicon wafer to contact or penetrate through the top of the P-type thin layers on the P-N thin layers alternately arranged on the first section formed in the first-third steps.
3. The first trench is filled with P-type semiconductor silicon 39, such as P-type epitaxial silicon. The silicon of the P-type semiconductor may be formed using low pressure chemical vapor deposition or low pressure epitaxial processes.
4. And obtaining a second section of alternately arranged P-N thin layers which are superposed on the first section of alternately arranged P-N thin layers by adopting chemical mechanical grinding.
The second alternating series of P-N layers consists of P-type layers 39 and N-type layers 40.
By adopting the process method, the alternately arranged P-N thin layers which are finished by one process in the prior art are divided into two sections, wherein the first section is carried out by epitaxial deposition, photoetching and ion implantation, and the second section is grown by groove etching and groove epitaxy, so that the process difficulty is reduced, and the uniformity of the device is improved.
The further improvement of the process method is that after the process steps are completed, the steps 1, 2, 3 and 4 of the step four are repeatedly carried out until the thickness of the P-N thin layer meets the requirement of reverse breakdown voltage of the device, so that the thickness of the P-N thin layer which is alternately arranged at each section is further reduced, and the process difficulty is reduced.
In the device manufacturing process according to any one of the first to fifth embodiments, the method further includes the following steps,
step 1, forming a well of a second type of semiconductor on the surface of the P-N thin layer through photoetching and injection;
and 2, forming gate oxide on the surface of the P-N thin layer through thermal oxidation, then depositing polycrystalline silicon or amorphous silicon of the first type of semiconductor, and forming a gate region through photoetching.
Step 3, performing ion implantation of a source region of the first type of semiconductor through photoetching and ion implantation to form a source region;
step 4, growing an interlayer film on the surface of the front side of the silicon wafer;
step 5, carrying out contact hole photoetching;
step 6, utilizing impurity ion implantation of the high-energy second type semiconductor to realize ohmic connection between metal in the contact hole and the second type semiconductor well;
step 7, forming a source electrode and a polysilicon gate wire on the surface of the front surface of the silicon wafer through metal growth, photoetching and etching;
and 8, thinning the back of the silicon wafer and metalizing the back to form the drain electrode.
In all the above embodiments, if the N type is changed to the P type, and the P type is changed to the N type (i.e., the first type of semiconductor is a P type semiconductor, and the second type of semiconductor is an N type semiconductor), the corresponding PMOSFET device manufacturing method is obtained.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (10)

1. A super junction semiconductor device, characterized by: the alternately arranged P-N thin layers of the device are formed by at least two alternately arranged P-N thin layers in the direction vertical to the surface of the device, and in the structure of the alternately arranged P-N thin layers formed by longitudinally overlapping the P-N thin layers of each section, the P-type thin layers of the P-N thin layers of the adjacent sections are aligned and contacted with each other and the N-type thin layers are aligned and contacted with each other;
the second conductive type thin layers of the P-N thin layers which are arranged closest to the back surface of the device in an alternating mode are composed of second conductive type silicon filled in the grooves or composed of second conductive type ion implantation regions, and the first conductive type thin layers are composed of first conductive type epitaxial layers among the second conductive type thin layers; the second conduction type thin layers of the P-N thin layers which are arranged alternately and are positioned above the P-N thin layers which are arranged alternately and closest to the back surface of the device consist of second conduction type silicon filled in the grooves, and the first conduction type thin layers consist of first conduction type epitaxial layers among the second conduction type thin layers; the grooves of the second conductive type thin layers of the P-N thin layers which are alternately arranged on the P-N thin layers which are alternately arranged and are closest to the back surface of the device have a structural relationship from bottom to top formed after the second conductive type thin layers corresponding to the bottoms are formed;
the alternating P-N thin layers closest to the back surface of the device are arranged, so that the uniformity of the longitudinal depth of the alternating P-N thin layers of the whole device is determined by the uniformity of the depth of the alternating P-N thin layers closest to the back surface of the device, the variation range of the longitudinal depth of the alternating P-N thin layers of the whole device is reduced, the uniformity of the longitudinal depth is improved, and the difference of reverse breakdown voltages of the device is improved;
the depth-to-width ratio of the grooves of the P-N thin layers which are alternately arranged on the section which is closest to the back surface of the device can be reduced by arranging the P-N thin layers which are alternately arranged on the section which is closest to the back surface of the device, so that the difficulty of the manufacturing process of the device is reduced, the uniformity of the thickness of the P-type thin layers is improved, and the uniformity of the reverse breakdown voltage of the device is improved;
a first conductive epitaxial layer is isolated between the bottom of a section of alternately arranged P-N thin layers closest to the back surface of the device and the high-concentration first type semiconductor substrate;
the thickness of the thin layers of the P-N thin layers which are arranged closest to the back surface of the device in an alternating mode is less than or equal to 20 micrometers, so that the in-plane difference of the reverse breakdown voltage of the device is controlled by the etching depth uniformity or the ion implantation depth uniformity with the depth of less than 20 micrometers;
the width of the P-type thin layers, the width of the N-type thin layers, the doping concentration of the P-type thin layers, the doping concentration of the N-type thin layers and the structure corresponding to the arrangement mode of the P-N thin layers in one step length of the adjacent P-N thin layers which are alternately arranged at different sections can be independently adjusted according to the required performance of the device.
2. The super-junction semiconductor device of claim 1, wherein: the first structure formed by the width of the P-type thin layer, the width of the N-type thin layer, the doping concentration of the P-type thin layer and the doping concentration of the N-type thin layer of the adjacent P-N thin layers which are alternately arranged at different sections is as follows: between the adjacent P-N thin layers which are alternately arranged in different sections, the width of the P-type thin layer in the P-N thin layers which are alternately arranged in one section is equal to the width of the P-type thin layer in the P-N thin layers which are alternately arranged in the other section adjacent to the P-type thin layer; the width of the N-type thin layer in the P-N thin layers which are alternately arranged in one section is equal to that of the N-type thin layer in the P-N thin layers which are alternately arranged in the other section adjacent to the one section; the concentration of the P-type impurities in the P-type thin layers in one section of the alternately arranged P-N thin layers is equal to that of the P-type impurities in the P-type thin layers in the other section adjacent to the one section of the alternately arranged P-N thin layers; the concentration of N-type impurities in the N-type thin layers in one section of the P-N thin layers which are alternately arranged is equal to that of the N-type impurities in the N-type thin layers in the other section of the P-N thin layers which are adjacent to the N-type impurities in the P-N thin layers which are alternately arranged; the first structure makes the total amount of P-type impurities and the total amount of N-type impurities in each of the alternately arranged P-N thin layers realize charge balance, thereby improving reverse breakdown voltage.
3. The super-junction semiconductor device of claim 1, wherein: the second structure formed by the width of the P-type thin layer, the width of the N-type thin layer, the doping concentration of the P-type thin layer and the doping concentration of the N-type thin layer of the adjacent P-N thin layers which are alternately arranged at different sections is as follows: between the adjacent P-N thin layers which are alternately arranged in different sections, the width of the P-type thin layer in the P-N thin layers which are alternately arranged in one section is equal to the width of the P-type thin layer in the P-N thin layers which are alternately arranged in the other section adjacent to the P-type thin layer; the width of the N-type thin layer in the P-N thin layers which are alternately arranged in one section is equal to that of the N-type thin layer in the P-N thin layers which are alternately arranged in the other section adjacent to the one section;
the concentration of N-type impurities in the N-type thin layers in the alternately arranged P-N thin layers of the first section closest to the back surface of the device is less than that in the N-type thin layers in the alternately arranged P-N thin layers of the second section adjacent to the first section and positioned closer to the front surface of the device; the concentration of the P-type impurities of the P-type thin layer in each section of the P-N thin layer is equal to that of the N-type impurities of the N-type thin layer in the same section; the second structure reduces the influence of the thickness of the P-type thin layers in the first section of the P-N thin layers which are alternately arranged, and further improves the uniformity of reverse breakdown voltage of the device.
4. The super-junction semiconductor device of claim 1, wherein: the third structure formed by the width of the P-type thin layers, the width of the N-type thin layers, the doping concentration of the P-type thin layers and the doping concentration of the N-type thin layers of the adjacent P-N thin layers which are alternately arranged at different sections is as follows: between the adjacent P-N thin layers which are alternately arranged in different sections, the width of the P-type thin layer in the P-N thin layers which are alternately arranged in one section is equal to the width of the P-type thin layer in the P-N thin layers which are alternately arranged in the other section adjacent to the P-type thin layer; the width of the N-type thin layer in the P-N thin layers which are alternately arranged in one section is equal to that of the N-type thin layer in the P-N thin layers which are alternately arranged in the other section adjacent to the one section; the concentration of N-type impurities in the N-type thin layers in one section of the P-N thin layers which are alternately arranged is equal to that of the N-type impurities in the N-type thin layers in the other section of the P-N thin layers which are adjacent to the N-type impurities;
the total amount of P-type impurities of the P-type thin layers in the first section of the alternately arranged P-N thin layers closest to the back surface of the device is less than that of N-type impurities of the N-type thin layers in the first section of the alternately arranged P-N thin layers; the total amount of P-type impurities of the P-type thin layers in the P-N thin layers which are arranged in the second section and are adjacent to the first section and positioned closer to the front surface of the device is larger than the total amount of N-type impurities of the N-type thin layers in the P-N thin layers which are arranged in the second section and are arranged in the alternating mode; the third structure further improves the voltage resistance and current overshoot capability of the device and improves the reliability of the device.
5. The super-junction semiconductor device of claim 1, wherein: the fourth structure formed by the width of the P-type thin layer, the width of the N-type thin layer, the doping concentration of the P-type thin layer and the doping concentration of the N-type thin layer of the adjacent P-N thin layers which are alternately arranged at different sections is as follows: between the adjacent P-N thin layers which are alternately arranged in different sections, the width of the P-type thin layer in the first section of the P-N thin layers which are alternately arranged and closest to the back surface of the device is larger than the width of the P-type thin layer in the second section of the P-N thin layers which are alternately arranged and adjacent to the first section and are positioned closer to the front surface of the device; the total amount of P-type impurities and the total amount of N-type impurities in the P-N thin layers which are alternately arranged in each section realize charge balance; the fourth structure further improves the stability of the process and the uniformity of the performance of the device.
6. The super-junction semiconductor device of claim 1, wherein: the fifth structure formed by the width of the P-type thin layer, the width of the N-type thin layer, the doping concentration of the P-type thin layer and the doping concentration of the N-type thin layer of the adjacent P-N thin layers which are alternately arranged at different sections is as follows: between the adjacent P-N thin layers which are alternately arranged at different sections, the width of the P-type thin layer in the first section of the P-N thin layers which are alternately arranged and closest to the back surface of the device is smaller than the width of the P-type thin layer in the second section of the P-N thin layers which are alternately arranged and adjacent to the first section and are positioned closer to the front surface of the device; the concentration of N-type impurities in the N-type thin layers in the P-N thin layers which are alternately arranged at the first section is greater than that of the N-type impurities in the N-type thin layers which are alternately arranged at the other section adjacent to the first section; the total amount of P-type impurities of the P-type thin layers in the first section of the alternately arranged P-N thin layers is less than that of N-type impurities of the N-type thin layers in the first section of the alternately arranged P-N thin layers; the fifth structure further improves the voltage resistance and current overshoot capability of the device and improves the reliability of the device.
7. The super-junction semiconductor device of claim 1, wherein: the sixth structure formed by the arrangement mode of the P-N thin layers in one step length of the adjacent P-N thin layers which are alternately arranged at different sections is as follows: the arrangement mode of the P-N thin layers in one step size in the first section of the P-N thin layers which are arranged alternately and closest to the back surface of the device is different from the arrangement mode of the P-N thin layers in one step size in the second section of the P-N thin layers which are adjacent to the first section and are positioned closer to the front surface of the device, and the arrangement mode of the P-N thin layers in one step size in the first section of the P-N thin layers which are arranged alternately enables the reverse breakdown occurrence point of the device to appear in the first section of the P-N thin layers which are arranged alternately; the sixth structure improves the voltage and current overshoot resistance of the device.
8. A manufacturing method of a super junction semiconductor device is characterized by comprising the following process steps:
step one, growing a first epitaxial layer of a first type of semiconductor on a high-concentration first type of semiconductor substrate;
step two, forming a first groove on the first epitaxial layer through photoetching;
filling first silicon of a second type of semiconductor into the first groove;
step four, obtaining a first section of alternately arranged P-N thin layers by utilizing chemical mechanical grinding; the first section of alternately arranged P-N thin layers are the sections of alternately arranged P-N thin layers closest to the back surface of the device, and the uniformity of the longitudinal depth of the alternately arranged P-N thin layers of the whole device is determined by the uniformity of the depth of the alternately arranged P-N thin layers closest to the back surface of the device, so that the variation range of the longitudinal depth of the alternately arranged P-N thin layers of the whole device is reduced, the uniformity of the longitudinal depth is improved, and the difference of reverse breakdown voltages of the device is improved;
a first conductive epitaxial layer is isolated between the bottom of a section of alternately arranged P-N thin layers closest to the back surface of the device and the high-concentration first type semiconductor substrate;
the thickness of the thin layers of the P-N thin layers which are arranged closest to the back surface of the device in an alternating mode is less than or equal to 20 micrometers, and the in-plane difference of the reverse breakdown voltage of the device is controlled by the etching uniformity with the etching depth of less than 20 micrometers; step five, the method comprises the following sub-steps:
1. growing a second epitaxial layer of the first type of semiconductor on the first section of the alternately arranged P-N thin layers;
2. forming a second groove by adopting a photoetching process, wherein the bottom of the second groove is contacted with or penetrates through the top of the first groove;
3. filling second silicon of a second type of semiconductor into the second trench;
4. utilizing chemical mechanical polishing to obtain a second section of alternately arranged P-N thin layers which are superposed on the first section of alternately arranged P-N thin layers;
then, repeatedly carrying out the sub-steps 1, 2, 3 and 4 of the step five to form the alternately arranged P-N thin layers of the device consisting of at least two alternately arranged P-N thin layers in the direction vertical to the surface of the device until the thickness of the alternately arranged P-N thin layers of the device meets the requirement of reverse breakdown voltage of the device;
in the structure of the alternately arranged P-N thin layers of the device formed by longitudinally overlapping the P-N thin layers of each section, the P-type thin layers of the P-N thin layers of the adjacent sections are aligned and contacted with each other and the N-type thin layers are aligned and contacted with each other;
the second conduction type thin layers of the P-N thin layers which are arranged alternately and are positioned above the P-N thin layers which are arranged alternately and closest to the back surface of the device consist of second conduction type silicon filled in the second grooves, and the first conduction type thin layers consist of first conduction type epitaxial layers among the second conduction type thin layers;
the depth-to-width ratio of the grooves of the P-N thin layers which are alternately arranged on the section which is closest to the back surface of the device can be reduced by arranging the P-N thin layers which are alternately arranged on the section which is closest to the back surface of the device, so that the difficulty of the manufacturing process of the device is reduced, the uniformity of the thickness of the P-type thin layers is improved, and the uniformity of the reverse breakdown voltage of the device is improved;
the width of the P-type thin layers, the width of the N-type thin layers, the doping concentration of the P-type thin layers, the doping concentration of the N-type thin layers and the structure corresponding to the arrangement mode of the P-N thin layers in one step length of the adjacent P-N thin layers which are alternately arranged at different sections can be independently adjusted according to the required performance of the device.
9. A manufacturing method of a super junction semiconductor device is characterized by comprising the following process steps:
step one, growing a first epitaxial layer with high resistivity on a first type of high-concentration semiconductor substrate;
step two, forming a first type semiconductor thin layer on the epitaxial layer through photoetching and first type semiconductor ion implantation;
step three, forming a second type semiconductor thin layer on the epitaxial layer through photoetching and second type semiconductor ion implantation; the first type semiconductor thin layers and the second type semiconductor thin layers are alternately arranged in a chip current flowing area to form a first section of alternately arranged P-N thin layers;
the first section of alternately arranged P-N thin layers are the sections of alternately arranged P-N thin layers closest to the back surface of the device, and the uniformity of the longitudinal depth of the alternately arranged P-N thin layers of the whole device is determined by the uniformity of the depth of the alternately arranged P-N thin layers closest to the back surface of the device, so that the variation range of the longitudinal depth of the alternately arranged P-N thin layers of the whole device is reduced, the uniformity of the longitudinal depth is improved, and the difference of reverse breakdown voltages of the device is improved; step four, the method comprises the following sub-steps:
1. carrying out second epitaxial layer growth of the first type of semiconductor on the first section of alternately arranged P-N thin layers formed in the first to third steps;
2. forming a first groove on the second epitaxial layer by adopting a photoetching process, wherein the bottom of the first groove is contacted with or penetrates through the tops of the P-N thin layers which are formed in the first step I to the third step and are alternately arranged on the first section of the P-N thin layers;
3. filling silicon of a second type of semiconductor into the first trench;
4. utilizing chemical mechanical polishing to obtain a second section of alternately arranged P-N thin layers which are superposed on the first section of alternately arranged P-N thin layers;
then, repeatedly carrying out the sub-steps 1, 2, 3 and 4 of the step five to form the alternately arranged P-N thin layers of the device consisting of at least two alternately arranged P-N thin layers in the direction vertical to the surface of the device until the thickness of the alternately arranged P-N thin layers of the device meets the requirement of reverse breakdown voltage of the device;
in the structure of the alternately arranged P-N thin layers of the device formed by longitudinally overlapping the P-N thin layers of each section, the P-type thin layers of the P-N thin layers of the adjacent sections are aligned and contacted with each other and the N-type thin layers are aligned and contacted with each other;
the second conduction type thin layers of the P-N thin layers which are arranged alternately and are positioned above the P-N thin layers which are arranged alternately and closest to the back surface of the device consist of second conduction type silicon filled in the first grooves, and the first conduction type thin layers consist of first conduction type epitaxial layers among the second conduction type thin layers;
the depth-to-width ratio of the grooves of the P-N thin layers which are alternately arranged on the section which is closest to the back surface of the device can be reduced by arranging the P-N thin layers which are alternately arranged on the section which is closest to the back surface of the device, so that the difficulty of the manufacturing process of the device is reduced, the uniformity of the thickness of the P-type thin layers is improved, and the uniformity of the reverse breakdown voltage of the device is improved.
10. The manufacturing method according to any one of claims 8 and 9, characterized by: the method also comprises the following steps of,
step 1, forming a well of a second type of semiconductor on the surface of the P-N thin layer through photoetching and injection;
step 2, forming gate oxide on the surface of the P-N thin layer through thermal oxidation, then depositing polycrystalline silicon or amorphous silicon of a first type of semiconductor, and forming a gate region through photoetching;
step 3, performing ion implantation of a source region of the first type of semiconductor through photoetching and ion implantation to form a source region;
step 4, growing an interlayer film on the surface of the front side of the silicon wafer;
step 5, carrying out contact hole photoetching;
step 6, injecting impurity ions of the high-energy second type semiconductor to realize ohmic contact between metal in the contact hole and the second type semiconductor well;
step 7, performing metal growth, photoetching and etching on the surface of the front side of the silicon wafer to form a source electrode and a polysilicon gate wire;
and 8, thinning the back of the silicon wafer and metalizing the back to form a drain electrode.
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