CN104124276A - Super-junction device and manufacturing method thereof - Google Patents

Super-junction device and manufacturing method thereof Download PDF

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CN104124276A
CN104124276A CN201410392143.1A CN201410392143A CN104124276A CN 104124276 A CN104124276 A CN 104124276A CN 201410392143 A CN201410392143 A CN 201410392143A CN 104124276 A CN104124276 A CN 104124276A
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thin layer
alternative arrangement
type
type semiconductor
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CN104124276B (en
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肖胜安
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Shenzhen Shangyangtong Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Abstract

The invention discloses a super-junction device and a manufacturing method thereof. Alternately arranged P-N (Positive-Negative) thin layers of the device are composed of at least two sections of alternately arranged P-N thin layers. The impurity concentration of the same type in the two adjacent sections of alternately arranged P-N thin layers can be equal or not; the arrangement mode of the P-N thin layers in one step length in one section of alternately arranged P-N thin layers of the two adjacent sections of the P-N thin layers and the arrangement mode of the P-N thin layers in one step length in the other adjacent section of alternately arranged P-N thin layers can be the same, and can also be different; the P-type impurity total quantity and the N-type impurity total quantity of the alternately arranged P-N thin layers in the same section can be the same or not. According to the super-junction device, the processing difficulty of the alternately arranged P-N thin layers can be reduced, the uniformity of the device performance is improved, and the current surge resistance and voltage surge resistance to the device and the design flexibility of the device can be improved. The invention further discloses a manufacturing technology of the device.

Description

A kind of super-junction device and preparation method thereof
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of structure of super junction high tension apparatus, the invention still further relates to the manufacture method of this super-junction device.
Background technology
Super junction metal-oxide layer semiconductcor field effect transistor, be called for short super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) adopt new structure of voltage-sustaining layer, utilize P type semiconductor thin layer and the N type semiconductor thin layer of a series of alternative arrangement under low voltage, just described P type semiconductor thin layer and N type semiconductor thin layer to be exhausted under cut-off state, realizing electric charge compensates mutually, thereby make P type semiconductor thin layer and N type semiconductor thin layer can realize high reverse breakdown voltage under high-dopant concentration, thereby obtain low on-resistance and high-breakdown-voltage simultaneously, power MOSFET theoretical limit breaks traditions.In US Patent No. 5216275, the P type semiconductor thin layer of above alternative arrangement is connected with N+ substrate with N type semiconductor thin layer; In US Patent No. 6630698B1, middle P type semiconductor thin layer and N type semiconductor thin layer and N+ substrate can have the interval that is greater than 0.
In prior art, the formation one of P type semiconductor thin layer and N type semiconductor thin layer is then to carry out photoetching and injection by epitaxial growth, repeatedly this process obtains P type semiconductor thin layer and the N type semiconductor thin layer of thickness needing repeatedly, in the MOSFET of this technique more than 600V, generally need to repeat more than 5 times, production cost is high, the production cycle is long.Another kind is after the extension that needs thickness by a kind of type of a secondary growth, carries out the etching of groove, inserts afterwards the silicon of opposite types in groove; After adopting groove structure, because P/N thin layer is that in the P type semiconductor thin layer of alternative arrangement and N type semiconductor thin layer, P type semiconductor thin layer and the doping content of N type semiconductor thin layer on longitudinal direction are easy to control, thereby and do not have repeatedly in thin layer that epitaxy technique causes P type semiconductor thin layer and N type semiconductor thin layer or the doping content of one of them change in the vertical to bring additional longitudinal electric field, ensured leakage current characteristic that device can obtain and high puncture voltage.This method has simplification of flowsheet, improve the effect of stability, but technology difficulty is large.
As shown in Figure 1, be the schematic top plan view of existing super-junction device.Device has comprised 1st district, 2nd district and 3rd district, the current flowing district that wherein said 1st district is described super-junction device, the current flowing district groove that this current flowing district comprises multiple parallel arranged.Described 2nd district and described 3rd district form the terminal protection structure of described super-junction device, and electric current is not provided in the time of described super-junction device conducting, are used for bearing the voltage from described 1st district to described super-junction device outermost end at reverse blocking state.Described 2nd district and 3rd district are all looped around the periphery in described current flowing district, and wherein said 2nd district and described 1st district are adjacent, and described 2nd district comprise at least one P type ring 24 and at least one ditch grooved ring 23, described P type ring 24 at least cover one described in ditch grooved ring 23; Described 3rd district comprise at least one ditch grooved ring 23 and a channel cutoff ring 21.Described ditch grooved ring 23 is tetragonal structure, is respectively formed with an additional trenches 22 at described ditch grooved ring 23 four jiaos, and this additional trenches 22 is used as charge balance compensation.
Be a kind of schematic cross-section of existing super-junction device as shown in Figure 2, this sectional view is along the sectional view that does AA ' direction as shown in Figure 1.On a N+ silicon chip, be formed with a N-type silicon epitaxy layer 2, be formed with multiple grooves 41 in described N-type silicon epitaxy layer 2, described groove 41 comprises current flowing district groove 25 and ditch grooved ring 23 and the annex groove 22 by as shown in Figure 1; In described groove 41, be filled with P type silicon 51, described P type silicon 51 and described N-type epitaxial loayer form P type silicon thin layer and the N-type epitaxial loayer laminate structure of alternative arrangement, a P type silicon 51 and an adjacent N-type epitaxial loayer (being placed in two N epitaxial loayers between adjacent groove) form a repetitive of the P-N thin layer of alternative arrangement, referred to here as a step-length.Described groove 41 in described 1st district is to be formed with P type trap 62 in the described P type silicon 51 on top of described current flowing district groove 25 and described N-type epitaxial loayer, in the described P type silicon 51 on the top that is simultaneously first ditch grooved ring 23 at first groove 41 in described 2nd district adjacent with described 1st district and described N-type epitaxial loayer, is formed with described P type ring 24; The quantity of described P type ring 24 is at least one, and described P type ring is general to link together with described P type trap.In described P type trap, be formed with the source region 6 that a N+ Implantation forms, in described 3rd district, outermost described N-type epitaxial loayer top is formed with described channel cutoff ring 21 simultaneously.Described 1st district also comprises P+ ohmic contact regions 63, grid oxygen 4, polysilicon gate 5, the inter-level dielectric film 7 that a P+ Implantation forms, contact hole 8, and source electrode and grid (graphical latter two electrode of metal 9), be formed with a drain electrode 10 in described N+ silicon chip bottom.In the time of described super-junction device conducting, electric current can arrive drain electrode through raceway groove and N-type epitaxial loayer thin layer by source electrode, and the P type silicon thin layer in described current flowing district groove 25 is under reverse blocking state, to form depletion region together with described N-type epitaxial loayer thin layer to bear together voltage.
Described epitaxial loayer 2 tops in described 2nd district are formed with inner side field plate 43, this inner side field plate 43 formed by surface metal and be a Metal field plate, isolated by described terminal dielectric layer and described epitaxial loayer 2 under the field plate of described inner side, the medial extremity of described inner side field plate 43 is formed on outermost polysilicon gate 5 and forms contact, described inner side field plate 43 and described grid are connected to each other, and described terminal dielectric layer is made up of dielectric layer 1 and dielectric layer 2 69.The described outside field plate that is formed with multiple mutual isolation at described epitaxial loayer 2 tops in described 3rd district, described outside field plate is Metal field plate, isolated by described dielectric layer 1 between described outermost field plate and described epitaxial loayer 2; In described 3rd district, can there is P type ring also can not have; Having described channel cutoff ring 21 in the outermost end in described 3rd district, is to be made up of N+ doping ring.Described 2nd district and 3rd district all belong to described terminal protection structure district, and in the time of described super-junction device conducting, it does not provide electric current, are used for bearing the voltage from described 1st district to described super-junction device outermost end at reverse blocking state.
With a reverse breakdown voltage 600-1000 volt super junction NMOSFET, the thickness of the P-N thin layer needing is 35-70 micron, and taking groove 41 width as 5 microns (generally between 2-7 microns), as example, the depth-to-width ratio of groove 41 is 7～12.Dark like this, and the high groove of depth-to-width ratio is wanted the disposable flawless extension filling that completes, technology difficulty is very large, simultaneously, the dark groove of disposable etching depth 35-70 micron, not only difficulty is large, and the uniformity of groove is difficult to meet the conforming requirement of device performance: the homogeneity of supposing etching depth on same silicon chip be controlled within 5% (homogeneity be the maximum of depth difference in silicon chip divided by silicon chip in depth capacity and minimum-depth sum), the excursion of the degree of depth will reach 3.5-7 micron, the difference of the reverse breakdown voltage bringing lies prostrate at 30-100, even be greater than 100 volts, therefore to realize difficulty large for the technique that realizes of existing device architecture, and the heterogencity of device is larger.
In the prior art of above-mentioned trench fill, because P-N thin layer is an etching groove and has filled, in termination environment, the general employing of the groove in (2nd district and the 3rd district) design the same with the groove in flow of charge district, has certain restriction to the flexibility of device design.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of structure of new high-voltage super junction-semiconductor device, the present invention also provides the manufacture method of the process of this super-junction device structure for this reason, can effectively reduce the difficulty that P-N thin layer forms technique, improve the homogeneity of P-N thin layer, improve device performance and increase the flexibility that device designs.
For solving the problems of the technologies described above, the invention provides a kind of super-junction semiconductor device structure, the P-N thin layer of its alternative arrangement is made up of the P-N thin layer of at least two sections of alternative arrangements in the direction perpendicular to device surface; Between the P-N thin layer of the adjacent alternative arrangement of different sections, the width of the P thin layer in the P-N thin layer of the alternative arrangement of a section, can with equate with the width of the P thin layer in the P-N thin layer of the alternative arrangement of another section near it, also can be unequal; The width of the N thin layer in the P-N thin layer of the alternative arrangement of a section, can with equate with the width of the N thin layer in the P-N thin layer of the alternative arrangement of another section near it, also can be unequal; In the P-N thin layer of the alternative arrangement of a section, in a step-length, the arrangement mode of P-N thin layer can be with identical with the arrangement mode of P-N thin layer in a step-length in the P-N thin layer of the alternative arrangement of another section near it, also can be not identical; The concentration of p type impurity in P thin layer in the P-N thin layer of the alternative arrangement of a section, can with equate with the concentration of p type impurity in P thin layer in the P-N thin layer of the alternative arrangement of another section near it, also can be unequal; The concentration of N-type impurity in N thin layer in the P-N thin layer of the alternative arrangement of a section, can with equate with the concentration of N-type impurity in N thin layer in the P-N thin layer of the alternative arrangement of another section near it, also can be unequal;
Further improve and be, between the P-N thin layer of the adjacent alternative arrangement of different sections, the width of the P thin layer in the P-N thin layer of the alternative arrangement of a section, be greater than with it near, position is than the width of the P thin layer in the P-N thin layer of the alternative arrangement of another section of its more close device front face surface.
Further improving is that the thickness of thin layer of the P-N thin layer of one section of alternative arrangement of the most close device backside surface is less than or equal to 20 microns.
Further improve and be, in the N thin layer of the P-N thin layer of one section of alternative arrangement of the most close device backside surface the concentration of N-type impurity be less than with it near, position is than the concentration of N-type impurity in the N thin layer in the P-N thin layer of the alternative arrangement of another section of its more close device front face surface.
Further improving is that in the P thin layer of the P-N thin layer of one section of alternative arrangement of the most close device backside surface, p type impurity is less than N-type total impurities in N thin layer; With near it, position is greater than N-type total impurities in N thin layer than p type impurity in P thin layer in the P-N thin layer of the alternative arrangement of another section of its more close device front face surface.
Further improve and be, the width of the P thin layer in the P-N thin layer of one section of alternative arrangement of the most close device backside surface, be less than with it near, position is than the width of the P thin layer in the P-N thin layer of the alternative arrangement of another section of its more close device front face surface.
Further improve and be, in the N thin layer of the P-N thin layer of one section of alternative arrangement of the most close device backside surface the concentration of N-type impurity be greater than with it near, position is than the concentration of N-type impurity in the N thin layer in the P-N thin layer of the alternative arrangement of another section of its more close device front face surface.
Further improve and be, P-N thin layer arrangement mode in a step-length in the P-N thin layer of one section of alternative arrangement of the most close device backside surface, be different from it near, position is than P-N thin layer arrangement mode in step-length of the P-N thin layer of the alternative arrangement of another section of its more close device front face surface.
The first provided by the invention realizes the manufacture method of above-mentioned super-junction device structure, comprises following processing step:
Step 1, on the first type semiconductor substrate of high concentration, carry out the first type semiconductor first epitaxial loayer grow up;
Step 2, by chemical wet etching, on described the first epitaxial loayer, form the first groove of certain depth-width ratio;
Step 3, in described the first groove, insert the first silicon of the second type semiconductor;
Step 4, utilize cmp to obtain the P-N thin layer of first paragraph alternative arrangement.
Step 5, comprise as follows step by step:
1, the second epitaxial loayer that carries out the first type semiconductor on the P-N of described first paragraph alternative arrangement thin layer is grown up;
2, adopt chemical wet etching technique to form the second groove, the bottom of second groove of telling will contact or the top of break-through the first groove;
3, in described the second groove, insert the second silicon of the second type semiconductor;
4, adopt cmp to obtain being superimposed upon the P-N thin layer of the second segment alternative arrangement on the P-N thin layer of described first paragraph alternative arrangement
Then repeat respectively step by step 1,2,3 and 4 of implementation step five, until the thickness of described P-N thin layer reaches the requirement of device reverse breakdown voltage.
The second provided by the invention is realized the manufacture method of above-mentioned super-junction device structure, comprises following processing step:
Step 1, on the first type semiconductor substrate of high concentration, carry out a kind of high resistivity first epitaxial loayer grow up;
Step 2, by photoetching and the first type semiconductor Implantation, on described epitaxial loayer, form the first type semiconductor thin layer.
Step 3, by photoetching and the second type semiconductor Implantation, on described epitaxial loayer, form the second type semiconductor thin layer.Described the first type semiconductor thin layer and described the second type semiconductor thin layer, at chip current flow region alternative arrangement, form the P-N thin layer of first paragraph alternative arrangement.
Step 4, comprise as follows step by step:
1, the second epitaxial loayer that carries out the first type semiconductor on the P-N thin layer of the described first paragraph alternative arrangement of above-mentioned steps one to three formation is grown up;
2, adopt chemical wet etching technique to form the first groove, the bottom of the first groove to contact or the P-N thin layer of the described first paragraph alternative arrangement of punch-through step one to three formation on P type thin layer top;
3, in described the first groove, insert the silicon of the second type semiconductor;
4, adopt cmp to obtain being superimposed upon the P-N thin layer of the second segment alternative arrangement on the P-N thin layer of described first paragraph alternative arrangement.
Then repeat respectively step by step 1,2,3 and 4 of implementation step four, until the thickness of P-N thin layer reaches the requirement of device reverse breakdown voltage.
The first provided by the invention and the second are realized the manufacture method of above-mentioned super-junction device structure, also comprise the steps:
Step 1, by photoetching and injection, form the trap of the second type semiconductor on the surface of described P-N thin layer;
Step 2, form grid oxygen on the surface of described P-N thin layer by thermal oxidation, and then the polysilicon of deposit the first type semiconductor or unformed silicon, and form grid region by chemical wet etching.
Step 3, by photoetching and Implantation, carry out the source region Implantation of the first type semiconductor, form source region;
Step 4, carry out interlayer film growth on front side of silicon wafer surface;
Step 5, carry out contact hole chemical wet etching;
Step 6, utilize the foreign ion of high-energy the second type semiconductor to inject, realize ohm connection of metal and the second type semiconductor trap in contact hole;
Step 7, form source electrode, the cabling of polysilicon gate in front side of silicon wafer surface metal growth-photoetching-etching;
Step 8, silicon chip back side attenuate-back face metalization, form drain electrode.
The present invention adopts the P-N laminate structure of the alternative arrangement of at least two sections, the thickness that has reduced the P-N thin layer of each alternative arrangement, has reduced depth-width ratio, has reduced the technology difficulty of the P-N thin layer of alternative arrangement, and improved the uniformity of P-N thin layer, improve the consistency of device performance.
The present invention adopts the P-N laminate structure of at least two sections of alternative arrangements, considers, under the condition of charge balance of P-N thin layer, can, to the structure independent design of the P-N thin layer of each section, facilitate the design of device architecture in entirety.
The present invention adopts the P-N laminate structure of at least two sections of alternative arrangements, by optimizing the distribution of impurity in P-N thin layer, can make the reverse breakdown origination point of device occur in current flowing district, and do not occur in the termination environment of device, can improve the proof voltage of device, the ability of resistance to current over pulse, has improved the reliability of device.
The present invention adopts the P-N laminate structure of at least two sections of alternative arrangements, can adopt easily the P-N thin layer of the alternative arrangement different from current flowing district in the termination environment of device, has facilitated the design of device terminal structure.
Brief description of the drawings
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
A schematic top plan view of the existing super-junction device of Fig. 1
A schematic cross-section of the existing super-junction device of Fig. 2
Fig. 3-Fig. 7 is the schematic diagram of embodiments of the invention
Fig. 3 is the current flowing district device architecture schematic diagram of the embodiment of the present invention one
Fig. 4 is the current flowing district device architecture schematic diagram of the embodiment of the present invention two
Fig. 5 is the current flowing district device architecture schematic diagram of the embodiment of the present invention three
Fig. 6 is the current flowing district device architecture schematic diagram of the embodiment of the present invention four
Fig. 7 is the current flowing district device architecture schematic diagram of the embodiment of the present invention five
Embodiment
All be specifically described as an example of the super junction NMOSFET device of 700 volts of drain-source reverse breakdown voltages example in the following embodiments, the semiconductor of the first type is N type semiconductor like this, and the semiconductor of the second type is P type semiconductor.
Embodiment mono-
Shown in Figure 3, be the flow of charge district device architecture schematic diagram of first embodiment of the invention.On the N-type silicon chip 01 of a low-resistivity, be formed with a N-type silicon epitaxy layer 1, the resistivity of described N-type silicon chip 01 is 0.001～0.005 ohm. centimetre, thickness is 0.2～750 micron, the resistivity of described N-type silicon epitaxy layer 1 is 1～5 ohm. centimetre (mix phosphorus or arsenic, concentration 4.83E15～8.95E14 atomicity/cubic centimetre), in described N-type silicon epitaxy layer 1, can be made up of the different epitaxial loayer of resistivity, can be also the epitaxial loayer of single resistivity.In described N-type silicon epitaxy layer 1, there is the P-N thin layer of first paragraph alternative arrangement, the thickness T 1 of the P-N thin layer of described first paragraph alternative arrangement is 15 microns, wherein 33 is P type thin layers in thin layer in first paragraph P-N, 5 microns of the width of each P type thin layer 33, resistivity is 2.83 ohm. centimetre (boron doping, impurity concentration is 4.83E15 atomicity/cubic centimetre), the 43rd, the N-type thin layer in the P-N of described first paragraph alternative arrangement in thin layer, 5 microns of the width of each N-type thin layer 43, resistivity is 1 ohm. centimetre (phosphorus doping, impurity concentration is 4.83E15 atomicity/cubic centimetre), a P type thin layer 33 and an adjacent N-type thin layer 43 form a step-length.On the P-N of described first paragraph alternative arrangement, there is the P-N thin layer of second segment alternative arrangement, in the P-N of described second segment alternative arrangement, the thickness T 2 of thin layer is 25 microns, wherein 34 is P type thin layers in thin layer in described second segment P-N, 5 microns of the width of each P type thin layer 34, resistivity is 2.83 ohm. centimetre (boron doping, impurity concentration is 4.83E15 atomicity/cubic centimetre), the 44th, the N-type thin layer in the P-N of described second segment alternative arrangement in thin layer, 5 microns of the width of each N-type thin layer 44, resistivity is 1 ohm. centimetre (phosphorus doping, impurity concentration is 4.83E15 atomicity/cubic centimetre), a P type thin layer 34 and an adjacent N-type thin layer 44 form a step-length.The thickness of the N-type silicon epitaxy layer 1 between the bottom of the P-N thin layer of described first paragraph alternative arrangement and the N-type silicon chip 01 of described low-resistivity is 2～10 microns, resistivity is 1～5 ohm. centimetre (mixing phosphorus or arsenic, concentration 4.83E15～8.95E14 atomicity/cubic centimetre).
The selection of the width of above-mentioned P thin layer and N thin layer and impurity concentration wherein, in the P-N of each section of alternative arrangement, in thin layer P thin layer, p type impurity total amount has equaled N-type total impurities in N thin layer, realize perfect charge balance, thereby made device can obtain the highest reverse breakdown voltage.In practical devices Design and manufacture, the width of P thin layer and N thin layer and impurity concentration wherein change within the specific limits, as long as can make in whole P-N thin layer (summation of the P-N thin layer of two sections of alternative arrangements) in P thin layer the absolute value of the difference of N-type total impurities in p type impurity total amount and N thin layer be less than or equal to 15% of p type impurity total amount in P thin layer, also be less than or equal to 15% of N-type total impurities in N thin layer, still can obtain higher reverse breakdown voltage.
The top of thin layer in the P-N of described second segment alternative arrangement,, in the epi region near device front, is formed with P type trap 62.In described P type trap 62, be formed with the source region 6 that a N+ Implantation forms.On silicon front, there are grid oxygen 4, polysilicon gate 5, inter-level dielectric film 7, contact hole 8 and source electrode and gate metal 9, also comprise P+ ohmic contact regions (the B Implanted acquisition after contact hole forms that a P+ Implantation forms, not shown), in described low-resistivity silicon chip 01 bottom, (be called silicon chip back side, or the device back side) has a drain electrode 10 (back metal).The feature of the part of these devices is consistent with the appropriate section of prior art, and its technical process does not repeat them here.
In the above-described embodiments, the P type thin layer 34 in the P-N of second segment alternative arrangement in thin layer must with thin layer in the P-N of the first second segment alternative arrangement in P type thin layer 33 join, can partly or entirely overlap.If P type thin layer 34 and P type thin layer 33 are all to be filled and realized by the extension of groove, the part overlapping so only has P type thin layer 34 to be retained, like this, in the time that the impurity concentration of second segment P type thin layer 34 equates with the impurity concentration of first paragraph P type thin layer 33, P type thin layer in the P-N of whole alternative arrangement in thin layer always assorted amount is not subject to the impact of the gash depth of second segment P type thin layer 34, as long as ensure that second segment P type thin layer 34 joins with first paragraph P type thin layer 33.
In the device of the present embodiment, the thickness of P-N thin layer is 40 microns, groove width is 5 microns, the homogeneity of supposing etching depth on same silicon chip be controlled within 5% (homogeneity be the maximum of depth difference in silicon chip divided by silicon chip in depth capacity and minimum-depth sum).So, by the existing technique of only having one section of P-N thin layer, 40 microns of the trench target degree of depth, in a silicon chip, the difference of the degree of depth will reach 4 microns, and the difference of the reverse breakdown voltage bringing lies prostrate at 40-80.The present embodiment, the thickness of first paragraph P-N thin layer is 15 microns, in a silicon chip, the difference of the degree of depth is 1.5 microns to the maximum, the thickness of second segment P-N thin layer is 25 microns, as long as ensure on whole silicon chip in second segment P-N thin layer that thin layer all directly contacts with the P thin layer of first paragraph P-N thin layer (can by suitably deepening the etching depth of groove of second segment P-N thin layer), the change in depth of the P thin layer of second segment P-N thin layer does not affect (the overlapping district of the P thin layer of the P thin layer of second segment P-N thin layer and first paragraph P-N thin layer to device architecture, that the P thin layer in the overlapping district of second segment P-N thin layer is etched away, recharge, device is not affected), therefore the varied in thickness of the P type thin layer of whole device just equals the variable quantity of the P thin layer of first paragraph P-N thin layer, maximum difference in silicon chip is 1.5 microns, the difference of the reverse breakdown voltage bringing lies prostrate at 15-30, there is obvious improvement than prior art.
In the present embodiment, the depth-width ratio of the P thin layer of first paragraph P-N thin layer is that the depth-width ratio of the P thin layer of 3, the two P-N thin layers is 5, is all 8 to have had significantly and reduce than depth-width ratio in prior art, has so also reduced the technology difficulty that etching groove and groove extension are filled.
Further improvement to embodiment mono-is, the P-N thin layer of the alternative arrangement of device can be by three sections, or the P-N thin layer of three sections of above alternative arrangements composition, further reduce the thickness of each section of P-N thin layer, thereby reduce the manufacturing process difficulty and the homogeneity of improving P type thickness of thin layer of device, improve the homogeneity of the reverse breakdown voltage of device.
Further improvement to embodiment mono-is, between the P-N thin layer of the adjacent alternative arrangement of different sections, the width of the P thin layer in the P-N thin layer of the alternative arrangement of a section, can with it near the P-N thin layer of alternative arrangement of another section in the width of P thin layer unequal, the design of more convenient like this device.
Further improvement to embodiment mono-is, in the P-N thin layer of the alternative arrangement of a section, in a step-length, the arrangement mode of P-N thin layer can be with not identical with the arrangement mode of P-N thin layer in a step-length in the P-N thin layer of the alternative arrangement of another section near it, the design of more convenient like this device.
Further improvement to embodiment mono-is, the concentration of p type impurity in P thin layer in the P-N thin layer of the alternative arrangement of a section, can with it near the P-N thin layer of alternative arrangement of another section in P thin layer in the concentration of p type impurity can be unequal, for example in first paragraph, the concentration of p type impurity can be below or above the concentration of p type impurity in second segment, improves the performance of device and facilitate device design.
Further improvement to embodiment mono-is, the concentration of N-type impurity in N thin layer in the P-N thin layer of the alternative arrangement of a section, can with it near the P-N thin layer of alternative arrangement of another section in N thin layer in the concentration of N-type impurity unequal, for example in first paragraph, the concentration of N-type impurity can be below or above the concentration of N-type impurity in second segment, the concentration of lower first paragraph N-type impurity can improve the reverse breakdown voltage of device, the concentration of higher first paragraph N-type impurity can improve resistance to rush of current and the proof voltage impact capacity of device, thereby improve the performance of device and facilitate device design.
Further improvement to embodiment mono-is, the P-N thin layer of one section of alternative arrangement of the most close device backside surface, be that thickness of thin layer in the P-N thin layer of first paragraph alternative arrangement is less than or equal to 20 microns, can reduce the homogeneity of P thickness of thin layer in the P-N thin layer of whole alternative arrangement by reducing this thickness, thereby improve the homogeneity of device performance.
Further improvement to embodiment mono-is, the P-N thin layer of one section of alternative arrangement of the most close device backside surface, be in the thin layer in the P-N thin layer of first paragraph alternative arrangement in N thin layer the concentration of N-type impurity be less than with it near, position is than the concentration of N-type impurity in the N thin layer in the P-N thin layer of the alternative arrangement of the second segment of its more close device front face surface, as the concentration of N-type impurity in N thin layer in the thin layer in the P-N thin layer of first paragraph alternative arrangement be 3.97E15 atomicity/cubic centimetre (1.2 ohm. centimetre), in thin layer in the P-N thin layer of second segment alternative arrangement in N thin layer the concentration of N-type impurity be 4.83E15 atomicity/cubic centimetre (1 ohm. centimetre), in corresponding P thin layer, the concentration of p type impurity equates with the concentration of N-type impurity in N thin layer in same section, so further reduce the impact of P thickness of thin layer (the etching groove degree of depth) in the P-N thin layer of first paragraph alternative arrangement, further improve the uniformity of device reverse breakdown voltage.
Further improvement to embodiment mono-is, in the P-N thin layer of first paragraph alternative arrangement, the impurity concentration of P thin layer is 4.35E15 atomicity/cubic centimetre, in the P-N thin layer of first paragraph alternative arrangement, the impurity concentration of N thin layer is 4.83E15 atomicity/cubic centimetre, makes p type impurity total amount in the P thin layer of P-N thin layer of first paragraph (the most close device backside surface a section) alternative arrangement be less than N-type total impurities in N thin layer; In the P-N thin layer of second segment alternative arrangement, the impurity concentration of P thin layer is 5.31E15 atomicity/cubic centimetre, in the P-N thin layer of second segment alternative arrangement, the impurity concentration of N thin layer is 4.83E15 atomicity/cubic centimetre, makes p type impurity in the P thin layer of P-N thin layer of second segment (more close device front face surface a section) alternative arrangement be greater than N-type total impurities in N thin layer.The ability of so further raising device proof voltage and current over pulse, improves the reliability of device.
Embodiment bis-
Fig. 4 is the flow of charge district device architecture schematic diagram of second embodiment of the invention, as different from embodiment mono-in the P-N thin layer of the alternative arrangement of Fig. 4 is, the width of the P thin layer in the P-N thin layer of first paragraph alternative arrangement is greater than the width of the P thin layer in the P-N thin layer of second segment alternative arrangement: the width of the P thin layer 33 in the P-N thin layer of first paragraph alternative arrangement is 6 microns, p type impurity concentration is 3.22E15 atomicity/cubic centimetre, the width of N thin layer 43 is 4 microns, and N-type impurity concentration is 4.83 E15 atomicity/cubic centimetres; 5 microns of the width of the P thin layer 34 in the P-N thin layer of the alternative arrangement of second segment, p type impurity concentration is 4.83E15 atomicity/cubic centimetre; The width of N thin layer 44 is 5 microns, and N-type impurity concentration is 4.83E15 atomicity/cubic centimetre.Because the width of the P thin layer in the P-N thin layer of first paragraph alternative arrangement is greater than the width of the P thin layer in the P-N thin layer of second segment alternative arrangement, even if make like this in the manufacture of the P thin layer in the P-N of second segment alternative arrangement thin layer, the width of groove has certain variation, there is certain deviation position to the P thin layer in the P-N thin layer of first paragraph alternative arrangement, as long as variable quantity sum is no more than 0.5 micron, P thin layer one in the P-N thin layer of second segment alternative arrangement drops on the P thin layer in the P-N thin layer of first paragraph alternative arrangement surely, further improve the stability of technique, improve the homogeneity of device performance.
To the described improvement of embodiment mono-, in embodiment bis-, can implement equally, as long as the N-type total impurities of the P-N thin layer of first and second sections of alternative arrangements of guarantee and p type impurity total amount can meet the requirement of charge balance, the design of each impurity concentration can be optimized according to the requirement of device performance and reliability.
Embodiment tri-
Fig. 5 is the flow of charge district device architecture schematic diagram of third embodiment of the invention, as different from embodiment mono-in the P-N thin layer of the alternative arrangement of Fig. 5 is, the width of the P thin layer in the P-N thin layer of first paragraph alternative arrangement is less than the width of the P thin layer in the P-N thin layer of second segment alternative arrangement: the width of the P thin layer 33 in the P-N thin layer (the P-N thin layer of one section of alternative arrangement of the most close device backside surface) of first paragraph alternative arrangement is 4.5 microns, P thin layer 33 impurity concentrations are 4.83E15 atomicity/cubic centimetre, the width of N thin layer 43 is 5.5 microns, N thin layer 43 impurity concentrations are 5.07E15 atomicity/cubic centimetre, the P-N thin layer of second segment alternative arrangement is (near first paragraph, near the P-N thin layer of one section of alternative arrangement of device front face surface) in the width of P thin layer 34 be 5 microns, P thin layer 34 impurity concentrations are 4.83E15 atomicity/cubic centimetre, the width of N thin layer 44 is 5 microns, N thin layer 44 impurity concentrations are 4.83E15 atomicity/cubic centimetre, be the P thin layer width of the P-N thin layer of first paragraph alternative arrangement be less than with it near, position is than the width of the P thin layer in the P-N thin layer of the alternative arrangement of the second segment of its more close device front face surface, in the N thin layer of the P-N thin layer of first paragraph alternative arrangement the concentration of N-type impurity be greater than with it near, position is than the concentration of N-type impurity in the N thin layer in the P-N thin layer of the alternative arrangement of the second segment of its more close device front face surface.Ensure like this in the N thin layer of P-N thin layer of first paragraph (the most close device backside surface a section) alternative arrangement that N-type total impurities is greater than in same section the summation of p type impurity in P thin layer, increase the not depleted N-type extrinsic region at the close device back side, or make can exhaust mutually with the medium-sized impurity of P-N thin layer of second segment alternative arrangement near the part N impurity in the P-N thin layer at the device back side, thereby further improve the ability of device proof voltage and current over pulse, improve the reliability of device.
To the described improvement of embodiment mono-, in embodiment tri-, can implement equally, as long as the N-type total impurities of the P-N thin layer of first and second sections of alternative arrangements of guarantee and p type impurity total amount can meet the requirement of charge balance, the design of each impurity concentration can be optimized according to the requirement of device performance and reliability.
Embodiment tetra-
Fig. 6 is the flow of charge district device architecture schematic diagram of four embodiment of the invention, as different from embodiment mono-in the P-N thin layer of the alternative arrangement of Fig. 6 is, P-N thin layer arrangement mode in a step-length in the P-N thin layer 35 of one section of alternative arrangement of the most close device backside surface, be different from it near, position is than P-N thin layer arrangement mode in 36 1 step-lengths of the P-N thin layer of the alternative arrangement of another section of its more close device front face surface.As Fig. 6, in first paragraph P-N thin layer 35, in a step-length, comprise P thin layer a-N thin layer b-P thin layer c-N thin layer d, wherein a=c=1.5 micron, b=2 micron, d=5 micron, the p type impurity concentration of P thin layer is 1.01E16 atomicity/cubic centimetre, the N-type impurity concentration of N thin layer is 4.83E15 atomicity/cubic centimetre, the total amount of p type impurity is less than the total amount of N-type impurity, in the second segment P-N thin layer 36 being located thereon, comprises P thin layer e-N thin layer f in a step-length, wherein e=5 micron, f=5 micron.The p type impurity concentration of P thin layer is 5.31E15～4.83E15 atomicity/cubic centimetre, and the N-type impurity concentration of N thin layer is 4.83E15 atomicity/cubic centimetre, and the total amount of p type impurity is more than or equal to the total amount of N-type impurity.
Through improvement above, make in the P-N thin layer 35 of the first paragraph alternative arrangement near silicon chip back side, there is local high electric field, thereby make device reverse breakdown origination point be easy to appear in the P-N thin layer of first paragraph alternative arrangement, puncture the electron hole centering forming while generation, electronics is drawn into silicon chip back side very soon, hole is drawn in the process of front surface, by the electronegative space charge neutralization in second segment alternative arrangement P-N thin layer 36, maximum field in second segment alternative arrangement P-N thin layer is reduced, thereby the proof voltage overshoot of device and the ability of resistance to current over pulse are improved.
Further improvement to embodiment mono-to embodiment tetra-arbitrary embodiment is, with reference to the structure of figure 2, only has the second alternative arrangement P-N thin layer in termination environment, there is no first paragraph alternative arrangement P-N thin layer, so more make device reverse breakdown origination point be easy in the P-N thin layer of the first paragraph alternative arrangement that appears at current flowing district, thereby improved the proof voltage overshoot of device and the ability of resistance to current over pulse.
To all embodiment of above-described embodiment one to embodiment tetra-, and in improving, employing can adopt following processing step to form alternative arrangement P-N thin layer:
Step 1, on the N-type substrate 01 of high concentration, carry out N-type first epitaxial loayer grow up;
Step 2, by chemical wet etching, on described the first epitaxial loayer, form the first groove of certain depth-width ratio; Can be at described the first epi-layer surface growth deielectric-coating before photoetching, after etching, can retain like this some deielectric-coating as the barrier layer of cmp afterwards.The epi-layer surface deielectric-coating of also can not growing up, can be directly with photoresist as the protective layer of etching groove.
Step 3, P type the first silicon of inserting in described groove, P type the first silicon can be P type epitaxial loayer; Can adopt low pressure chemical vapor deposition or low pressure epitaxy technique to form described P type the first silicon.
Step 4, utilize cmp to obtain the P-N thin layer of first paragraph alternative arrangement.If there be the barrier layer of deielectric-coating as cmp, after grinding, need deielectric-coating to remove.
Step 5, comprise as follows step by step:
1, the second epitaxial loayer that carries out N-type on the P-N of described first paragraph alternative arrangement thin layer is grown up;
2, adopt chemical wet etching technique to form the second groove, the bottom of described the second groove to contact or break-through described in the top of P thin layer of P-N thin layer of first paragraph alternative arrangement; The bottom that need to ensure the second groove on positions all in silicon chip to contact or break-through described in the top of P thin layer of P-N thin layer of first paragraph alternative arrangement, therefore the technique of the second etching groove can suitably increase etch amount.
3, in described the second groove, insert the second silicon of P type semiconductor; The second silicon of P type semiconductor can be P type epitaxial loayer.Can adopt low-pressure chemical vapor phase deposition or low pressure epitaxy technique to form described P type the second silicon.
4, adopt chemical mechanical milling tech to obtain being superimposed upon the P-N thin layer of the second segment alternative arrangement on the P-N thin layer of first paragraph alternative arrangement.
So just obtain the P-N thin layer of the alternative arrangement of two sections.
Due to than prior art, adopt the P-N laminate structure of two sections of alternative arrangements, reduce the difficulty of technique, and improve the homogeneity of gash depth, therefore improve the homogeneity of P thickness of thin layer in the P-N thin layer of whole alternative arrangement, thereby improved the homogeneity of the reverse breakdown voltage of device.
Further improvement to above-mentioned processing step is, after completing above-mentioned processing step, repeat respectively step by step 1,2,3 and 4 of implementation step five, until the thickness of described P-N thin layer reaches the requirement of device reverse breakdown voltage, the thickness of the P-N thin layer of each section of alternative arrangement of so further minimizing, has reduced the difficulty of technique.
Embodiment five
Fig. 7 is the flow of charge district device architecture schematic diagram of fifth embodiment of the invention, as the different from embodiment mono-of the P-N thin layer of the alternative arrangement of Fig. 7 are, in the P-N thin layer of one section of alternative arrangement of the most close device backside surface, P-N thin layer is to utilize epitaxy technique, and photoetching and Implantation form.
In the manufacture craft of embodiment five, comprise following processing step:
Step 1, a kind of low resistivity of carrying out on the N type semiconductor substrate 01 of high concentration (as 1-5 ohm. centimetre) zero degree N-type epitaxial loayer grow up, grow up afterwards the first epitaxial loayer of a high resistivity, described the first epitaxial loayer 38 can be N-type, and resistivity can be greater than 50 times of described zero degree N-type epilayer resistance rate;
Low resistivity (as 1-5 ohm. centimetre) the thickness of zero degree N-type epitaxial loayer be 2-10 micron.
Step 2, by photoetching and N type semiconductor Implantation, as phosphonium ion inject, on described the first epitaxial loayer, form N-type thin layer district.
Step 3, by photoetching and P type semiconductor Implantation, as boron inject, on described the first epitaxial loayer, form P type thin layer district.
The ion that step 2 and step 3 are injected is above activated and spreads in high-temperature technology after this, forms the P-N thin layer of the first paragraph alternative arrangement being made up of P type thin layer 37 and N-type thin layer 38.In the P-N thin layer of first paragraph alternative arrangement, the resistivity of N thin layer is greatly about 1-5 ohm. centimetre, the about 6-8 micron of thickness of P-N thin layer.
Step 4, comprise as follows step by step:
1, the second epitaxial loayer that carries out N type semiconductor on the P-N thin layer of the described first paragraph alternative arrangement of above-mentioned steps one to three formation is grown up, and the thickness of described N type semiconductor the second epitaxial loayer is 32～34 microns, 1～5 ohm of resistivity. centimetre.
2, adopt chemical wet etching technique to form the first groove, the bottom of described the first groove to contact or the P-N thin layer of the described first paragraph alternative arrangement of punch-through step one to three formation on P type thin layer top; The degree of depth of described the first groove is greater than the thickness of N type semiconductor the second epitaxial loayer, for example 35-36 micron, ensures in silicon chip P type thin layer top on the P-N thin layer of described first paragraph alternative arrangement of the bottom of the first groove contact described in all positions or punch-through step one to three formation.
3, in described the first groove, insert the silicon 39 of P type semiconductor, as P type epitaxial silicon.Can adopt low pressure chemical vapor deposition or low pressure epitaxy technique to form the silicon of described P type semiconductor.
4, adopt cmp to obtain being superimposed upon the P-N thin layer of the second segment alternative arrangement on the P-N thin layer of described first paragraph alternative arrangement.
The P-N thin layer of second segment alternative arrangement is made up of P type thin layer 39 and N-type thin layer 40.
Adopt above-mentioned process, the P-N thin layer of the alternative arrangement that one-time process in prior art is completed, being divided into two sections completes, first paragraph is undertaken by epitaxial diposition, photoetching and Implantation, second segment is by etching groove and groove epitaxial growth, reduce technology difficulty, improved the homogeneity of device.
Further improvement to above-mentioned process is, after completing above-mentioned processing step, repeat respectively step by step 1,2,3 and 4 of implementation step four, until the thickness of described P-N thin layer reaches the requirement of device reverse breakdown voltage, the thickness of the P-N thin layer of each section of alternative arrangement of so further minimizing, has reduced the difficulty of technique.
In the device making technics of arbitrary embodiment of above-described embodiment one to embodiment five, also comprise the steps,
Step 1, by photoetching and injection, form the trap of the second type semiconductor on the surface of described P-N thin layer;
Step 2, form grid oxygen on the surface of described P-N thin layer by thermal oxidation, and then the polysilicon of deposit the first type semiconductor or unformed silicon, and form grid region by chemical wet etching.
Step 3, by photoetching and Implantation, carry out the source region Implantation of the first type semiconductor, form source region;
Step 4, carry out interlayer film growth on front side of silicon wafer surface;
Step 5, carry out contact hole chemical wet etching;
Step 6, utilize the foreign ion of high-energy the second type semiconductor to inject, realize ohm connection of metal and the second type semiconductor trap in contact hole;
Step 7, form source electrode, the cabling of polysilicon gate in front side of silicon wafer surface metal growth-photoetching-etching;
Step 8, silicon chip back side attenuate-back face metalization, form drain electrode.
In all embodiment, if N-type is changed into P type, P type changes N-type (semiconductor that is the first type is P type semiconductor, and the semiconductor of the second type is N type semiconductor) into, just obtains the manufacture method of corresponding PMOSFET device above.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (10)

1. a super junction-semiconductor device, is characterized in that: the P-N thin layer of the alternative arrangement of device is made up of the P-N thin layer of at least two sections of alternative arrangements in the direction perpendicular to device surface; Between the P-N thin layer of the adjacent alternative arrangement of different sections, the width of the P thin layer in the P-N thin layer of the alternative arrangement of a section, can with equate with the width of the P thin layer in the P-N thin layer of the alternative arrangement of another section near it, also can be unequal; The width of the N thin layer in the P-N thin layer of the alternative arrangement of a section, can with equate with the width of the N thin layer in the P-N thin layer of the alternative arrangement of another section near it, also can be unequal; In the P-N thin layer of the alternative arrangement of a section, in a step-length, the arrangement mode of P-N thin layer can be with identical with the arrangement mode of P-N thin layer in a step-length in the P-N thin layer of the alternative arrangement of another section near it, also can be not identical; The concentration of p type impurity in P thin layer in the P-N thin layer of the alternative arrangement of a section, can with equate with the concentration of p type impurity in P thin layer in the P-N thin layer of the alternative arrangement of another section near it, also can be unequal; The concentration of N-type impurity in N thin layer in the P-N thin layer of the alternative arrangement of a section, can with equate with the concentration of N-type impurity in N thin layer in the P-N thin layer of the alternative arrangement of another section near it, also can be unequal.
2. super junction-semiconductor device as claimed in claim 1, it is characterized in that, the width of the P thin layer in the P-N thin layer of the alternative arrangement of a section, be greater than with it near, position is than the width of the P thin layer in the P-N thin layer of the alternative arrangement of another section of its more close device front face surface.
3. super junction-semiconductor device as claimed in claim 1, is characterized in that, the thickness of thin layer of the P-N thin layer of one section of alternative arrangement of the most close device backside surface is less than or equal to 20 microns.
4. super junction-semiconductor device as claimed in claim 1, it is characterized in that, in the N thin layer of the P-N thin layer of one section of alternative arrangement of the most close device backside surface the concentration of N-type impurity be less than with it near, position is than the concentration of N-type impurity in the N thin layer in the P-N thin layer of the alternative arrangement of another section of its more close device front face surface.
5. super junction-semiconductor device as claimed in claim 1, is characterized in that, in the P thin layer of the P-N thin layer of one section of alternative arrangement of the most close device backside surface, p type impurity total amount is less than N-type total impurities in N thin layer; With near it, position is greater than N-type total impurities in N thin layer than p type impurity total amount in P thin layer in the P-N thin layer of the alternative arrangement of another section of its more close device front face surface.
6. super junction-semiconductor device as claimed in claim 1, it is characterized in that, the width of the P thin layer in the P-N thin layer of one section of alternative arrangement of the most close device backside surface, be less than with it near, position is than the width of the P thin layer in the P-N thin layer of the alternative arrangement of another section of its more close device front face surface.
7. super junction-semiconductor device as claimed in claim 1, it is characterized in that, P-N thin layer arrangement mode in a step-length in the P-N thin layer of one section of alternative arrangement of the most close device backside surface, be different from it near, position is than P-N thin layer arrangement mode in step-length of the P-N thin layer of the alternative arrangement of another section of its more close device front face surface.
8. a manufacture method for super junction-semiconductor device, is characterized in that, comprises following processing step:
Step 1, on the first type semiconductor substrate of high concentration, carry out the first type semiconductor first epitaxial loayer grow up;
Step 2, by chemical wet etching, on described the first epitaxial loayer, form the first groove of certain depth-width ratio;
Step 3, in described the first groove, insert the first silicon of the second type semiconductor;
Step 4, utilize cmp to obtain the P-N thin layer of first paragraph alternative arrangement.
Step 5, comprise as follows step by step:
1, the second epitaxial loayer that carries out the first type semiconductor on the P-N of described first paragraph alternative arrangement thin layer is grown up;
2, adopt chemical wet etching technique to form the second groove, the bottom of described the second groove to contact or break-through described in the top of the first groove;
3, in described the second groove, insert the second silicon of the second type semiconductor;
4, utilize cmp to obtain being superimposed upon the P-N thin layer of the second segment alternative arrangement on the P-N thin layer of described first paragraph alternative arrangement
Then repeat respectively step by step 1,2,3 and 4 of implementation step five, until the thickness of P-N thin layer reaches the requirement of device reverse breakdown voltage.
9. a manufacture method for super junction-semiconductor device, is characterized in that, comprises following processing step:
Step 1, on the first type semiconductor substrate of high concentration, carry out a kind of high resistivity first epitaxial loayer grow up;
Step 2, by photoetching and the first type semiconductor Implantation, on described epitaxial loayer, form the first type semiconductor thin layer.
Step 3, by photoetching and the second type semiconductor Implantation, on described epitaxial loayer, form the second type semiconductor thin layer.The first type semiconductor thin layer and the second type semiconductor thin layer, at chip current flow region alternative arrangement, form the P-N thin layer of first paragraph alternative arrangement.
Step 4, comprise as follows step by step:
1, the second epitaxial loayer that carries out the first type semiconductor on the P-N thin layer of the described first paragraph alternative arrangement of above-mentioned steps one to three formation is grown up;
2, adopt chemical wet etching technique to form the first groove at described the second epitaxial loayer, the bottom of described the first groove to contact or the P-N thin layer of the described first paragraph alternative arrangement of punch-through step one to three formation on P type thin layer top;
3, in described the first groove, insert the silicon of the second type semiconductor;
4, adopt cmp to obtain being superimposed upon the P-N thin layer of the second segment alternative arrangement on the P-N thin layer of first paragraph alternative arrangement.
Then repeat respectively step by step 1,2,3 and 4 of implementation step four, until the thickness of P-N thin layer reaches the requirement of device reverse breakdown voltage.
10. as the manufacture method as described in arbitrary in claim 8 and 9, it is characterized in that: also comprise the steps,
Step 1, by photoetching and injection, form the trap of the second type semiconductor on the surface of described P-N thin layer;
Step 2, form grid oxygen on the surface of described P-N thin layer by thermal oxidation, and then the polysilicon of deposit the first type semiconductor or unformed silicon, and form grid region by chemical wet etching.
Step 3, by photoetching and Implantation, carry out the source region Implantation of the first type semiconductor, form source region;
Step 4, carry out interlayer film growth on front side of silicon wafer surface;
Step 5, carry out contact hole chemical wet etching;
Step 6, the foreign ion that carries out high-energy the second type semiconductor inject, and realize ohm connection of metal and the second type semiconductor trap in contact hole;
Step 7, form source electrode, the cabling of polysilicon gate in front side of silicon wafer surface metal growth-photoetching-etching;
Step 8, silicon chip back side attenuate-back face metalization, form drain electrode.
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