CN105304687A - End connection device for nanotube MOSFET - Google Patents
End connection device for nanotube MOSFET Download PDFInfo
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- CN105304687A CN105304687A CN201510418871.XA CN201510418871A CN105304687A CN 105304687 A CN105304687 A CN 105304687A CN 201510418871 A CN201510418871 A CN 201510418871A CN 105304687 A CN105304687 A CN 105304687A
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Abstract
The present invention mainly relates to a semiconductor power device. The end connection structure of a power device comprises a plurality of end connection groups formed in a light doping epitaxial layer of a first conduction type and above a heavy doping semiconductor substrate of a second conduction type. Each end connection group comprises one groove formed in the light doping epitaxial layer of the first conduction type, all the side walls of the groove are covered by a plurality of epitaxial layers of alternated conduction types, and the plurality of epitaxial layers are precipitated at two opposite edges. All the side walls of the groove are basically symmetrical with a central gap filling layer between two innermost epitaxial layers of the deepest conduction type.
Description
Technical field
The present invention relates generally to semiconductor power device.More precisely about structure and the collocation method of alternating-doping nanotube, to utilize easy preparation technology, what preparation had the puncture voltage of improvement and significantly reduced resistance can the semiconductor power device of charge balance of flexible expansion.
Background technology
Semiconductor device comprises mos field effect transistor (MOSFET) device, and with the power semiconductor of vertical this structure of super junction, its electric property is well known, and in multinomial patent document or other open source literatures, have relevant discussion.Patent document disclosed in these for example comprises: U.S. Patent number US5438215, US5216275, US4754310, US6828631 etc.In addition copywriter FUJIHIRA also proposes the structure of vertical super-junction device in " semiconductor super-junction device is theoretical " (being loaded in volume 23S-241 page in " Japanese Applied Physics bulletin " October the 36th in 1979) literary composition.Exactly, Fig. 1 C represents the vertical trench MOSFET super-junction device (Fig. 2 A in FUJIHIRA article) that FUJIHIRA proposes.FUJIHIRA also proposes a kind of vertical semiconductor devices with drift region in U.S. Patent number US6097063, if device is in conduction mode, then drift current flows, if device is in Disconnected mode, then drift current exhausts.Drift region is as the spacer region with the discrete drift region of multiple first conduction type and multiple second conduction type, and wherein each spacer region is parallel is positioned among contiguous drift region, thus can form P-N junction respectively.In U.S. Patent number US6608350, propose a kind of vertical super-junction device being furnished with dielectric material layer filling groove.But as hereinbefore set forth, the structure of these super-junction devices and service behaviour still run into many technology limitation, thus limit the broad practice of these devices.
Exactly, traditional preparation technology and the low series resistance of device architecture reduce puncture voltage further, comprise the device being furnished with this structure of super junction, still face and manufacture difficulty.Traditional high-power component needs multiple consuming time, complicated, expensive preparation technology just can make structure usually, limits practical application and the purposes of high-voltage semi-conductor power device.Or rather, some technique preparing high voltage power device is very complicated, and output and productive rate are all very low.
Compared with conventional art, super junction technology has the resistance RDSON not needing excessively to increase between drain-source, just can obtain the advantage of high breakdown voltage (BV).For the power transistor cell of standard, puncture voltage depends on the low-doped drift layer of wafer to a great extent.Therefore, drift layer has larger thickness and relatively low doping content, can obtain higher rated voltage.But this also will significantly improve the effect of RDSON resistance.In traditional power device, resistance RDSON has following functional relation: RDSON ∝ BV
2.5.
By comparison, there is the cell configuration charge balance drift region of this structure of super junction.Then resistance RDSON and puncture voltage have desirable functional relation, are expressed as: RDSON ∝ BV.
For high-voltage applications, by designing and preparing the semiconductor power device with super-junction structures, device performance must be improved, to reduce resistance RDSON, obtain high-breakdown-voltage.In drift region, the region of passage has contrary conduction type.Drift region can heavy doping relatively, as long as with the alloy doping of similar films of opposite conductivity near the region of passage.When off-state, the charge balance in two regions, makes drift region exhaust, and can bear high voltage.This is called super junction effect.When on-state, because doping content is higher, therefore drift region has lower resistance RDSON.Research shows 1E12/cm
2region dopant concentration for super-junction device drift region the best.
But, when traditional super junction technology is for the preparation of power device, the limitation that still possesses skills and difficulty.The design feature of these devices and preparation technology are unfavorable for the autgmentability of low pressure to high-voltage applications in addition.In other words, certain methods is used for relative-high voltage rated, high cost and/or too tediously long.And, in the device of original technology, be difficult to the thin vertical channel preparing super junction area.Hereafter will discuss further, these traditional devices with different structure feature made by various preparation method, often kind has limitation and difficulty, hinders the practical application commercially of these devices.
The semiconductor power device structure of high-voltage applications has three basic forms of it.For the VDMOS of standard not introducing charge balance functional characteristics, the first type comprises the device that utilization normal structure is as shown in Figure 1A made.For these reasons, according to the I-V performance measurement of this types of devices and the further confirmation of sunykatuib analysis, it does not increase above the puncture voltage of performance one-dimensional theory figure (i.e. the Johnson limit).With the device of this structure owing to having very low drain electrode drift region doping content, there is higher conducting resistance usually, to meet the requirement of high-breakdown-voltage.If in order to the conducting resistance RDSON reducing device, such device needs to possess very large wafer size usually.Although this device has the advantage such as easy preparation technology and very low manufacturing cost, but in standard packaging and be not suitable for high electric current low resistance application, its main deficiency is: wafer cost price costliness (because every wafer on wafer or chip very few), unlikely standard accreditation encapsulation in hold larger wafer.
The device of the second type comprises the structure with two-dimensional charge balance, for specifying resistance acquisition higher than the puncture voltage of the Johnson limit, or is the ratio resistance (RDSON* area product) that appointment puncture voltage obtains lower than the Johnson limit.The device architecture of the type is commonly referred to the device with super junction technology.In super-junction structures, charge balance, along the direction paralleled with current flowing in the drift drain region of vertical devices, according to the PN junction configured in oxide-bypass device or by field plate techniques, makes device obtain higher puncture voltage.The device of the third type comprises three-dimensional charge balance, and direction is all coupled horizontal and vertical.Owing to the object of the invention is to device architecture and the preparation technology of improvement super junction technical configuration, to obtain two-dimensional charge balance, therefore hereafter will discuss with the limitation of super-junction device and difficulty.
Figure 1B represents the profile of super-junction device, by increasing the drain doping concentration in drift region, keeps specific puncture voltage simultaneously, reduces the ratio resistance (Rsp, resistance is multiplied by active region area) of device.Obtain charge balance by being formed in P-type vertical pillars in drain electrode, the transverse direction drained under causing high pressure exhausts completely, thus at N+ substrate place's pinch off and protection channel do not affect by high voltage drain.Figure 13 for example in European patent 0053854 (1982), U.S. Patent number US4754310 and U.S. Patent number US5216275 proposes this technology.In above-mentioned file, vertical super junction is the vertical pillars as N and P type alloy.In vertical DMOS, by sidewalls orthogonal structure, obtain vertical electric charge balance, form in doping column, as shown in the figure.Except doping column, configurable doping float island, to increase puncture voltage or to reduce resistance, described in U.S. Patent number US4134123 and U.S. Patent number US6037632.What this super junction device structure still relied on P-district exhausts the impact that protection grid/passage do not drained.The structure of float island is subject to the limitations such as the technical difficulty of charge storage and switch problem.The vertical pillars preparing alternating conductivity type is very difficult, especially when column is very dark and/or column width is smaller.For such device of super junction, because method needs multiple step, and part steps slowly, output is very low, therefore preparation method is usually very complicated, expensive, needs the processing time grown very much.
In addition, for vertical super-junction device (VSJD), preparation technology is very difficult in etching or filling groove.Subject matter comprises to be needed to use epitaxial loayer filling groove, needs the interface place avoiding the epitaxial loayer being covered with trenched side-wall to be to carry out merging in the center of groove to produce cavity when utilizing epitaxial loayer filling groove.When accompanying drawing 1D (U.S. Patent number US6608350) middle expression material fills up gap (Fig. 1 D), when the gap filling difficulty that sidewall approximately causes in producing cavity when 90 °.In addition, charge balance and puncture voltage very responsive for the Sidewall angles of groove.According to the technique of conventional method, multiple extension and boron element infusion, cause wider P column and N column, reduces device performance.These manufacturing process also improve manufacturing cost.For these reasons, traditional structure and preparation method are subject to the restriction of slow, expensive manufacturing process, for uneconomical extensive use.
Therefore, the new device structure and the manufacture method that manufacture power device must be proposed in power semiconductor Design and manufacture field, to solve above-mentioned difficulties and limitation.
Summary of the invention
Leading statement, the application be in the U.S. Patent Application No. submitted on August 26th, 2012 be US13/594, the partial continuous application (CIP) of the pending United States application case of 837, above-mentioned application case is the U.S. Patent number US13/065 submitted on March 31st, 2011, the continuous application of 880, existing U.S. Patent number is US8263482, is the U.S. Patent Application No. US12/319 submitted on December 31st, 2008, the divisional application of 164.Hereby quote it in full with for referencial use.
Therefore, one aspect of the present invention is to propose a kind of new and improved device architecture and manufacture method, preparation doping column in drift region, realizes charge balance with treatment process simply and easily.By storehouse multiple in etching groove as the epitaxial loayer of nanotube, realize Simplified flowsheet, etching groove has larger opening, is about 5 to 10 microns, is surrounded by the column of 3 to 5 microns.The epitaxial loayer of growth different-thickness, from 1 micron with down to several microns, nanotube is formed with N and the P type alloy replaced, by the center slot being less than the width (being in most cases less than 1 micron or 1 micron) that specific fill process is arranged, filling groove.Then, fill center slot with gap filling layer, gap filling layer can be insulation, the such as growth of thermal growth oxide, deposition oxide, deposit dielectric material or intrinsic or depositing silicon (preferably regrowth silicon on the silicon of deposition).Gap filling dielectric layer can have extremely light dope or unadulterated dielectric layer.Exemplarily, the doping content of gap filling is equal to or less than 10% of contiguous nanotube doping content.Residue gap is filled as nanotube, but is difficult to prepare exactly, and possibly cannot realize charge balance.Therefore, one gap filling more flexibly must be configured.Simplify preparation technology, utilize technical module and the equipment of standard, most standard preparation technology can be carried out easily.Thus solve above-mentioned technical difficulty and limitation.
Exactly, one aspect of the present invention is the device architecture and the manufacture method that propose a kind of novel improvement, in almost vertical groove, prepare the nanotube of multiple alternating conductivity type, first adulterated with original epitaxial loayer before etching groove and extension are filled.And regulate the doping content of nanotube and column, realize charge balance with this.And multiple nanotube has 2E12/cm
2(can regard two halves as, every half is 1E12/cm
2the region dopant concentration of)/nanotube, to optimize charge balance.Multiple nanotube as the passage (N-type dopen Nano pipe is as the conductive channel of N-type device) in zonule, to form the semiconductor power device of low Rdson.
Another aspect of the present invention is to propose a kind of new and improved device architecture and manufacture method, prepares the nanotube of multiple alternating conductivity type in vertical groove, and nanotube thickness is about 1 micron with down to several microns.Exemplarily, each groove can hold 5 to 20 conductive channels (nanotube).Compared with the traditional structure of a conductive channel super junction power device, the resistance of nano tube structure of the present invention can reduce by 5 to 10 times than the resistance of traditional super-junction device.
Another aspect of the present invention is to propose a kind of new and improved device architecture and manufacture method, by the groove of etching with sizable inclination angle (inclination angle is determined according to vertical line) sidewall, in vertical groove, prepare the nanotube of multiple alternating conductivity type.The inclination angle that silicon trench is conventional is about 1 ° (if relative to channel bottom plane survey, angle then should be 89 °).Exemplarily, inclination angle can be 5 ° to 1 °, obviously can not reduce the performance of power semiconductor.
The width of groove can be increased to surface from channel bottom; Multiple groove width (groove step change width is about 0.5 to 2 micron) can be had, therefore can configure the column of different in width, make filling easier.
Owing to utilizing extremely lightly doped parent material can flexible charge balance, therefore can use very large inclination angle, etch large groove, form column, and regulate the doping content of nanotube, without the need to being strict with the angle of trenched side-wall.Because column is light dope, only produce slight influence to charge balance, therefore the different in width of column can not appreciable impact charge balance.And because pipe is in growth, no matter how inclination angle changes, and the thickness of each nanotube is consistent.Therefore, a kind of convenient, economic preparation technology can be realized.
Another aspect of the present invention is to propose a kind of new and improved device architecture and manufacture method, prepares the nanotube of multiple alternating conductivity type in vertical groove, obtains charge balance as conductive channel.Above-mentioned basic super-junction structures can be configured, to prepare the vertical devices of number of different types, include but not limited to the devices such as MOSFET, bipolar junction transistor (BJT), diode, junction field effect transistor (JFET), igbt (IGBT).
Mainly propose a kind of semiconductor power device in preferred embodiment of the present invention, be deposited in the Semiconductor substrate containing multiple groove.Each groove epitaxial loayer of multiple alternating conductivity type is filled, and forms and is used as the nanotube of conductive channel, thus to be stacked into be the layer extended along sidewall direction, and insulating barrier fills the merging gap in each groove.In an exemplary embodiment, the multiple grooves between nanotube merge gap and are substantially deposited on groove center, and ditch groove center is separated by column, and the width of each column is about the half to 1/3 of groove width.
In another exemplary embodiments, each groove in multiple groove has the width of 10 microns, is separated by the groove of column and surrounding, and the width of circumferential grooves is about 3 to 5 microns.In another exemplary embodiments, each groove in multiple groove has the width of 10 microns, and fills with the epitaxial loayer of alternating conductivity type, and form nanotube, the thickness of nanotube is about 0.2 to 2 micron.In an exemplary embodiment, the depth bounds in semiconductor column district is 10 to 120 microns, and in multiple groove, the degree of depth of each groove is about 5 to 120 microns.Exemplarily, the device of 10 micrometer depth carrying 100V can be utilized, and the degree of depth of 120 microns can be used for the device carrying 1200V.
In an exemplary embodiment, Semiconductor substrate comprises N+ substrate, and the bottom section below nanotube and column form N+ nanotube assembly section, and the bottom of nanotube combines, and they are connected to base substrate district.Exemplarily, this nanotube assembly section can be diffusion region bottom N+, by diffuseing to form from base substrate district, or can be injected by top (pilot process in nanotube growth), or after backgrind, carry out back injection, hereafter will be described.Thus formed and the diffusion base area of base substrate identical conduction type at the bottom section that P and N-type nanotube are positioned at channel bottom separately, and the bottom section of column between adjacent trenches forms the diffusion column district with base substrate identical conduction type.In another optional but nonrestrictive embodiment, have multiple grooves of sidewall with inclination angle and the end face of Semiconductor substrate or the plane at substrate place rectangular.In another exemplary embodiments, Semiconductor substrate comprises N+ substrate, and P-type epitaxial loayer is positioned on N+ substrate, to open multiple groove.
The invention allows for a kind of preparation method of semiconductor power device, in the N++ Semiconductor substrate with lightly doped thick N-or P-epitaxial loayer.The method is included between light dope column and opens multiple deep trench, fully fills this deep trench, be full of and cover the end face of Semiconductor substrate by top epitaxial layer with multiple epitaxial loayers of alternately N and P doping.With the very light silicon material layer of doped in concentrations profiled or the dielectric layer of thermal growth oxide or deposition, fill residue gap completely.The method comprises and utilizes CMP (chemico-mechanical polishing) method, removes epitaxial loayer downwards, until initial leg surface.After CMP, by injecting or epitaxial growth, make the N layer that thickness is 1-2 micron.
The invention allows for a kind of optional method preparing semiconductor power device in light dope single crystalline substrate (not with initial epitaxial layer).As mentioned above, groove and nanotube are formed in single crystalline substrate, but substrate back is grounded to nanotube, and inject at back or a growth heavily doped base substrate.
According to another aspect of the present invention, end on structure in semiconductor power device comprises multiple termination group, be formed in the light dope epitaxial loayer of the first conduction type, the light dope epitaxial loayer of the first conduction type is positioned at the heavily-doped semiconductor types of flexure of the second conduction type, wherein each termination group comprises a groove be formed in the first conduction type light dope epitaxial loayer, wherein all sidewalls of groove are all covered by multiple epitaxial loayers of alternating conductivity type, multiple epitaxial deposition is on two opposite side of groove, with center slot packed layer almost symmetry, center slot packed layer is deposited between two innermost epitaxial loayers, the bosom conduction type of epitaxial loayer is consistent with the first conduction type.
In one alternate embodiment, provide a kind of end on structure arranged on the semiconductor wafer, described end on structure surrounds the active device region of semiconductor power device, comprise: multiple termination group be formed in the light dope epitaxial loayer of the first conduction type, at the heavily-doped semiconductor types of flexure of the second conduction type, wherein each termination group comprises a groove be formed in the light dope epitaxial loayer of the first conduction type, wherein trenched side-wall is covered by the epitaxial loayer of multiple alternating conductivity type, multiple epitaxial loayer is arranged on groove opposite side, and relative to the intermediate gap packed layer almost symmetry between the innermost epitaxial loayer being arranged on two bosom conduction types.Can be understood as, second group of epitaxial loayer of multiple alternating conductivity type that first group of epitaxial loayer of multiple alternating conductivity type of in opposite side, a limit or sidewall adhering to and another limit or sidewall adhere to is arranged in the mode that this packed layer is symmetrical for symmetric points are rendered as, namely and also namely an innermost epitaxial loayer between be provided with an intermediate gap near groove center near groove center also in an innermost epitaxial loayer and second group of epitaxial loayer in this first group of epitaxial loayer, packed layer is positioned among this intermediate gap.Here term heavy doping can also substitute with the first doping level, and light dope can also substitute with the second doping level, and wherein the concentration range of the first doping level is greater than the concentration range of the second doping level.
Above-mentioned end on structure, also comprise multiple field plate be formed on oxide insulating layer, oxide insulating layer is above multiple termination group, and wherein each field plate is electrically connected to and is formed in corresponding heavily doped region, each termination group top (this heavily doped region may also be referred to as top doped region).
Above-mentioned end on structure, also comprises a marginal texture, and wherein marginal texture comprises the heavily-doped semiconductor substrate of the second conduction type, carries the light dope epitaxial loayer of the first conduction type; The heavy doping marginal zone of one or more first conduction type, is formed in the light dope epitaxial loayer top of the first conduction type; And one or more edges field plate, be formed on the second oxide insulating layer above light dope epitaxial loayer, wherein one or more edge field plates are electrically connected to the heavy doping marginal zone of one or more first conduction type respectively.
Above-mentioned end on structure, wherein the first conduction type is P-type, and the second conduction type is N-type, and bosom conduction type is P-type.
Above-mentioned end on structure, two outmost epitaxial loayers wherein along each trenched side-wall are first conduction types.
Above-mentioned end on structure, the doping content of multiple epitaxial loayers of alternating conductivity type is greater than the doping content of the light dope epitaxial loayer of the first conduction type.
Above-mentioned end on structure, also comprises the epi region of first conduction type, is arranged between termination group and active device region, is arranged on the width of width much larger than each termination group of the epitaxial layer region between termination group and active device region.
Above-mentioned end on structure, also comprises a field plate be arranged on above epitaxial layer region, is arranged between termination group and active device region.Optionally, on the insulating barrier above the epitaxial layer region of this field plate between termination group and active device region.
Above-mentioned end on structure, wherein termination group extends to the edge of semiconductor wafer.
In one alternate embodiment, provide a kind of semiconductor power device, comprise multiple active device, multiple active device comprises: the light dope epitaxial loayer of first conduction type, at the heavily-doped semiconductor types of flexure of the second conduction type; Multiple active groove be formed in light dope epitaxial loayer; The first epitaxial loayer that wherein each active groove is multiply provided in the alternating conductivity type of opposite side covers, and the first epitaxial loayer on opposite side is relative to the first center slot packed layer almost symmetry between the first innermost epitaxial loayer being arranged on two the first bosom conduction types.Can be regarded as, the first epitaxial loayer of the first epitaxial loayer of first group of alternating conductivity type that an opposite side of groove adheres to and second group of alternating conductivity type that another opposite side of the relative of groove adheres to is that symmetric points are mutually symmetrical with packed layer.
Semiconductor power device also comprises the end on structure that surrounds multiple active device, this end on structure comprises: multiple termination group be formed in the light dope epitaxial loayer of the first conduction type, at the heavily-doped semiconductor types of flexure of the second conduction type, each termination group comprises a termination groove be formed in the light dope epitaxial loayer of the first conduction type, and wherein the sidewall of termination groove is all multiply provided in the second epitaxial loayer covering of the alternating conductivity type of opposite side, and and the second center slot packed layer almost symmetry between the second innermost epitaxial loayer being arranged on two the second bosom conduction types.Can be regarded as, the second epitaxial loayer of second group of alternating conductivity type that another limit of the second epitaxial loayer of first group of alternating conductivity type that a limit of groove or sidewall adhere to and the relative of groove or sidewall adhere to is that symmetric points are mutually symmetrical with packed layer.
Above-mentioned semiconductor power device, also comprises: multiple field plate be formed on oxide insulating layer, and oxide insulating layer is above multiple termination group, and wherein each field plate is electrically connected to the first corresponding heavily doped region of conduction type being formed in each termination group top.
Above-mentioned semiconductor power device, also comprises: wherein end on structure also comprises a marginal texture, and wherein marginal texture comprises the heavily-doped semiconductor substrate of the second conduction type, carries the light dope epitaxial loayer of the first conduction type; The heavy doping marginal zone of one or more first conduction type, is formed in the light dope epitaxial loayer top of the first conduction type; And one or more edges field plate, be formed on the second oxide insulating layer above light dope epitaxial loayer, wherein one or more edge field plates are electrically connected to the heavy doping marginal zone of one or more first conduction type all respectively.
Above-mentioned semiconductor power device, wherein the first conduction type is P-type, and the second conduction type is N-type.
Above-mentioned semiconductor power device, two outmost epitaxial loayers along each trenched side-wall are the first conduction type.
Above-mentioned semiconductor power device, the doping content of the second epitaxial loayer of multiple alternating conductivity type is greater than the doping content of the light dope epitaxial loayer of the first conduction type.
Above-mentioned semiconductor power device, multiple active device and multiple termination group are made in same step simultaneously.
Above-mentioned semiconductor power device, comprises the epitaxial layer region of first conduction type, between the termination group being arranged on active device, is arranged on the width of peak width much larger than each termination group of the epitaxial loayer between termination group and active device region.
Above-mentioned semiconductor power device, wherein the first conduction type is P-type, and the second conduction type is N-type.
Above-mentioned semiconductor power device, wherein also comprises a field plate be arranged on above epitaxial layer region, is arranged between termination group and active device.
In one embodiment, provide a kind of preparation method of end on structure of the semiconductor power device be positioned on semiconductor wafer, comprise the following steps: the light dope epitaxial loayer of preparation first conduction type, at the heavily-doped semiconductor types of flexure of the second conduction type; Along the edge of the semiconductor wafer in the light dope epitaxial loayer of the first conduction type, prepare multiple deep trench (or directly preparing multiple groove); Deep trench (or filling groove) is filled with the epitaxial loayer of multiple alternating conductivity type, to prepare multiple termination group, wherein the sidewall of each deep trench (or groove) covers with the epitaxial loayer of the alternating conductivity type be deposited on opposite side, and epitaxial loayer on the opposite side center slot packed layer almost symmetry relative to two of bosom conduction type between the epitaxial loayer of the inside.
Above-mentioned method, also comprise: at the core of semiconductor wafer, prepare multiple active device region, the peak width of the first conductive type epitaxial layer wherein between multiple deep trench (or groove) and active device region is much larger than the width of deep trench (or being greater than groove).
Above-mentioned method, wherein deep trench (or this groove) is through epitaxial loayer, extends to the top of semiconductor substrate layer.
Read the following explanation of preferred embodiment and with reference to various accompanying drawing, these characteristics and advantages of the present invention for a person skilled in the art, undoubtedly will be apparent.
Accompanying drawing explanation
Figure 1A-1D is the profile of traditional vertical power device structure.
Fig. 2 is in an alternate embodiment of the present invention where, with the profile of the high voltage power device of the super-junction structures of nanotube in groove.
Fig. 2-1 is the device profile map with multiple unit cell 101 of Fig. 2, repeats to represent in whole semiconductor wafer.
Fig. 2-2 is perspective views of the unit cell 101 shown in the Fig. 2 not with P-injection top layer 130.
Fig. 2 A is the perspective view being similar to unit cell 101 not injecting top layer 130, band N-type column 110 ' with P-.
Fig. 2 A-1 is the profile of device shown in Fig. 2 A, for representing conduction type and doping content.
Fig. 2 A-2 is the profile of the embodiment of the present invention of filling with center nanotube instead of Insulating gap.
Fig. 2 B is the device perspective view being similar to Fig. 2 A, is electrically connected to all N-type columns with N+ type superficial layer.
Fig. 2 C is the vertical plane MOSFET perspective view with planar polysilicon grid, and planar polysilicon grid is lined with grid oxic horizon, is that 90 ° of directions extend along P and N-type column.
Fig. 2 D is except N-type superficial layer is electrically connected to all N-type column 115-N, other another all similar with Fig. 2 C exemplary embodiments.
Fig. 2 E also comprises another exemplary embodiments that is deposited on the schottky metal on end face, for connecting all N-column 115-N, forms Schottky diode.
Fig. 2 E-1 is except removing schottky metal is to show except rectangular structure, other all identical with Fig. 2 E embodiments.
Fig. 2 E-2 is that other are all identical with Fig. 2 E-1 except the drift layer 120 in Fig. 2 E-2 is made up of oxide instead of low concentration doping (intrinsic) silicon.
Fig. 2 F is an alternative embodiment of the invention, and wherein device has P+ type substrate 105 ', has N-type bottom buffer layer 105-B ' and column resilient coating 105-C ', to form IGBT device at P column 115-P and N column 115-N and N-type column 110 ' below.
Fig. 2 F-1 is the IGBT device similar with Fig. 2 F, but wherein with trench-gate.
Fig. 2 G is one and is similar to and appears at junction field effect transistor (JFET) such in the plane 111 of Fig. 2 A, and wherein device also comprises P-type grid electrode district, N+ source contact area and N-district to form JFET device.
Fig. 2 H is bipolar junction transistor (BJT), and wherein device also comprises a N+ emitter region and a P-type base region, and form BJT device, substrate is as collector electrode.
Fig. 2 I is another exemplary embodiments, and wherein device also comprises one and is lined with grid oxic horizon with the groove MOSFET of trench polysilicon silicon gate, is that 90 ° of directions extend along P and N-type column.
Fig. 2 J is another exemplary embodiments being similar to Fig. 2 I, and wherein gate pad is formed in above field oxide.
Fig. 3 A-3J is profile and the vertical view for the treatment of process of the present invention, for the preparation of the high voltage power device shown in the Fig. 2 with super-junction structures.
Fig. 4 is a kind of alternate configurations perspective view of the alternately unit cell 301 of N and P nanotube with charge balance, N and P nanotube is surrounded by the N-column that center has Insulating gap packed layer, is positioned on N++ substrate.
Fig. 4 A is the perspective view of a part of active area 390 of the semiconductor power device 300 utilizing the unit cell 301 of nanotube shown in Fig. 4 structure.
Fig. 4 A-1 is the vertical view of semiconductor device 300 layout of the present invention.
Fig. 4 B is as shown in Figure 4, with the termination area closed sectional figure of the semiconductor power device 300 of vertical nanotube.
Fig. 5 is the profile of the whole termination area 399 of semiconductor power device of being furnished with the nano tube structure shown in Fig. 4-4B.
Fig. 6 be in final end on structure with optional field plate designs, be similar to the profile of termination area shown in Fig. 5.
Fig. 6 A is a kind of optional termination area 399 " profile of structure.
Fig. 6 B is a kind of optional termination area 399 " ' profile of structure.
Fig. 6 C is a kind of optional termination area 399 " " profile of structure.
Fig. 7 A-7E is the profile of the optional preparation technology for the preparation of semiconductor power device of the present invention.
Fig. 8 A-8G is in analysis fill process, for solving the profile of the treatment process forming this difficult problem of cavity.
Fig. 9 A is the vertical view of closed cell configuration, includes the multiple nanotube unit cells in source region, is arranged on Semiconductor substrate mid portion.
Fig. 9 B-1 is the vertical view of the first end T-Ring of the termination area of semiconductor device.
Fig. 9 B is optional, the staggered rectangular plan view of unit cell.
Fig. 9 C is optional, the hexagon vertical view of unit cell.
Embodiment
See Fig. 2, illustrate vertical nanotube high pressure (Verticalnano-tubeHighvoltage, be called for short HV) profile of unit cell (UnitCell) 101 of diode component 100, for explaining the new ideas comprising new structure of the present invention and preparation characteristic.HV diode component 100 is positioned in heavily doped N-type base substrate 105 (such as N+ red phosphorus substrate), base substrate 105 is positioned at below N+ nanotube assembly section 105-B, this assembly section 105-B can be diffusion base area 105-B, and N+ cylinder diffusion region 105-C also can be formed by diffusion technology, hereafter will introduce in detail.HV device also comprises multiple N-type nanotube and P-type nanotube, as N-type thin epitaxial layer 115-N and P-type thin epitaxial layer 115-P.These nanotubes, as the N-epitaxial loayer 115-N replaced and P-epitaxial loayer 115-P, between two P-type columns 110, as vertical nanotube, inject top layer 130 from P-and extend to bottom N+ district 105-B.HV nanotube diodes device 100 also comprises a gap filling thing 120---one extremely the silicon of light dope concentration or oxide (or other dielectrics) district---, and it is positioned at the center of each unit cell 101 substantially, i.e. nanotube center.Nanotube is formed in Semiconductor substrate top.Semiconductor substrate also comprises a light dope epitaxial loayer, is made up of column 110.Also can select, column 110 is made up of lightly doped single crystalline substrate, is not with initial epitaxial layer, hereafter will introduce in detail.
Do not form in the embodiment of any specific restriction a typical exemplarily property, each N-type nanotube can have the width of 0.25 micron, and its region dopant concentration is about 2E12/cm
2(for 8E16/cm
3every volumetric concentration), most P-type nanotube width is about 0.5 micron, and its region dopant concentration is about 2E12/cm
2.But the region dopant concentration near the P-type nanotube of gap filling thing 120 is about 1E12/cm
2.Width near the P-type nanotube of P-type column 110 is about 0.5 micron, and region dopant concentration is about 8.5E11/cm
2.The width of P-type column 110 is around approximately 1.5 microns, and its region dopant concentration is about 1.5E11/cm
2(every volumetric concentration is at 2E14/cm
3to 1E15/cm
3between).In this case, P-type column 110 and the total regional concentration near the P-type nanotube of P-type column 110 are about 1E12/cm
2.The region dopant concentration of each P-type nanotube and N-type nanotube can be 2E12/cm
2, can regard two adjacent parts as and form, the region dopant concentration of every half is 1E12/cm
2, the Nanotube composite adjacent with two of identical charges with complementary opposite charges is become the nanotube of charge balance.Utilize above-mentioned typical doping content, the nanotube of films of opposite conductivity is mutual charge balance, and with P-type column 110 charge balance, realize super junction effect.The unit cell 101 that in Fig. 2, only expression one is independent.Fig. 2-1 represents the profile of the HV diode component 100 that multiple unit cell 101 repeats on whole semiconductor wafer.Therefore, utilize the unit cell 101 that these two are close to each other, adjacent P-type column 110 combines, and overall width is about 3 microns, in conjunction with after the region dopant concentration of each half column structure on 1.5 microns remain 1.5E11/cm
2, therefore every volume doping content of P-type column is about 1E15/cm
3.Exemplarily, the width of column is about the half of 1/4 groove width.The perspective view of Fig. 2-2 representation unit structure cell 101, is not with P-to inject top layer 130.The perspective view of Fig. 2 A representation unit structure cell 101, is not with P-to inject top layer 130, with N-type column 110 '.
High pressure (HV) nanotube diodes device 100 as shown in Figure 2 can be made by multiple nanotube N-passage and P-passage, to reduce resistance, obtains very low drain-source resistance (Rds).Such as, the device widths with N-type nanotube is 0.25 micron, and overall area doping content is 1E12/cm
2, its resistance and channel width are 5 microns, region dopant concentration is 1E12/cm
2the Rds of device the same.The drain-source resistance of traditional super-junction device is about 25-30 milliohm-cm2, and the above-mentioned device being furnished with 10 nanotubes, for 600VBV, estimates that Rds is 2-4 milliohm-cm2.
This structure of vertical junction as shown in Figure 2 may be used for preparing many dissimilar devices, such as mosfet transistor, bipolar junction transistor (BJT), diode, junction field effect transistor (JFET) and igbt (IGBT) etc.Nanotube can be made up of thin epitaxial layer, exemplarily but be not restricted to the P-layer being about 0.5 micron as comprised thickness, with 0.6-0.8E12cm-2 doping, being formed in thickness is near the N-layer of 0.25 to 0.5 micron, the arsenic of N-layer then within the scope of the most handy 1.6-2E12cm-2 or Sb doped.Then the P-type column within the scope of 0.5 to 1 microns wide is formed, with 1.6E12 to 2E12/cm
2scope doping.These thin N-type and P-type column are respectively formed in groove, until these layers merge with the core of groove.Then, the gap filling layer 120 of formation dielectric or the extremely silicon of light dope concentration, fills the gap merged between this nanotube column.As mentioned above, gap filling layer can grow oxide, the dielectric substance of deposition or intrinsic silicon.
Vertical super-junction structures as described in Fig. 2-1, utilizes following technique to make, and is made, and carry out the light dope within the scope of 0.1-0.2E12cm-2 by the P-type column/pillar construction of 2 to 5 microns wide on N++ substrate.Replace using P-type column/column, these columns can be N-type, N++ substrate use the N-extension of light dope (2E14-1E15cm-3) as original material.Fig. 2 A represents a kind of alternate configurations of nanotube, and N-type column 110 ' is formed between groove.Compared with Fig. 2, the conduction type of column and nanotube can exchange, but substrate 105 is still N-type, just as N-type diffusion bottom is the same with column district 105-B with 105-C.Doping content represents in Fig. 2 A-1, is still in charge balance.The conduction type of column and N-type, P-type nanotube, thickness, quantity and arrangement can reconfigure, as long as be still in charge balance.
Fig. 2 A-2 represents high pressure (HV) the nanotube diodes device 100 ' of an embodiment of the present invention, is similar to shown in Fig. 2 A-1, but the center nanotube 115 ' doping of the center of groove is filled, instead of Insulating gap filler.Such as, a sidewall in the pair of sidewalls of a groove adheres to the epitaxial loayer that first group of P and N-type are arranged alternately, another sidewall relative in this pair of sidewalls adheres to the epitaxial loayer that another second group of P and N-type are arranged alternately, be attached to so respectively and two sidewalls can reserve the gap that is positioned at groove center position substantially between first, second group P and epitaxial loayer of being arranged alternately of N-type, center nanotube 115 ' is filled among this gap.Can this center nanotube 115 of epitaxial growth N-type epitaxial material, to fill the residue gap around between nanotube completely.In this example, the thickness of center nanotube 115 ' is about 1 micron, and region dopant concentration is about 2E12/cm
2, obtain the charge balance with surrounding nanotube.Due to problems such as tolerance, charge balance and gap fillings, the present embodiment may implement difficulty slightly.
Whole device end face or various different structure can be formed on the surface, be 90 ° with P and N-type column, hereafter will introduce in detail; The cross section of these results is as shown in the plane 111 in Fig. 2 A, and this will illustrate in the examples below.In the exemplary embodiments of shown in Fig. 2 B, N+ type superficial layer 130 ' is electrically connected to all N-type columns.Top surface layer 130 ' can be injected by alloy or grow formation.In another exemplary embodiments, device also comprises a vertical plane MOSFET be made up of planar polysilicon grid 150, grid is lined with grid oxic horizon 155, along being 90 ° with P and N-type column, direction extends, and its meaning can be regarded as and extends along the direction with column place plane being perpendicular.The P-body zone 160 P+ body contact region 180 surrounded in N+ source area 170, P-body zone 160 is formed in the adjacent top surface between source area 170, as shown in Figure 2 C.N+ substrate 105 is used as the drain electrode of MOSFET.MOSFET structure shown in Fig. 2 C is superimposed upon in the plane 111 shown in Fig. 2 A.Fig. 2 D represents except N-type superficial layer 130 ' is electrically connected to all N-type column 115-N, other another all similar with Fig. 2 C exemplary embodiments.By n-type column 115-N and N-type superficial layer 130 ' short circuit, contribute to reducing Rds and diffusion resistance.Similar with Fig. 2 C, device shown in Fig. 2 D also comprises a vertical plane MOSFET, and along being 90 ° with P and N-type column, direction is formed, and all P column 115-P are electrically connected to P-body zone 160.N-type nanotube 115-N and N-type column 110 ' are connected to N-type superficial layer 130 ', and as super junction drift region.Fig. 2 E represents another exemplary embodiments, also comprises a schottky metal 131 and is deposited on the end face of nanotube and column, for connecting all N-column 115-N.The ohmic contact regions 181 comprising P+ doping can be selected, to provide ohmic contact between P column 115-P and schottky metal 131, the ohmic contact regions 181 being such as formed in nanotube and column top can extend along the direction with epitaxial loayer 115-P or 115-N place plane being perpendicular.Fig. 2 E-1 represents except removing schottky metal 131 is to show except rectangular structure, other all identical with shown in Fig. 2 E embodiments.Except the gap filling thing 120 in Fig. 2 E-2 is made up of tin-oxide, instead of outside light dope (or intrinsic) silicon material formation, other places of Fig. 2 E-2 are all identical with Fig. 2 E-1.Fig. 2 F represents another embodiment of the present invention, and wherein device also has P+ type substrate 105 ', with N-type resilient coating 105-B ' and 105-C ' below P column 115-P and N column 115-N and N-type column 110 ', to form IGBT device.IGBT device also comprises the gate oxide 195 below planar gate 191, N+ emitter/source area 192, P-body zone 193, P+ body joint 194 and grid.P+ substrate 105 ' is as collector electrode.Fig. 2 F-1 represents another kind of similar IGBT device, but is classified as groove-shaped device, is with gate trench 191 ', instead of planar gate.Fig. 2 G-2H represents other additional embodiment, and wherein along being 90 ° with P and N-type column 115-P and 115-N, direction is formed in plane 111 shown in Fig. 2 A various device architecture.Fig. 2 G represents one, and just as the junction field effect transistor (JFET) that plane 111 shown in Fig. 2 A will occur, wherein device also comprises P-type grid electrode district 151, N+ source contact area 152, N-district 153, forms JFET device.N+ substrate 105 is as drain electrode.Fig. 2 H represents bipolar junction transistor (BJT), and wherein device also comprises a N+ emitter region 161 and P-type base region 162, forms BJT device.N+ substrate 105 is as collector electrode.
Fig. 2 I represents another exemplary embodiments, wherein device also comprises a groove MOSFET be made up of trench polysilicon silicon gate 150 ', grid is lined with grid oxic horizon 155, along being 90 ° with P and N-type column, direction extends, and namely polysilicon gate 150 ' extends along the direction of P and the N column place plane being perpendicular with nanotube.The P-body zone 160 P+ body contact region 180 surrounded in N+ source area 170, P-body zone 160 is formed in the adjacent top surface between source area 170.N+ substrate 105 is as drain electrode.Fig. 2 J representation class is similar to another exemplary embodiments of Fig. 2 I, wherein gate pad 150 " to be initially formed in above field oxide 165.Similar with Fig. 2 I, device also comprises a groove MOSFET, and along being 90 ° with P and N-type column, direction is formed, and all P columns are all electrically connected to P-body zone 160.
See a series of sectional side views of Fig. 3 A to 3E, represent the preparation technology being furnished with the semiconductor power device of nanotube as shown in Figure 2.Fig. 3 A represents initial N+ red phosphorus silicon substrate 205, i.e. the silicon substrate of heavy N+ doping, and carrying P-type epitaxial loayer 210, P-type epitaxial loayer 210 and substrate 205 can be referred to as a substrate or wafer.The thickness of P-type epitaxial loayer 210 is such as about 40 microns, and P-doping content is about 1e15/cm
3.In Fig. 3 B-1 and 3B-2, carry out etching technics, in epitaxial loayer 210 and base substrate 205, open groove 212-1 and 212-2, they can extend downward runs through in epitaxial loayer arrival base substrate 205.Groove width is about 10 microns, and the column width of P-column 210-P reserved between adjacent trenches is about 3 microns (exemplarily, column width is not from 2 to 5 microns etc.).Because appreciable impact can not be caused to charge balance performance in the inclination angle of sidewall and column 210-P, therefore the sidewall of groove 212-1 and 212-2 has very little angle of inclination beta, such as 85-88 ° (if measured from Relative vertical axle, inclination angle is 2-5 °), instead of subvertical column, be such as about the column of 89-90 °.
In fig. 3 c, the alternating thin layers of growth N epitaxial loayer 215-N and P epitaxial loayer 215-P, covering groove sidewall and epitaxial loayer 210 are positioned at the top surface areas around groove 212-1 and 212-2.After having grown P-epitaxial loayer 215-P and the N-epitaxial loayer 215-N adjacent to P-epitaxial loayer 215-P, stay next crack near heart part in the trench.This very little center slot is filled with the gap filling thing 220 of heat growth or deposition insulation.In fig. 3d, at the end face of P-column 210-P and the end face of groove, chemico-mechanical polishing (CMP) technique is carried out.In fig. 3e, utilize high temperature from N+ substrate 205, spread heavily doped N-Doped ions, carry out N-diffusion technology, in this example, the bottom being coated with the groove of epitaxial loayer in inside approximately spreads 5 microns, and be diffused into the bottom of P column 210-P, then N-Doped ions diffuse into epitaxial loayer 215-P, 215-N be positioned at channel bottom region and enter bottom column 210-P with formed respectively N+ spread base area 205-B and N+ spread column district 205-C.The remainder of N and P epitaxial loayer 215-N, 215-P can be transformed into vertical nanotube by this diffusion process.If the concentration of electric charges of selecting properly these N and P epitaxial loayer 215-N, 215-P and column 210-P, as shown in Figure 2, so finally will obtain charge balance, these vertical nanotubes can be used for super junction application.The aspect ratio of diffusion technology as shown in FIGURE 3 E comparatively Fig. 2 more easily realizes.
P type alloy can also be utilized to inject, form P+ district, a top 130 on the top surface of a substrate, to form high pressure vertical diode, similar as shown in Figure 2.
From Fig. 3 F, represent a kind of optional method contributing to diffusion technology, use the first step identical with Fig. 3 A with 3B-1.But, as illustrated in Figure 3 F, after making multiple N and P epitaxial loayer 215-N and 215-P, epitaxial process stops, a gap or breach can be left in groove center, and inject 251 by carrying out vertical (anisotropy) N+, thus N+ district 250 is formed in exposed epitaxial loayer 215-N and 215-P, N+ injection ion 251 is doped with in such as, epitaxial loayer 215-N bottom gap and 215-P region, the top area of epitaxial loayer 215-N and 215-P is also doped with N+ and injects ion 251, as shown in Figure 3 G.Can also select first on the exposed surface of epitaxial loayer 215-N and 215-P outermost one deck, to grow oxide layer (not indicating in figure), so as in injection process protective side wall, again except oxide layer after injection.In Fig. 3 H, continued growth remaining N and P type epitaxial loayer 215-N and 215-P and as a rule reserved along centre gap growth filler 220 in the gap of groove.CMP process is utilized to remove unnecessary top material, as the top area of epitaxial loayer 215-N and 215-P, as shown in fig. 31.In the diffusion process shown in Fig. 3 J, N+ district 250 contributes to forming N+ and spreads base area 205-B and N+ diffusion column district 205-C.
The alternate configurations of Fig. 4 representation unit structure cell 301, unit cell 301 has alternately N and P nanotube 315-N and 315-P of charge balance, is surrounded, have dielectric gap filling layer 320, be positioned on N++ substrate 305 in center by N-column 310.Side on the substrate 305, also has a N+ to spread base area 305-B and N+ and spreads column district 305-C.The nano tube structure of this simplification is easy to preparation more than said structure.Exemplarily, the width of N and P nanotube 315-N and 315-P and N-column 310 and doping content display are in the diagram.For the embodiment shown in the embodiment shown in Fig. 4 and Fig. 2 to Fig. 3, nanotube and column are charge balances.Fig. 4 A represents the active area 390 of semiconductor power device 300, uses nanotube unit cell 301 structure shown in Fig. 4.In this example, power device 300 is groove MOSFET (similar with shown in Fig. 2 I).Groove MOSFET has trench polysilicon silicon gate 350, grid is lined with grid oxic horizon 355, along being 90 ° with P and N-type column 315-P and 315-N, direction extends for it, the P-body zone 360 P+ body contact region 380 surrounded in N+ source area 370, P-body zone 360 is formed in the adjacent top surface between source area 370.N+ substrate 305 is as drain electrode.
See Fig. 4 A-1 to Fig. 6, the structure concrete configuration of the termination area 399 of semiconductor power device 300 in the present embodiment, as MOSFET.Fig. 4 A-1 represents the vertical view of semiconductor device 300 layout.Active area 390 occupies the core of power device 300.A part of source metal 350-1 and gate metal 350-G, in active area 390, forms source pad and gate pad respectively.Other parts of power device 300 are passivated layer 302 and cover.Region on wafer beyond active area is termination area 399.Termination area 399 forms a ring at active region, near the edge of power device 300.Drain electrode, on base, does not therefore show from this schematical top view.
Fig. 4 B represents the closed sectional figure of the termination area 399 of the semiconductor power device 300 shown in Fig. 4 A-1, is furnished with the vertical nanowires tubular construction shown in above-mentioned Fig. 4 to 4A, to obtain the high-breakdown-voltage of semiconductor power device 300.Nanotube still can be in charge balance, to realize high-breakdown-voltage.In order to simplify, Fig. 4 B does not indicate passivation layer.Fig. 4 B represents the profile at termination area beginning.Semiconductor power device 300 is positioned on heavily doped N-type substrate, and heavily doped N-type substrate is expressed as red phosphorus substrate N++ layer 305.The bottom of nano tube structure also comprises the bottom of N+ diffusion layer 305-B and N-column 310, has N+ column diffusion layer 305-C, is made by the diffusion technology of above-mentioned N++ red phosphorus substrate 305.Semiconductor power device also comprises multiple N-type thin epitaxial layer 315-N and P-type thin epitaxial layer 315-P.The N-epitaxial loayer 315-N that what these nanotubes had replace, and the P-epitaxial loayer 315-P be formed between N-type column 310, as vertical nanotube, the end face of the substrate that they cover from oxide insulating barrier 330, extend downwardly into bottom N+ district 305-B and N+ substrate 305.Nano tube structure also comprises a center slot filler (lightly-doped silicon or dielectric substance) 320, is substantially formed in the center between N-type and P-type nanotube 315-N and 315-P.Semiconductor power device 300 also comprises P-body zone 340, is formed in the top of nano tube structure.Semiconductor power device 300 also comprises multiple polysilicon field plate 345, by metal layer at top 350, be electrically connected to P+ district 340, the innermost metal level 350-I in termination area is also electrically connected to the source area of semiconductor power device, and other metal levels 350 remaining then conduct float metal.P+ district 340 short circuit P-type nanotube 315-P.Innermost metal level 350-I is configured to work when zero volt usually, and as an exemplary embodiments, and each continuous print metal level 350 that floats is configured to bear the voltage of about 50 volts.Each nanotube termination group forms a ring 398 around active area 390 near active area 390.Fig. 4 B represents a part of beginning region of these two kinds of nanotube termination groups and the 3rd nanotube termination group.The basic structure (not comprising P+ district 340, oxide 330, polysilicon field plate 345 and floating metal 350) of each nanotube group is identical with the unit cell 301 in active area 390, and is formed simultaneously.
Fig. 5 represents the quantity by increasing nanotube super junction ring 398, regulate the doping content in N-district 306, the voltage of field plate 345 and 2 step-like step field plates (twostepfieldplate) 346, be furnished with the profile of the whole termination area 399 of the semiconductor power device 300 of nano tube structure shown in Fig. 4 to 4B.After last ring, form final end on structure 397, comprise formation 2 step field plate 346, this field plate can utilize polysilicon and metallic combination to reduce surface field; Also form field plate region 346, it is electrically connected to drawn area (will in this place's sawing), so that stopping exhausting after sawing touches Waffer edge.A N+ tunnel end points 370 ' is also had at Waffer edge.The puncture voltage up to 760 volts can be born in termination area 399, as shown in Figure 5 with ten rings and 2 final step field plate 346 marginal textures of nanotube super-junction structures.Shown passivation layer 380 covers most termination area 399.
Fig. 6 represents the profile with the termination area 399 ' of optional field plate designs in final end on structure 397 '; As shown in Figure 5, three steps are used to substitute two steps, for the preparation of field plate 346 ' (replacing 346), can without the need to a N-type doped region as N+ tunnel end points 370 '.These field plates 346 ' are that oxide layer, polysilicon, deposition oxide (silex glass (BPSG) containing boric acid or tetraethyl orthosilicate (TEOS)) and the metal layer combination grown by heat is formed, better than final end on structure 397 performance shown in Fig. 5, but need extra preparation technology.
Fig. 6 A represents a kind of optional end on structure 399 " profile.This structure utilizes wider groove (wider than active area groove) to make, and after epitaxial process, retains wide gap.Unit cell 301 ' is formed in the trench, and unit structure 301 (Fig. 4) similar with active area, can use identical technique to prepare simultaneously, but will retain a wider gap in centre.Have column between adjacent trenches, column and the nanotube be adjacent form silicon island ring 361, surrounded, and with dielectric substance 362 blind, have the floating P-district 363 of formation at silicon island top surface of ring by the gap of 2-5 micron.Floating P-district strides across N-shaped nanotube and column, bridge joint p-type nanotube.
These silicon island rings 361 are separated by dielectric substance 362, form floating capacitor 366 network, according to equivalent capacitance value, are distributed by the voltage in whole floating P-district 363.In other words, high pressure termination of the present invention can utilize the trench capacitor 366 by sidewall silicon electrode separates to configure.Exemplarily, can oxide and the silica-filled wide gap 362 with polysilicon compound (SIPOS) be used, to reduce the stress from thick Si02, thus avoid crack.After MOSFET/ active device treatment process, before metallization, can be filled by etching and extension or as the part of active area etching groove and extension fill process, prepare termination groove.
Another kind of optional end on structure comprises a lightly doped P type epitaxial region 197, between active device region and the nanotube group of end on structure, surround active device, to reduce electric field, increases puncture voltage.Fig. 6 B represents this structure 399 " ' an example.Also namely unit cell 101 is similar for each termination group 198 and the nanotube filling groove structure shown in Fig. 2, is not with top p-type implanted layer 130.End on structure 399 " ' comprise a ring containing multiple nanotube termination group 198, as mentioned above, each ring is made up of N-type and P-type nanotube 115-N and 115-P.Each nanotube group 198 also comprises a center slot and fills (lightly doped silicon or dielectric) 120, is formed in the center between N-type and P-type nanotube 115-N and 115-P.Nanotube termination group 198 forms a series of ring, surrounds the active area 390 of vertical nanotube high pressure (HV) MOSFET element, can be configured with source region 390 according to foregoing.The active area of vertical nanotube high pressure (HV) MOSFET element preferably has P-type column 110 between nanotube filling groove structure 101, similar with Fig. 2-1, nanotube termination group and active area nanotube filling groove structure can be formed in same preparation technology.In the example shown in Fig. 6 B, the outmost unit cell 301 ' of vertical nanotube high pressure (HV) MOSFET element represents on the right side (active area) of accompanying drawing.End on structure 399 " ' comprise the field plate 345 ' that is arranged on top, heavy doping P district 365 ', in outmost unit cell 301 ' top.
Termination group 198 can ignore floating P+ district, field plate and metal structure, as Fig. 4 B, 5, shown in 6 and 6A, N-type and P-type nanotube 115-N and 115-P can extend to the oxide insulating layer 330 of top.Termination group 198 can extend to Waffer edge.End on structure shown in this from Fig. 5 and Fig. 6 is different, the nanotube termination group 398 in Fig. 5 and Fig. 6 by being presented as the epitaxial loayer 306 of the end on structure 397 of bearing structure, away from Waffer edge.Doped with P type epitaxial region 197 surrounds active device region and between nanotube group end on structure and active device region, the doping content of P type epitaxial region 197 is between 1E14/cm3 to 2E14/cm3, and its width is much larger than the width of each nanotube termination group 198.Also can selecting, utilizing the epitaxial loayer identical with preparing column 110, preparation doped with P type epitaxial region 197, column 110 is between each nanotube termination group 198 and in active device region between nanotube filling groove structure 101.In a preferred embodiment, doped with P type epitaxial region 197 is about 5 to 10 times of each nanotube termination group 198 width.Doped with P type epitaxial region 197, from the end face of semiconductor, extends vertically up to the degree of depth the same with nanotube, and lightly doped N district 105C upwards spreads from bottom N+ substrate 105, is separated in doped with P type epitaxial region 197 and base substrate.In one embodiment, the doped with P type epitaxial region 197 of 60 microns wide only needs to combine with 2-3 group nanotube end on structure, just can provide gratifying termination effect for the device of 600V.
In the embodiment of shown in Fig. 6 C, end on structure 399 " " there is a lightly doped P type epitaxial region 197, in active area between outmost unit cell 301 ' and termination group 198, with the end on structure 399 shown in Fig. 6 B " ' similar.End on structure 399 " " also comprise the heavily doped region 365 ' of an identical conduction type (such as P+), be formed in the region 197 between outmost unit cell 301 ' and termination group 198, as guard ring.As shown in Figure 6 C, end on structure 399 " " the extra field plate 345 ' also comprised above a Ge P-district 197 is connected to the heavily doped region 365 ' of identical conduction type (such as P+), heavily doped region 365 ' is formed in the region 197 below the field plate between outmost unit cell 301 ' and termination group 198, punctures with the termination improving device.
Although termination area shown in Fig. 4 B-Fig. 6 399 and 399 ' uses nanotube unit cell 301 structure shown in Fig. 4, identical principle may be used for other charge balance nano tube structure, structure as shown in Figure 2 to Figure 3.
Fig. 7 A to 7D represents a series of profiles of the optional preparation technology of semiconductor power device of the present invention.The nanotube be made up of N-column 315-N and P-column 315-P is formed in an independent light dope N-type silicon substrate 305 ', is not with epitaxial loayer.Similar shown in this structure and Fig. 2 to Fig. 3, but not used for forming the initial epitaxial layer of column.The substitute is, nanotube is formed in lightly doped single crystalline substrate.In figure 7b, MOSFET structure cell is formed on end face, and body zone 343 surrounds the source area 341 around trench-gate 342.In Fig. 7 B-1, dielectric layer deposition 364 (BPSG or TEOS), protects end face in the subsequent processes such as backgrind.In fig. 7 c, the Bottom ground of substrate 305 '.In fig. 7d, in the bottom of substrate 305 ', inject, deposit or epitaxial growth N and N+ district 310-1 and 310-2.The bottom of N district 310-1 and nanotube, column combines, and forms nanotube assembly section.If each layer prepared bottom substrate does not have heavy doping demand, the mode of growth is so preferably used to be formed.In order to carry IGBT device as shown in Figure 2 F, region 310-1 and 310-2 can be made respectively N-buffering and P+ layer.After forming the back N++ layer (for IGBT device, being N-buffering and P+ layer) of MOSFET, the pattern of end face dielectric layer 364 as seen in figure 7e, can complete remaining top process (such as metal passivation).Also can select, if back technique is carried out at temperatures sufficiently low, top technique can be completed before the technique of back.
Fig. 8 A to 8C represents in gap filling process, solves a series of profiles of the preparation technology of a hole formation difficult problem.In fig. 8 a, groove 308 is formed in the N-epitaxial loayer 310 above N++ substrate 305, and sidewall presents very large tiltangleθ relative to vertical axis.Exemplarily, tiltangleθ can be 2-5 degree (if measuring, in 85-88 degree relative to the bottom surface of groove 308).In the fig. 8b, N-doped epitaxial layer 315-N and the P-doped epitaxial layer 315-P of multiple alternately appearance is grown, the sidewall of covering groove 308 and bottom surface.Groove pars intermedia branch is still with the gap 308 ' presenting a band angle.The top of epitaxial loayer can be removed by CMP in the later stage, repeats no more in order to easy.In Fig. 8 C, fill intermediate gap 308 ' with gap filling layer 820, gap filling layer 820 can be oxide or intrinsic silicon, or the dielectric substance of other types.Owing to forming the difficult problem in cavity when inclination angle structure solves between dopen Nano pipe gap filling, therefore gap filling can be carried out more easily.Fig. 8 D represents if sidewall is also vertical, the formation cavity problem that gap filling process may exist; When gap is very narrow, this problem can worsen.
Fig. 8 E-8G represents optional embodiment of the present invention, utilizes groove and the column of different in width, after epitaxial growth, improves gap-filled processes.In Fig. 8 E, groove has an angle to add (angleplusstep) technique, changes the width of groove.In this case, the tiltangleθ of groove is without the need to very large.Groove can be even vertical, utilizes the technique changing groove width, simplifies gap filling process.Utilize the pad shown in trench etch process composition graphs 8F-8G, groove width can be revised length by length.In Fig. 8 F, etched portions groove.In Fig. 8 G, sidewall forms pad, etching another part groove, forms a step in the trench.Exemplarily, can first the etching groove degree of depth 1/3, then within the scope of 0.1 to 1 micron thickness, form pad.Utilize pad, the remainder of etching groove, form a second order column (and groove).Increase a pad and etching technics, the column of three kinds of different in width can be formed.Pad can be made up of oxide, nitride or the combination of the two (or equivalent material).
Fig. 9 A represents the vertical view of closed cell configuration, and closed cell configuration containing multiple nanotube unit cell 401, is substantially disposed in the mid portion of Semiconductor substrate in active area 490.Each nanotube unit cell 401 comprises the concentric alternately ring of N and P type column 415-N and 415-P, and surrounded by N-type column 410, center has gap filling thing 420.Unit cell 301 shown in the cross-section structure of unit cell 401 and Fig. 4 is similar.Substrate is filled in multiple groove with multiple nanotube, and groove is opened in substrate/epitaxial loayer, as shown in Fig. 2 to 8.Although unit cell can have various shape and direction in the semiconductor wafer, the overall width " w " of the nanotube segment of each unit cell in same semiconductor wafer should keep equal.If doping content is very low, can not have a huge impact charge balance, therefore the width in column district 410 can be more flexible.Semiconductor power device also comprises a termination area 499 (not to scale (NTS)), and termination area 499 forms a ring at the outside place of Waffer edge 491 around active area 490, and has multiple nanotube column carrying high-voltage applications, as shown in Fig. 4 to 6C.Although this figure not in proportion, only gives the general concepts of various structure relative section.Do not indicate the concrete structure of termination area in Fig. 9 A yet, but with the termination area 399,399 ', 399 shown in Fig. 4-6C ", 399 " ', 399 " " similar.
Fig. 9 B-1 represents the vertical view of the first end T-Ring 498 of semiconductor device termination area 499.Basic structure and the unit cell 401 of termination ring are similar.Termination ring 498 can be regarded as and surrounds active area 490.Remaining termination ring 498 is outside the border of Fig. 9 B-1.Fig. 9 B represents the optional alternating expression rectangular shape of the one of unit cell 401 in active area.The optional hex shape of one of Fig. 9 C representation unit structure cell 401.
Although the present invention has been described in detail according to existing preferred embodiment, should this explanation be specified and be not used in limitation.Such as, although above-mentioned explanation refers to n-passage device, by the conduction type of conversion doped region, just the present invention can be used for p-passage device.Such as, substrate and nanotube assembly section can be P-types, instead of N-type.After reading above-mentioned explanation, various optional and amendment scheme of the present invention undoubtedly will be apparent for those skilled in the art.Therefore, true intention of the present invention and scope should be determined by appending claims and whole equivalent thereof.
Claims (22)
1. arrange an end on structure on the semiconductor wafer, it is characterized in that, described end on structure surrounds the active device region of semiconductor power device, comprising:
Multiple termination group be formed in the light dope epitaxial loayer of the first conduction type, at the heavily-doped semiconductor types of flexure of the second conduction type, wherein each termination group comprises a groove be formed in the light dope epitaxial loayer of the first conduction type, wherein trenched side-wall is covered by the epitaxial loayer of multiple alternating conductivity type, multiple epitaxial loayer is arranged on groove opposite side, and relative to the intermediate gap packed layer almost symmetry between the innermost epitaxial loayer being arranged on two bosom conduction types.
2. end on structure according to claim 1, it is characterized in that, also comprise multiple field plate be formed on oxide insulating layer, oxide insulating layer is above multiple termination group, and wherein each field plate is electrically connected to and is formed in corresponding heavily doped region, each termination group top.
3. end on structure according to claim 2, is characterized in that, also comprises a marginal texture, and wherein marginal texture comprises the heavily-doped semiconductor substrate of the second conduction type, carries the light dope epitaxial loayer of the first conduction type; The heavy doping marginal zone of one or more first conduction type, is formed in the light dope epitaxial loayer top of the first conduction type; And one or more edges field plate, be formed on the second oxide insulating layer above light dope epitaxial loayer, wherein one or more edge field plates are electrically connected to the heavy doping marginal zone of one or more first conduction type respectively.
4. end on structure according to claim 1, is characterized in that, wherein the first conduction type is P-type, and the second conduction type is N-type, and bosom conduction type is P-type.
5. end on structure according to claim 1, is characterized in that, two outmost epitaxial loayers wherein along each trenched side-wall are first conduction types.
6. end on structure according to claim 1, is characterized in that, the doping content of multiple epitaxial loayers of alternating conductivity type is greater than the doping content of the light dope epitaxial loayer of the first conduction type.
7. end on structure according to claim 1, it is characterized in that, also comprise the epi region of first conduction type, be arranged between termination group and active device region, be wherein arranged on the width of width much larger than each termination group of the epitaxial layer region between termination group and active device region.
8. end on structure according to claim 7, is characterized in that, also comprises a field plate be arranged on above epitaxial layer region, is arranged between termination group and active device region.
9. end on structure according to claim 1, is characterized in that, wherein termination group extends to the edge of semiconductor wafer.
10. a semiconductor power device, is characterized in that, comprising:
Multiple active device, comprising:
The light dope epitaxial loayer of first conduction type, at the heavily-doped semiconductor types of flexure of the second conduction type;
Multiple active groove be formed in light dope epitaxial loayer; The first epitaxial loayer that wherein each active groove is multiply provided in the alternating conductivity type of opposite side covers, and the first epitaxial loayer on opposite side is relative to the first center slot packed layer almost symmetry between the first innermost epitaxial loayer being arranged on two the first bosom conduction types;
An end on structure surrounding multiple active device, this end on structure comprises:
Multiple termination group be formed in the light dope epitaxial loayer of the first conduction type, at the heavily-doped semiconductor types of flexure of the second conduction type, wherein each termination group comprises a termination groove be formed in the light dope epitaxial loayer of the first conduction type, and the second epitaxial loayer that wherein sidewall of termination groove is all multiply provided in the alternating conductivity type of opposite side covers, and the second epitaxial loayer on opposite side is relative to the second center slot packed layer almost symmetry between the second innermost epitaxial loayer being arranged on two the second bosom conduction types.
11. devices according to claim 10, it is characterized in that, also comprise: multiple field plate be formed on oxide insulating layer, oxide insulating layer is above multiple termination group, and wherein each field plate is electrically connected to the first corresponding heavily doped region of conduction type being formed in each termination group top.
12. devices according to claim 11, is characterized in that, also comprise: wherein end on structure also comprises a marginal texture, and wherein marginal texture comprises the heavily-doped semiconductor substrate of the second conduction type, carry the light dope epitaxial loayer of the first conduction type; The heavy doping marginal zone of one or more first conduction type, is formed in the light dope epitaxial loayer top of the first conduction type; And one or more edges field plate, be formed on the second oxide insulating layer above light dope epitaxial loayer, wherein one or more edge field plates are electrically connected to the heavy doping marginal zone of one or more first conduction type all respectively.
13. devices according to claim 10, is characterized in that, wherein the first conduction type is P-type, and the second conduction type is N-type.
14. devices according to claim 10, is characterized in that, two outmost epitaxial loayers wherein along each trenched side-wall are the first conduction type.
15. devices according to claim 10, is characterized in that, the doping content of the second epitaxial loayer of multiple alternating conductivity type is greater than the doping content of the light dope epitaxial loayer of the first conduction type.
16. devices according to claim 10, is characterized in that, wherein multiple active device and multiple termination group are made in same step simultaneously.
17. devices according to claim 10, it is characterized in that, also comprise the epitaxial layer region of first conduction type, between the termination group being arranged on active device, be wherein arranged on the width of peak width much larger than each termination group of the epitaxial loayer between termination group and active device region.
18. devices according to claim 17, is characterized in that, wherein the first conduction type is P-type, and the second conduction type is N-type.
19. devices according to claim 18, is characterized in that, wherein also comprise a field plate be arranged on above epitaxial layer region, are arranged between termination group and active device.
20. 1 kinds of preparation methods being positioned at the end on structure of the semiconductor power device on semiconductor wafer, is characterized in that, comprise the following steps:
The light dope epitaxial loayer of preparation first conduction type, at the heavily-doped semiconductor types of flexure of the second conduction type;
Along the edge of the semiconductor wafer in the light dope epitaxial loayer of the first conduction type, prepare multiple deep trench;
Deep trench is filled with the epitaxial loayer of multiple alternating conductivity type, to prepare multiple termination group, wherein the sidewall of each deep trench covers with the epitaxial loayer of the alternating conductivity type be deposited on opposite side, and epitaxial loayer on the opposite side center slot packed layer almost symmetry relative to two of bosom conduction type between the epitaxial loayer of the inside.
21. methods according to claim 20, it is characterized in that, also comprise: at the core of semiconductor wafer, prepare multiple active device region, the peak width of the first conductive type epitaxial layer wherein between multiple deep trench and active device region is much larger than the width of deep trench.
22. methods according to claim 20, is characterized in that, wherein deep trench is through epitaxial loayer, extends to the top of semiconductor substrate layer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107045973A (en) * | 2017-03-16 | 2017-08-15 | 上海华虹宏力半导体制造有限公司 | The manufacture method of groove-shaped super junction |
| CN108933120A (en) * | 2017-05-23 | 2018-12-04 | 旺宏电子股份有限公司 | Semiconductor structure and its operating method |
| US10833151B2 (en) | 2017-06-07 | 2020-11-10 | Macronix International Co., Ltd. | Semiconductor structure and operation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050006699A1 (en) * | 2003-05-13 | 2005-01-13 | Kabushiki Kaisha Toshiba | Semiconductor device and its manufacturing method |
| CN101414553A (en) * | 2007-09-27 | 2009-04-22 | 三洋电机株式会社 | Semiconductor device and method of processing the same |
| CN102194880A (en) * | 2010-03-05 | 2011-09-21 | 万国半导体股份有限公司 | Device structure with channel-oxide-nanotube super junction and preparation method thereof |
| CN203690304U (en) * | 2013-12-20 | 2014-07-02 | 西安芯派电子科技有限公司 | Vertical super junction metal-oxide -semiconductor field effect transistor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7592668B2 (en) * | 2006-03-30 | 2009-09-22 | Fairchild Semiconductor Corporation | Charge balance techniques for power devices |
| EP2208229A4 (en) * | 2007-09-21 | 2011-03-16 | Fairchild Semiconductor | Superjunction structures for power devices and methods of manufacture |
| US8546875B1 (en) * | 2012-03-14 | 2013-10-01 | Infineon Technologies Austria Ag | Vertical transistor having edge termination structure |
-
2015
- 2015-07-16 TW TW104123068A patent/TWI567974B/en active
- 2015-07-16 CN CN201510418871.XA patent/CN105304687B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050006699A1 (en) * | 2003-05-13 | 2005-01-13 | Kabushiki Kaisha Toshiba | Semiconductor device and its manufacturing method |
| CN101414553A (en) * | 2007-09-27 | 2009-04-22 | 三洋电机株式会社 | Semiconductor device and method of processing the same |
| CN102194880A (en) * | 2010-03-05 | 2011-09-21 | 万国半导体股份有限公司 | Device structure with channel-oxide-nanotube super junction and preparation method thereof |
| CN203690304U (en) * | 2013-12-20 | 2014-07-02 | 西安芯派电子科技有限公司 | Vertical super junction metal-oxide -semiconductor field effect transistor |
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| CN107045973A (en) * | 2017-03-16 | 2017-08-15 | 上海华虹宏力半导体制造有限公司 | The manufacture method of groove-shaped super junction |
| CN108933120A (en) * | 2017-05-23 | 2018-12-04 | 旺宏电子股份有限公司 | Semiconductor structure and its operating method |
| CN108933120B (en) * | 2017-05-23 | 2020-06-30 | 旺宏电子股份有限公司 | Semiconductor structure and operation method thereof |
| US10833151B2 (en) | 2017-06-07 | 2020-11-10 | Macronix International Co., Ltd. | Semiconductor structure and operation method thereof |
Also Published As
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| TWI567974B (en) | 2017-01-21 |
| CN105304687B (en) | 2019-01-11 |
| TW201605039A (en) | 2016-02-01 |
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