CN104617158B - A kind of Transient Voltage Suppressor structure with ultra-deep groove - Google Patents
A kind of Transient Voltage Suppressor structure with ultra-deep groove Download PDFInfo
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- CN104617158B CN104617158B CN201510034207.5A CN201510034207A CN104617158B CN 104617158 B CN104617158 B CN 104617158B CN 201510034207 A CN201510034207 A CN 201510034207A CN 104617158 B CN104617158 B CN 104617158B
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- 230000001052 transient effect Effects 0.000 title claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 239000007787 solid Substances 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 238000005530 etching Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 210000003739 neck Anatomy 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 description 1
- 102000013275 Somatomedins Human genes 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
Abstract
The invention discloses a kind of Transient Voltage Suppressor structures with ultra-deep groove, and it includes the heavily doped silicon substrates that one has the first conduction type；In the heavily doped silicon substrate surface, the one doped epitaxial layer with the first conduction type is set；A series of ultra-deep groove of solid matters is provided on the doped epitaxial layer, and the depth-width ratio of the ultra-deep groove is 10:1 to 60:1.The ultra-deep groove promotes to form a three-dimensional diffusing, doping region with the second conduction type by the filling of DOPOS doped polycrystalline silicon, and by high temperature, the PN junction with wafer doped silicon substrate one vertical structure of formation with the first conduction type.The junction area of the PN junction of the vertical structure is made of lateral area and floor space.And the junction area of the PN junction of vertical structure can be increased by the depth of etching groove, therefore this TVS diode structure with longitudinal P N knots can bear the surge power of bigger on smaller chip size（Multikilowatt）Or surge current.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of Transient Voltage Suppressor knot with ultra-deep groove
Structure.
Background technology
Transient Voltage Suppressor（Transient Voltage Suppressor, abbreviation TVS）It is that one kind is based on diode
The high-performance protection device of form, for system is protected to protect against the impact of various forms of high voltage transients and surge.Such as Fig. 1
Shown, TVS 1 is in parallel with by protection circuit 2 in the circuit board.In normal working conditions, TVS1 is on by protection circuit 2
Existing high impedance status.Under ESD or the surge impact of other forms, TVS1 can be opened with the speed of 10-12 picosecond magnitudes, by it
High impedance becomes Low ESR, absorbs up to thousands of watts of surge power, and the voltage clamp of two interpolars is had in a predetermined value
Protect the precision components in electronic circuit from the damage of ESD and various forms of surge pulses to effect.It is rung since it has
The advantages such as fast, transient power is greatly between seasonable, clamp voltage is low, leakage current is low are widely used to AC/DC power supply, meter at present
Each necks such as calculation machine system, tablet computer, smart mobile phone, household electrical appliance, communication equipment, security protection, automobile and industrial instruments
Domain.
However, existing TVS device is a planar diode structure mostly（As shown in Figure 2）, plane TVS can bear
The transient current for flowing through device it is directly proportional with its junction area.Therefore, in order to bearing the surge power of multikilowatt, plane
The size needs of TVS chips are made very big.Therefore this planar structure not only makes the reverse leakage current of device be difficult to be made very low,
Also the cost of increased chip simultaneously.Current electronic equipment is to the performance of TVS device（Such as surge capacity, leakage current）Have very
High requirement, size are also the smaller the better.And traditional plane TVS can not be by the high-power TVS chips of multikilowatt from traditional
DO-214AA（SMB）And DO-214AB（SMC）Encapsulation is transferred to smaller encapsulation such as DO-214AC（SMA）Or the envelope of other forms
Dress（SOD is encapsulated and DFN encapsulation）In.
Therefore, in the art, it is badly in need of a kind of surge power that bigger can be carried on smaller chip size（Kilowatt
Grade）Or the TVS device of dual-purpose power.
The content of the invention
The present invention provides a kind of Transient Voltage Suppressor structure with ultra-deep groove, and specifically, one kind has super
The rate Transient Voltage Suppressor of deep trench (Ultra-deep Trench, abbreviation UDT)（Transient Voltage
Suppressor, abbreviation TVS）Structure.
Present invention is disclosed a kind of Transient Voltage Suppressor structures with ultra-deep groove, and it includes have：
One has the first conduction type（P-type or N-type）Heavily doped silicon substrate；It is set in the heavily doped silicon substrate surface
One has the first conduction type（P-type or N-type）Doped epitaxial layer；A series of solid matters are provided on the doped epitaxial layer
Ultra-deep groove, and the depth-width ratio of the ultra-deep groove is 10:1 to 60:1.
Preferably, the doping concentration of the heavily doped silicon substrate is more than 1E18/cm3.
Preferably, the doping concentration of the doped epitaxial layer is 1E13/cm3 to 1E18/cm3, and thickness is 20-60 microns.
Preferably, the spacing of the ultra-deep groove is 1 to 5 microns.
Preferably, the opening of the ultra-deep groove is 1 to 5 microns.
Preferably, the depth of the ultra-deep groove is 10 microns to 60 microns.
Preferably, the second conduction type is filled in the ultra-deep groove（N-type or p-type）Auto-dope polysilicon.
Preferably, the resistivity of the auto-dope polysilicon is 0.002-0.020 Ohm.cm.
Preferably, patterned dielectric layer, metal layer and passivation layer are disposed on the upside of the ultra-deep groove.
The beneficial effects of the invention are as follows：The present invention proposes a kind of new Transient Voltage Suppressor knot with ultra-deep groove
Structure by the filling of ultra-deep groove etching and DOPOS doped polycrystalline silicon, and promotes by high temperature to form one and three-dimensional have second
The diffusing, doping region of conduction type forms one with the wafer doped silicon substrate with the first conduction type or doped epitaxial layer
The PN junction of vertical structure.The junction area of the PN junction of the vertical structure is made of lateral area and floor space.And the PN of vertical structure
The junction area of knot can be increased by the depth of etching groove, therefore this TVS diode structure with longitudinal P N knots can
To bear the surge power of bigger on smaller chip size（Multikilowatt）Or surge current, this is that plane PN junction can not
It realizes.This new high-power TVS diode can pass through IEC 61000-4-2（ESD）、61000-4-4（EFT）With
61000-4-5（Surge）Etc. multinomial International Electrotechnical Commission（IEC）Standard, can be widely applied to communication, security protection, industry,
In the protection of electric appliance electrical equipment.Another considerable advantage of the present invention is to reduce device size, in current electronics
Become more and more important under the trend of device miniaturization.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing, wherein：
Fig. 1 is the operating diagram of transient voltage suppresser diode；
Fig. 2 is existing Transient Voltage Suppressor structure diagram；
Fig. 3 is the device architecture schematic diagram that the present invention manufactures high-power Transient Voltage Suppressor using ultra-deep groove；
Fig. 4 is that the technological process for the manufacturing method that the present invention manufactures high-power Transient Voltage Suppressor using ultra-deep groove walks
Rapid one schematic diagram；
Fig. 5 is that the technological process for the manufacturing method that the present invention manufactures high-power Transient Voltage Suppressor using ultra-deep groove walks
Rapid two schematic diagram；
Fig. 6 is that the technological process for the manufacturing method that the present invention manufactures high-power Transient Voltage Suppressor using ultra-deep groove walks
Rapid three schematic diagram；
Fig. 7 is that the technological process for the manufacturing method that the present invention manufactures high-power Transient Voltage Suppressor using ultra-deep groove walks
Rapid four schematic diagram；
Fig. 8 is that the technological process for the manufacturing method that the present invention manufactures high-power Transient Voltage Suppressor using ultra-deep groove walks
Rapid five schematic diagram；
Fig. 9 is that the technological process for the manufacturing method that the present invention manufactures high-power Transient Voltage Suppressor using ultra-deep groove walks
Rapid six schematic diagram；
Figure 10 is the technological process for the manufacturing method that the present invention manufactures high-power Transient Voltage Suppressor using ultra-deep groove
The schematic diagram of step 7；
Figure 11 is the technological process for the manufacturing method that the present invention manufactures high-power Transient Voltage Suppressor using ultra-deep groove
The schematic diagram of step 8；
Figure 12 is the technological process for the manufacturing method that the present invention manufactures high-power Transient Voltage Suppressor using ultra-deep groove
The schematic diagram of step 9.
Specific embodiment
The technical solution in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example is only the part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
All other embodiment that technical staff is obtained without making creative work belongs to the model that the present invention protects
It encloses.
As shown in figure 3, its disclose be the present invention have ultra-deep groove Transient Voltage Suppressor structure device architecture
Schematic diagram.Wherein, label 10 is with the first conduction type（P-type or N-type）Heavily doped silicon substrate, label 11 are the first conductive-type
Type（P-type or N-type）Doped epitaxial layer, marked as 12 second conduction types（N-type or p-type）Auto-dope polysilicon（in-situ
Doped Poly), label 13 is the hard mask of silica（SiO2 Mask), label 14 is dielectric layer（ILD）, label 15 is gold
Belong to layer（Metal）, label 16 is passivation layer（Passivation）, label 17 is ultra-deep groove (Ultra-deep Trench, letter
Claim UDT), label 18 is PN junction.
As shown in figure 3, with the first conduction type（P-type or N-type）10 top surface of heavily doped silicon substrate set and one have
First conduction type（P-type or N-type）Doped epitaxial layer 11, the thickness of the doped epitaxial layer is 20-60 microns, in the doping
The ultra-deep groove 17 of solid matter is provided on epitaxial layer, and the depth-width ratio of the ultra-deep groove is 10:1 to 60:1, and described super
The second conduction type is filled in deep trench 17（N-type or p-type）Auto-dope polysilicon 12 and by the auto-dope polysilicon 12
One layer of auto-dope polysilicon membrane is formed in 17 upside of ultra-deep groove, wherein, the resistivity of the auto-dope polysilicon 12
For 0.002-0.020 Ohm.cm.
In addition, to realize breakdown reverse voltage adjustable variation between 5V to 200V of transient voltage suppresser diode,
And then realize to the equipment of 5V-200V operating at voltages and the protection of circuit, the doping concentration of the doped silicon substrate 15 can be set
It is set to 1E13/cm3 to 1E18/cm3.In addition, to realize different 18 areas of PN junction, the spacing of the ultra-deep groove 17 can basis
Need to be arranged to 1 to 5 microns, the opening of the ultra-deep groove 17 is 1 to 5 microns, depth is 10 microns to 60 microns.In addition,
The doping concentration of the heavily doped silicon substrate 10 may be configured as being more than 1E18/cm3, and the doping concentration of the doped epitaxial layer 11 is set
It is set to 1E13/cm3 to 1E18/cm3.
In addition, it is disposed with patterned dielectric layer 14, metal layer 15 and passivation in 17 upside of ultra-deep groove
Layer 16.
The present invention is that form a kind of new TVS PN junctions using ultra-deep groove and auto-dope polysilicon filling technique adjustable
Structure, and then realize small size, high-power, Low dark curient TVS diode device.
In addition, as shown in Fig. 4 to Figure 12, what is disclosed is the Transient Voltage Suppressor structure that the present invention has ultra-deep groove
Manufacturing method process flow diagram.
Its specific manufacturing process flow step is：
Step 1, with the first conduction type（P-type or N-type）10 grown on top a layer thickness of heavily doped silicon substrate be
20-60 microns have the first conduction type（P-type or N-type）Doped epitaxial layer 11；
Step 2,11 top surface of doped epitaxial layer deposit the hard mask 13 of layer of silicon dioxide, using as etching ultra-deep
The hard mask of groove 17；
Step 3 carries out photoetching to the hard mask of the silica 13, forms hard mask pattern；
Step 4, the doped silicon substrate 10 below the hard mask pattern carries out ion etching, to form ultra-deep groove
17；
Auto-dope growth is had the second conduction type by ultra-deep groove step 5（N-type or p-type）Polysilicon 12 fill
In the ultra-deep groove 17；
Step 6 is promoted by high temperature, will be in the DOPOS doped polycrystalline silicon 12 with the second conduction type and with first
Diffusion PN junction 18 is formed between the heavy doping substrate 10 of conduction type；
Step 7, somatomedin layer 14；
Step 8 grows metal layer 15 and etching；
Step 9, growth of passivation layer 16 and etching.
In addition, in the step 1, the doping concentration of the heavily doped silicon substrate 10 should be more than 1E18/cm3, described
The doping concentration of doped epitaxial layer 11 is 1E13/cm3 to 1E18/cm3.
In addition, in the step 3, the ultra-deep groove 17 etched is open between 1-5 microns, the ultra-deep groove
It it is 10-60 microns away from 17 depth of ultra-deep groove for 1 to 5 microns, etched, the depth-width ratio of ultra-deep groove 17 that etches is
10:1 to 60:1.
In addition, in the step 3, the resistance of the polysilicon 12 with the second conduction type of the auto-dope growth
Rate is 0.002-0.020 Ohm.cm.
In conclusion the present invention is picked by high temperature into so that the doped polycrystalline being filled in the ultra-deep groove 17 of solid matter
Silicon 12 is diffused in by doping and is laterally connected with each other, and forms the three-dimensional doped region with the second conduction type of a large volume
Domain.The solid doped region forms one with the silicon substrate 10 with the first conduction type in the side wall of ultra-deep groove and bottom and indulges
To the TVS diode PN junction 18 of stereochemical structure, junction area is made of two parts of floor space and lateral area.PN junction 18
Floor space determines chip size size, and lateral area is then directly proportional to the depth of groove.
Therefore, on the chip of same size, this totality with longitudinal stereoscopic structure PN junction 18TVS structures of the present invention
Junction area can be much larger than the TVS of traditional plane PN junction, and can in the case where not increasing chip size., by adjusting ditch
The depth of slot increases the junction area of TVS diode, therefore the TVS diode of the longitudinal stereoscopic structure has bis- poles of plane TVS
Manage inaccessiable high-power and Surge handling capability.In addition, the breakdown reverse voltage of TVS diode（Vbr）Height with the
The doping concentration of the silicon substrate of one conduction type is inversely proportional, therefore the doping concentration by adjusting silicon substrate（1E13/cm3 is arrived
1E18/cm3）, the breakdown reverse voltage of TVS diode（Vbr）It can change between 5V to 200V, so as to realize pair
The equipment of 5V-200V operating at voltages and the protection of circuit.
The foregoing is merely the embodiment of the present invention, are not intended to limit the scope of the invention, every to utilize this hair
The equivalent structure or equivalent flow shift that bright description is made directly or indirectly is used in other relevant technology necks
Domain is included within the scope of the present invention.
Claims (6)
1. a kind of Transient Voltage Suppressor structure with ultra-deep groove, which is characterized in that including：One has the first conduction type
（P types or N types）Heavily doped silicon substrate；The heavily doped silicon substrate surface sets one with the first conduction type（P types or N
Type）Doped epitaxial layer；A series of ultra-deep groove of solid matters is provided on the doped epitaxial layer, the heavily doped silicon substrate
Doping concentration is more than 1E18/cm3, and the doping concentration of the doped epitaxial layer is 1E13/cm3 to 1E18/cm3, the doping
The thickness of epitaxial layer is 20-60 microns, and the depth-width ratio of the ultra-deep groove is 10:1 to 60:1.
2. there is the Transient Voltage Suppressor structure of ultra-deep groove as described in claim 1, which is characterized in that the ultra-deep ditch
The spacing of slot is 1 to 5 microns.
3. there is the Transient Voltage Suppressor structure of ultra-deep groove as described in claim 1, which is characterized in that the ultra-deep ditch
The opening of slot is 1 to 5 microns, depth is 10 microns to 60 microns.
4. there is the Transient Voltage Suppressor structure of ultra-deep groove as claimed in claim 3, which is characterized in that the ultra-deep ditch
The second conduction type is filled in slot（N types or P types）Auto-dope polysilicon.
5. there is the Transient Voltage Suppressor structure of ultra-deep groove as claimed in claim 4, which is characterized in that the auto-dope
The resistivity of polysilicon is 0.002-0.020 Ohm cm.
6. there is the Transient Voltage Suppressor structure of ultra-deep groove as claimed in claim 5, which is characterized in that the ultra-deep ditch
Patterned dielectric layer, metal layer and passivation layer are disposed on the upside of slot.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109244069A (en) * | 2018-09-19 | 2019-01-18 | 深圳市心版图科技有限公司 | Transient voltage suppressor and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106803520A (en) * | 2016-08-27 | 2017-06-06 | 湖北文理学院 | A kind of many PN junction Transient Suppression Diodes and its application method for arrester |
| CN109360823B (en) * | 2018-10-08 | 2020-08-28 | 南京溧水高新创业投资管理有限公司 | Groove type transient voltage suppressor and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8377757B2 (en) * | 2010-04-30 | 2013-02-19 | Shanghai Sim-Bcd Semiconductor Manufacturing Limited | Device and method for transient voltage suppressor |
| CN103050545A (en) * | 2011-10-14 | 2013-04-17 | 上海韦尔半导体股份有限公司 | TVS (Transient Voltage Suppressor) diode and manufacturing method thereof |
| CN102592995B (en) * | 2012-02-27 | 2014-03-12 | 上海先进半导体制造股份有限公司 | Manufacture method of Zener diode |
| CN103295898A (en) * | 2013-05-10 | 2013-09-11 | 江苏应能微电子有限公司 | Method for manufacturing transient voltage suppressor by aid of ultra-deep trench structures |
| CN104091823A (en) * | 2014-07-24 | 2014-10-08 | 江苏捷捷微电子股份有限公司 | Transient-suppression diode chip and manufacturing method thereof |
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Cited By (1)
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| CN109244069A (en) * | 2018-09-19 | 2019-01-18 | 深圳市心版图科技有限公司 | Transient voltage suppressor and preparation method thereof |
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