CN103474346B - The implementation method of transient voltage suppression diode PN junction - Google Patents
The implementation method of transient voltage suppression diode PN junction Download PDFInfo
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- CN103474346B CN103474346B CN201210188975.2A CN201210188975A CN103474346B CN 103474346 B CN103474346 B CN 103474346B CN 201210188975 A CN201210188975 A CN 201210188975A CN 103474346 B CN103474346 B CN 103474346B
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- intrinsic polysilicon
- contact hole
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Abstract
The invention discloses a kind of implementation method of transient voltage suppression diode PN junction, P type substrate applies photoresist, gone out the groove of device by lithographic definition, protect the region outside groove with photoresist, carry out dry etching and obtain groove; Remove photoresist, fill intrinsic polysilicon in the trench; Adopt selective etch to remove unnecessary intrinsic polysilicon, after etching, the distance on intrinsic polysilicon distance groove top is 0.1 ~ 3 μm; N-type polycrystalline silicon is filled in the top of intrinsic polysilicon in the trench; Remove unnecessary N-type polycrystalline silicon by selective etch, and carry out chemico-mechanical polishing; N-type polycrystalline silicon forms metal silicide, in metal silicide, forms contact hole, realize contact hole and connect; Two end electrodes is drawn respectively with the backplate be positioned at below P type substrate by the metal wire be positioned at above contact hole.The present invention effectively can reduce the specific capacitance density of device.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly relate to a kind of implementation method of transient voltage suppression diode PN junction of low capacitance density.
Background technology
The glitch of voltage and electric current causes the main cause of electronic circuit and device damage, often brings the loss that cannot estimate.These interference come from the start-stop operation of power equipment, the instability of AC network, thunderbolt interference and static discharge etc. usually.The appearance of a kind of dynamical circuit brake TVS makes glitch obtain effective suppression.TVS(TransientVoltageSuppressor) or claim transient voltage suppressor be a kind of new product grown up on voltage-stabiliser tube Process ba-sis, TVS and Zener voltage-stabiliser tube can be used as voltage stabilizing, but Zener voltage-stabiliser tube breakdown current is less, the voltage stabilizing being greater than 10V only has 1mA, and TVS is more many greatly than Zener voltage-stabiliser tube breakdown current comparatively speaking.TVS circuit symbol is identical with common voltage stabilizing didoe, and profile is also as good as with general-purpose diode, and when the high energy impact events of moment is stood at TVS pipe two ends, it (can be up to 1 × 10 with high speed
-12second) its impedance is reduced suddenly, simultaneously stability big current, the voltage clamp between its two ends is numerically predetermined at one, thus guarantee that circuit element below damages from the high-octane impact of transient state.Be widely used in mobile phone at present, LCD module, and some more accurate handheld devices.The product particularly exporting Europe generally all will be arranged, as one of the Main Means of electrostatic defending.
TVS regulation applied in reverse condition under, when in circuit due to thunder and lightning, various electrical equipment interference occur significantly glitch voltage or pulse current time, it (can reach 1 × 10 within the extremely short time
-12second) proceed to rapidly reverse-conducting state, and by the voltage clamp of circuit on required security value (s), thus in effective protection electronic circuit precision components from damage.The transient pulse power that TVS can bear can reach kilowatt, and its clamping time is only 1ps.Clamping time is relevant to TVS electric capacity, and capacitance is tied cross section by TVS snowslide and determined, this records under specific 1MHz frequency.The size of electric capacity is directly proportional to the current carrying capability of TVS, and electric capacity too senior general makes signal attenuation.Therefore, electric capacity is the important parameter that data interface circuit selects TVS.
For the loop that data/signal frequency is higher, the interference of the capacitance on circuit of diode is larger, and formation noise or decaying signal strength are also large, therefore, need the capacitance range deciding selected device according to the characteristic in loop.The size of electric capacity can affect the response time of TVS device.Therefore, under the prerequisite ensureing device current ability to bear, reduce the total capacitance of device, can effectively shorten the device response time.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of implementation method of transient voltage suppression diode PN junction, effectively can reduce the specific capacitance density of device.
For solving the problems of the technologies described above, the implementation method of transient voltage suppression diode PN junction of the present invention, comprises the steps:
Step 1, P type substrate applies photoresist, is gone out the groove of device by lithographic definition, protects the region outside groove with photoresist, carries out dry etching and obtain groove;
Step 2, removes photoresist, fills intrinsic polysilicon in the trench;
Step 3, adopts selective etch to remove unnecessary intrinsic polysilicon, and after etching, the distance on described intrinsic polysilicon distance groove top is 0.1 ~ 3 μm;
Step 4, N-type polycrystalline silicon is filled in the top of described intrinsic polysilicon in the trench;
Step 5, removes unnecessary described N-type polycrystalline silicon by selective etch, and carries out chemico-mechanical polishing;
Step 6, described N-type polycrystalline silicon forms metal silicide, in this metal silicide, form contact hole, realizes contact hole and connects; Two end electrodes is drawn respectively with the backplate be positioned at below described P type substrate by the metal wire be positioned at above described contact hole.
The present invention does not adopt two-dimensional structure, the substitute is the method adopting trench fill, make regularly arranged groove-shaped diode array, by N-type polycrystalline silicon extraction electrode, and directly draw backplate at the back side of P type substrate, effectively reduce the specific capacitance density of device.
The present invention can be used in the manufacture craft of packet routing device.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is device depletion region distribution schematic diagram ();
Fig. 2 is device depletion region distribution schematic diagram (two);
Fig. 3 be etching groove after device sectional view;
Fig. 4 is the device sectional view after intrinsic polysilicon is filled;
Fig. 5 is the device sectional view after intrinsic polysilicon etching;
Fig. 6 is the device sectional view after heavily doped N-type polysilicon deposition;
Fig. 7 is the device sectional view after heavily doped N-type etching polysilicon;
Fig. 8 is the device sectional view after contact hole extraction electrode.
Embodiment
Step 1, see Fig. 3, P type substrate 101 is applied photoresist, is gone out the groove of device by lithographic definition, and the width of groove and the spacing range of groove are 0.5 ~ 3 μm.Protect the region outside groove with photoresist, carry out dry etching and obtain groove 102, the degree of depth of this groove 102 is 2 ~ 10 μm.The impurity concentration of described P type substrate 101 is low doping concentration, and the impurity concentration scope of doping is 1e
12cm
-2~ 5e
14cm
-2.
Step 2, see Fig. 4, removes photoresist by degumming process, fills intrinsic polysilicon 103 by epitaxial diposition in described groove 102.
Step 3, see Fig. 5, removes unnecessary intrinsic polysilicon by selective etch, and the intrinsic polysilicon thickness range finally obtained is relevant to the degree of depth of groove, and after etching, intrinsic polysilicon 103 is 0.1 ~ 3 μm apart from the distance on groove 102 top.
Step 4, see Fig. 6, fills heavy doping (1x10 in place by epitaxial diposition above intrinsic polysilicon 103 described in groove 102
18~ 1x10
21cm
-2) N-type polycrystalline silicon 104.
Step 5, see Fig. 7, removes unnecessary described N-type polycrystalline silicon 104 by selective etch, and carries out chemico-mechanical polishing.
Step 6, see Fig. 8, described N-type polycrystalline silicon 104 forms metal silicide; Adopt existing contact hole process to form contact hole 105 again, realize contact hole and connect N-type polycrystalline silicon 104; By being positioned at the metal wire 106 above contact hole 105, and the backplate 107 being positioned at (i.e. the back side of P type substrate 101) below described P type substrate 101 draws two end electrodes respectively; The device architecture of the transient voltage suppression diode PN junction of the low capacitance density of final formation.
The present invention abandons two-dimensional structure, and adopt the method for trench fill, etching groove 102 in P type substrate 101 upper end, fills certain thickness intrinsic polysilicon 103, and by N-type polycrystalline silicon 104 extraction electrode above intrinsic polysilicon 103.Backplate 107 is directly drawn at the back side of P type substrate 101.Found out by Fig. 1,2, when substrate concentration is identical, choose reasonable groove pitch and groove width are than the PN junction array obtained compared with conventional diode, and width of depletion region increases, and electric capacity reduces.Do not affect the gross area of device simultaneously, finally can obtain ultralow capacitance density.Wherein the groove pitch of Fig. 1 compares for 1:1 with groove width than the groove pitch for 3:1, Fig. 2 with groove width.The region that in Fig. 1,2, label 108 indicates is the depletion region under zero-bias, and in Fig. 2, groove mid portion is completely exhausted, thus greatly can reduce the capacitance of PN junction.
Above by embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. an implementation method for transient voltage suppression diode PN junction, is characterized in that, comprises the steps:
Step 1, P type substrate applies photoresist, is gone out the groove of device by lithographic definition, protects the region outside groove with photoresist, carries out dry etching and obtain groove;
Step 2, removes photoresist, fills intrinsic polysilicon in the trench;
Step 3, adopts selective etch to remove unnecessary intrinsic polysilicon, and after etching, the distance on described intrinsic polysilicon distance groove top is 0.1 ~ 3 μm;
Step 4, N-type polycrystalline silicon is filled in the top of described intrinsic polysilicon in the trench;
Step 5, removes unnecessary described N-type polycrystalline silicon by selective etch, and carries out chemico-mechanical polishing;
Step 6, described N-type polycrystalline silicon forms metal silicide, in this metal silicide, form contact hole, realizes contact hole and connects; Two end electrodes is drawn respectively with the backplate be positioned at below described P type substrate by the metal wire be positioned at above described contact hole.
2. the method for claim 1, is characterized in that: the impurity concentration of P type substrate described in step 1 is low doping concentration, and the impurity concentration scope of doping is 1e
12cm
-2~ 5e
14cm
-2.
3. method as claimed in claim 1 or 2, it is characterized in that: the width of groove described in step 1 and the spacing range of groove are 0.5 ~ 3 μm, the degree of depth of groove is 2 ~ 10 μm.
4. the method for claim 1, is characterized in that: N-type polycrystalline silicon described in step 4 is heavily doped N-type polycrystalline silicon in place.
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| CN201210188975.2A CN103474346B (en) | 2012-06-08 | 2012-06-08 | The implementation method of transient voltage suppression diode PN junction |
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|---|---|---|---|
| CN201210188975.2A CN103474346B (en) | 2012-06-08 | 2012-06-08 | The implementation method of transient voltage suppression diode PN junction |
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|---|---|
| CN103474346A CN103474346A (en) | 2013-12-25 |
| CN103474346B true CN103474346B (en) | 2016-04-13 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024624B (en) * | 2016-07-23 | 2019-03-05 | 中国振华集团永光电子有限公司（国营第八七三厂） | A kind of manufacturing method of highly reliable Flouride-resistani acid phesphatase transient voltage suppressor |
| CN106024625B (en) * | 2016-07-23 | 2019-03-05 | 中国振华集团永光电子有限公司（国营第八七三厂） | A kind of highly reliable Flouride-resistani acid phesphatase glassivation voltage adjustment diode manufacturing method |
| CN108565260B (en) * | 2018-04-08 | 2020-10-27 | 南京矽力微电子技术有限公司 | Semiconductor device with a plurality of transistors |
| CN108565259B (en) * | 2018-04-08 | 2022-03-01 | 南京矽力微电子技术有限公司 | Semiconductor device and method for manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853853A (en) * | 2009-03-31 | 2010-10-06 | 万国半导体有限公司 | The semiconductor controlled rectifier that has low electric capacity and forward drop and exhaust is as the Transient Voltage Suppressor of steering diode |
| CN103035669A (en) * | 2012-06-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Pn junction with ultra-low junction capacity density and manufacture method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7244970B2 (en) * | 2004-12-22 | 2007-07-17 | Tyco Electronics Corporation | Low capacitance two-terminal barrier controlled TVS diodes |
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2012
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853853A (en) * | 2009-03-31 | 2010-10-06 | 万国半导体有限公司 | The semiconductor controlled rectifier that has low electric capacity and forward drop and exhaust is as the Transient Voltage Suppressor of steering diode |
| CN103035669A (en) * | 2012-06-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Pn junction with ultra-low junction capacity density and manufacture method thereof |
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