CN109860309A - A kind of the structure design and production method of TVS - Google Patents
A kind of the structure design and production method of TVS Download PDFInfo
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- CN109860309A CN109860309A CN201910111924.1A CN201910111924A CN109860309A CN 109860309 A CN109860309 A CN 109860309A CN 201910111924 A CN201910111924 A CN 201910111924A CN 109860309 A CN109860309 A CN 109860309A
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Abstract
The invention discloses a kind of design of the structure of TVS and production methods; the structure includes: substrate P0; the doped region N1 of chip tow sides; the doped region N2 of chip tow sides; the groove of chip front and back sides; glass passivation layer inside groove; the metal layer of front and back sides; using the negative resistance charactertistic of TVS two-way under specified conditions, solve the problems, such as tradition TVS due to caused by positive resistance characteristic VC be significantly larger than VRWM, under the premise of guaranteeing device power; possess lower VC; bigger IPP ability is more timely protected to be provided more precisely by protection circuit.
Description
Technical field
The invention belongs to circuit brake technical fields, are specifically related to the structure design and production method of a kind of TVS.
Background technique
TVS diode, also known as Transient Suppression Diode are a kind of new and effective circuit brakes generally used,
It has the response time (subnanosecond grade) being exceedingly fast and quite high surge absoption ability.When its both ends are subjected to the high energy of moment
When stroke, the impedance value between both ends can be become Low ESR from high impedance with high speed by TVS, big to absorb a moment
Electric current, its both end voltage strangulation one it is scheduled numerically, to protect subsequent circuit element not by high voltage transient
The impact of spike.
Under the impact of high voltage transient spike, the voltage between the both ends TVS is risen by specified reversed shutdown voltage VRWM
To breakdown voltage VBR, and it is breakdown, and with the appearance of breakdown current, the electric current for flowing through TVS is up to peak pulse current IPP,
Voltage at its both ends is clamped to scheduled maximum clamp voltage VC hereinafter, thereafter, as pulse current declines by index simultaneously
Subtract, the voltage of two interpolar of TVS also constantly declines, and is finally restored to initial state.
According to application demand, TVS is divided into unidirectional and two-way, it is generally the case that only one PN junction of unidirectional TVS, it is two-way
There are two TVS by the PN junction of backrest, under normal circumstances, two-way TVS forward and reverse characteristics symmetric.
The main parameter of TVS has following:
1) voltage VRWM Reverse Standoff Voltage is reversely turned off
It defines TVS in the case where blocking working condition, for protection circuit system, no ceiling voltage for influencing electric leakage.
VRWM should be more than or equal to by the normal working voltage of protection circuit, but cannot be much larger, otherwise when circuit input voltage is big
When damaging voltage by the limit of protection circuit, TVS is still failure to actuate, and does not have protective effect.
2) breakdown voltage VBR
Device is in the region punctured, and at defined test current IT, the voltage for measuring device both ends is known as hitting
Voltage is worn, in this area, diode becomes low-impedance access, this is the mark voltage for indicating TVS pipe conducting.This parameter has
Minimum value and maximum value represent TVS operation voltage section.
3) peak pulse current IPP
In reverse operation, under defined impulsive condition, device allow by Maximum Peak Impulse Current, conventional arteries and veins
Punching is 10/1000 μ s exponential wave, may cause permanent damage more than this current value.
4) maximum clamp voltage VC
VC refers to the transient voltage maximum value at pipe both ends when specified IPP.VC cannot be greater than rear class by protection circuit
The transient state limit damage voltage.After transient pulse terminates, TVS diode automatically returns to high-impedance state, and entire circuit enters
Normal voltage.
5) peak pulse power PPP
The product of IPP and maximum clamp voltage VC, are exactly the maximum value of transient pulse power.Rated peak pulse power
PPP should be greater than the maximum electrical surge power that protected device or route are likely to occur.
By the VBR of TVS and the dispersion degree of standard value, VBR can be divided to is 5% and 10% two kind.5% VBR is come
It says, VRWM=0.85VBR；For 10% VBR, VRWM=0.81VBR.Currently popular mark method is the minimum value of VBR
It is generally bigger than VRWM by 10% or so, be in order to cope with and may reserve surplus there are certain floating by real work voltage in circuit,
The type selecting of normal working voltage is corresponded to convenient for VRWM.
The voltage of maximum clamp voltage VC 60% or so, TVS generally bigger than VRWM is higher, the absolute value of VRWM and VC difference
It is bigger.Such as the TVS of nominal 100V, VRWM is 100V, and maximum clamp voltage VC is 160V.
Under specific maximum clamp voltage, power consumption is bigger, and the ability to bear of electrical surge electric current is bigger；Specific
Under power consumption, clamp voltage VC is lower, and the ability to bear of electrical surge electric current is bigger.
Traditional production method one: mesa structure (attached drawing 1)
Design feature: the terminal of chip is groove, and passivation glass powder is covered in usual groove, and deposit metal electricity is done on table top
Pole.
One of production method of mainstream, technical maturity, product power and product voltage wide coverage, individual event TVS and double
It is all suitable for TVS.Attached drawing is the structure of individual event TVS.
Traditional production method two: planar structure (attached drawing 2)
Design feature: the terminal of chip is in surface, terminal oxide layer or other passivation films, such as SIPOS or PSG
Deng.One of production method of mainstream, but it is rare in high pressure or powerful product.If the passivation effect of terminal end surface is good
It is good, it leaks electricity smaller than mesa structure.Substrate material has non-epitaxial of epitaxial wafer, if can increase product using epitaxial wafer
Surge capacity, but also can greatly increase cost.Attached drawing is the structure of individual event TVS.
Traditional production method three: negative resistance structure (attached drawing 3)
Design feature: two-way TVS, silicon wafer thickness are thin.Device is at work, it may appear that negative resistance charactertistic.
Since the interference of negative resistance charactertistic meeting is by the normal work of protection circuit, seldom applied in real protection.
For common TVS, the either TVS of mesa structure or the TVS of planar structure, all it is much higher than in the presence of maximum VC
The case where VRWM, this needs have very big appearance wide between the normal working voltage of circuit to be protected and its energy power limit voltage.
For the TVS of negative resistance charactertistic, what it was made of in structure two back-to-back PN junctions, belong to two-way TVS, when
When surge pulse occurs, there is the TVS of negative resistance charactertistic although to have a very low clamp voltage VC, but this VC is possibly lower than being protected
The normal working voltage of protection circuit, so that can not work normally by protection circuit.
According to the difference of substrate material, TVS, due to the difference of electrons and holes mobility, is led there are also point of p-type and N-type
The material of p-type is caused to be easier the curve for negative resistance charactertistic occur than the material of N-type.The method for preventing negative resistance from occurring serves as a contrast first is that increasing
The thickness of egative film, this can sacrifice the surge processing capacity of TVS；Prevent negative resistance another method be increase substrate doping it is dense
Degree, this can serious restricted T VS voltage rating.
Summary of the invention
The present invention provides the structure design and production method of a kind of TVS, special using the negative resistance of TVS two-way under specified conditions
Property, solve the problems, such as tradition TVS due to caused by positive resistance characteristic VC be significantly larger than VRWM, in the premise for guaranteeing device power
Under, possess lower VC, bigger IPP ability is more timely protected to be provided more precisely by protection circuit.
The present invention provides the structure design and production method of a kind of TVS device, and traditional TVS is combined in the same device
The negative resistance charactertistic of positive resistance characteristic and two-way TVS device during device breakdown, make the breakdown curve of device finally present it is micro- just
Resistance or micro- negative resistance charactertistic.Correlated current voltage curve comparison such as attached drawing 7:A is the TVS of positive resistance characteristic, and B is the TVS of negative resistance charactertistic,
C is TVS provided by the present invention.
The technical solution of invention:
The present invention provides the structure design and production method of a kind of TVS device, which includes: substrate P0, chip are positive and negative
The doped region N1 on two sides, the doped region N2 of chip tow sides, the groove of chip front and back sides, the glass passivation layer inside groove,
The metal layer of front and back sides.
A kind of the structure design and production method of semiconductor TVS, are characterized in that:
There are diffusing, doping area N1 and N2 in the tow sides of substrate P0；The junction depth ratio N2 of the total doping concentration ratio N2 high, N1 of N1
It is deep.
Diffusing, doping area N1 and N2 is connected with each other, N1 and N2 are same type of impurity by impurity diffusion.
Diffusing, doping area N1 and N2 and substrate P0 form a big PN junction, and the junction of this big PN junction is along doped region N1
With the periodically concave-convex variation of N2.
When PN junction reverse bias, puncture first at the PN junction junction of diffusing, doping area N2 and substrate P0, punctures curve
With positive resistance characteristic；It is secondary at the PN junction junction of diffusing, doping area N1 and substrate P0 to puncture afterwards, start to generate conductance in PN junction
Mudulation effect.
The terminal of TVS is passivated layer protection.
A kind of the structure design and production method of TVS, are characterized in that: concentration 1e13~1e19atom/cm3 of substrate P0,
The thickness of substrate P0 is in 100um~500um；Peak concentration 1e15~1e21atom/cm3 of front doped region N1, front doping
The junction depth 10-200um of area N1；Peak concentration 1e15~1e21atom/cm3 of front doped region N2, the knot of front doped region N2
Deep 10-200um；
A kind of the structure design and production method of TVS, are characterized in that comprising following procedure of processing:
N1 doping is done in substrate P0, is then promoted；
N2 doping is done in substrate P0, is then promoted；
The PN junction termination environment for needing to keep is outputed in chip surface；
The passivation of PN junction end area end；
It metallizes in chip front and back sides.
A kind of the structure design and production method of TVS, are characterized in that, the dopant of the above doped region are transformed into conductive-type
The opposite dopant of type, device are still the present invention.
Compared with prior art, the present invention using two-way TVS under specified conditions negative resistance charactertistic, solve tradition TVS due to
VC is significantly larger than the problem of VRWM caused by positive resistance characteristic, under the premise of guaranteeing device power, possesses lower VC, more
Big IPP ability is more timely protected to be provided more precisely by protection circuit.
Detailed description of the invention
Fig. 1 is table top TVS structure of the present invention；
Fig. 2 is plane TVS structure of the present invention；
Fig. 3 is negative resistance TVS structure of the present invention；
Fig. 4 is implementation method one of the present invention；
Fig. 5 is implementation method two of the present invention；
Fig. 6 is other implementation methods of the invention；
Fig. 7 is TVS device current-voltage curve of the present invention.
Specific embodiment
Embodiment 1
Implementation method one (attached drawing 4)
Select the silicon substrate film of boron-doping, twin polishing, thickness 255um, resistivity 0.5ohm.cm.
After chemical cleaning, silicon wafer feeding oxidation furnace is aoxidized, 1100 DEG C of main technological temperature, main process time 130min,
Oxidated layer thickness
Using photoetching process and etching process, the oxidation layer window adulterated required for being outputed in the tow sides of silicon wafer, i.e.,
The doping window in the area N1；
1) after chemical cleaning, silicon wafer is sent into prediffusion boiler tube and does impurity prediffusion, doped source POLC3, main process warm
1185 DEG C of degree, main process time 50min；
2) after chemical cleaning, silicon wafer is sent into diffusion furnace tube to do and is spread, 1250 DEG C of main technological temperature, the main process time
700min；
3) chemical corrosion liquid containing hydrofluoric acid, the full oxide layer for shelling silicon chip surface are used；
4) after chemical cleaning, silicon wafer is sent into prediffusion boiler tube and does impurity prediffusion, doped source POLC3, main process warm
900 DEG C of degree, main process time 50min；
5) after chemical cleaning, silicon wafer is sent into diffusion furnace tube to do and is spread, 1250 DEG C of the main technological temperature of first segment, main technique
Time 200min, 950 degree of the main technological temperature of second segment, main process time 90min；Oxidated layer thicknessFinal N1
The diffusion junction depth 5-15um in the area diffusion junction depth 35-40um, N2 in area；
6) by photoetching process and etching process, PN junction terminal trenches are outputed in the front and back sides of silicon wafer；
7) glass blade coating and glass sintering are done in silicon wafer front and back sides；
8) by photoetching process and etching process, metal lead wire hole window is outputed in the front and back sides of silicon wafer；
9) evaporation of metal is done in chip front side and the back side and do metal lithographic；
10) silicon wafer is sent to alloying furnace alloy.
Implementation method two (attached drawing 5)
1) silicon substrate film of boron-doping, twin polishing, thickness 300um, resistivity 0.5ohm.cm are selected.
2) after chemical cleaning, silicon wafer feeding oxidation furnace is aoxidized, 1100 DEG C of main technological temperature, the main process time
130min, oxidated layer thickness
3) photoetching process and etching process are used, the oxidation layer window adulterated required for being outputed in the tow sides of silicon wafer,
That is the doping window in the area N1；Retain photoresist after outputing doping window；
4) silicon etching process is used, the N1 doped region corrosion region of front and back sides is respectively eroded into 25um；
5) after chemical cleaning, silicon wafer is sent into prediffusion boiler tube and does impurity prediffusion, doped source POLC3, main process warm
1185 DEG C of degree, main process time 50min；
6) after chemical cleaning, silicon wafer is sent into diffusion furnace tube to do and is spread, 1250 DEG C of main technological temperature, the main process time
700min；
7) chemical corrosion liquid containing hydrofluoric acid, the full oxide layer for shelling silicon chip surface are used；
8) after chemical cleaning, silicon wafer is sent into prediffusion boiler tube and does impurity prediffusion, doped source POLC3, main process warm
900 DEG C of degree, main process time 50min；
9) after chemical cleaning, silicon wafer is sent into diffusion furnace tube to do and is spread, 1250 DEG C of the main technological temperature of first segment, main technique
Time 200min, 950 degree of the main technological temperature of second segment, main process time 90min；Oxidated layer thicknessFinal N1
The diffusion junction depth 5-15um in the area diffusion junction depth 35-40um, N2 in area；
10) by photoetching process and etching process, PN junction terminal trenches are outputed in the front and back sides of silicon wafer；
11) glass blade coating and glass sintering are done in silicon wafer front and back sides；
12) by photoetching process and etching process, metal lead wire hole window is outputed in the front and back sides of silicon wafer；
13) evaporation of metal is done in chip front side and the back side and do metal lithographic；
14) silicon wafer is sent to alloying furnace alloy.
The present invention illustrates as above with regard to typical implementation method, however and the non-limiting present invention.
For example, as attached drawing 6 first does P1 doped region before doing N2 doped region.
For example, the dopant of the above doped region is transformed into the opposite dopant of conduction type, device is still the present invention.
The basic principles, main features and advantages of the present invention have been shown and described above.The technology of the industry
Personnel are it should be appreciated that the present invention is not limited to the above embodiments, and what is described in the above embodiment and the description is only the present invention
Principle, various changes and improvements may be made to the invention without departing from the spirit and scope of the present invention, these variation and
Improvement is both fallen in the range of claimed invention.The present invention claims protection scope by appended claims and its
Equivalent defines.
Claims (4)
1. the structure of TVS a kind of designs, it is characterized in that:
(1) stone there are into diffusing, doping area N1 and N2 in the tow sides of substrate P0；The junction depth ratio of the total doping concentration ratio N2 high, N1 of N1
N2 is deep；
(2) diffusing, doping area N1 and N2 is connected with each other, N1 and N2 are same type of impurity by impurity diffusion；
(3) diffusing, doping area N1 and N2 and substrate P0 form a big PN junction, and the junction of this big PN junction is along doped region N1
With the periodically concave-convex variation of N2；
(4) when PN junction reverse bias, puncture first at the PN junction junction of diffusing, doping area N2 and substrate P0, breakdown curve tool
There is positive resistance characteristic；It is secondary at the PN junction junction of diffusing, doping area N1 and substrate P0 to puncture afterwards, start to generate conductance tune in PN junction
Effect processed；
(5) terminal of TVS is passivated layer protection.
2. the structure design of TVS as described in claim 1 a kind of, is characterized in that: concentration 1e13~1e19atom/ of substrate P0
Cm3, the thickness of substrate P0 is in 100um~500um；Peak concentration 1e15~1e21atom/cm3 of front doped region N1, front
The junction depth 10-200um of doped region N1；Peak concentration 1e15~1e21atom/cm3 of front doped region N2, front doped region N2
Junction depth 10-200um.
3. a kind of production method of TVS structure design as claimed in claim 2, it is characterised in that: be characterized in that comprising following
Procedure of processing:
N1 doping is done in substrate P0, is then promoted；
N2 doping is done in substrate P0, is then promoted；
The PN junction termination environment for needing to keep is outputed in chip surface；
The passivation of PN junction end area end；
It metallizes in chip front and back sides.
4. a kind of production method of TVS structure design as claimed in claim 3, is characterized in that, by the doping of the above doped region
Agent is transformed into the opposite dopant of conduction type.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910111924.1A CN109860309A (en) | 2019-02-13 | 2019-02-13 | A kind of the structure design and production method of TVS |
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| CN201910111924.1A CN109860309A (en) | 2019-02-13 | 2019-02-13 | A kind of the structure design and production method of TVS |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114038900A (en) * | 2021-09-27 | 2022-02-11 | 安徽芯旭半导体有限公司 | TVS chip and production method thereof |
| CN116169181A (en) * | 2022-09-30 | 2023-05-26 | 富芯微电子有限公司 | Low-leakage low-voltage TVS device and manufacturing method thereof |
-
2019
- 2019-02-13 CN CN201910111924.1A patent/CN109860309A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114038900A (en) * | 2021-09-27 | 2022-02-11 | 安徽芯旭半导体有限公司 | TVS chip and production method thereof |
| CN116169181A (en) * | 2022-09-30 | 2023-05-26 | 富芯微电子有限公司 | Low-leakage low-voltage TVS device and manufacturing method thereof |
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Application publication date: 20190607 |
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