CN210403741U

CN210403741U - Schottky diode core, diode and photovoltaic module

Info

Publication number: CN210403741U
Application number: CN201921536190.3U
Authority: CN
Inventors: 闫勇
Original assignee: Suzhou Chengbang Dayi Material Technology Co ltd
Current assignee: Suzhou Chengbang Dayi Material Technology Co ltd
Priority date: 2019-09-16
Filing date: 2019-09-16
Publication date: 2020-04-24
Anticipated expiration: 2029-09-16

Abstract

The utility model provides a schottky diode die, diode and photovoltaic module relates to photovoltaic power generation technical field. The tube core comprises a monocrystalline silicon substrate, a Schottky barrier junction, a control PN junction, a protection PN junction, an isolation medium, tube core positive electrode contact metal and tube core negative electrode contact metal, a plurality of corrosion pits are arranged on the first side face, the control PN junction is arranged on the walls of the corrosion pits, and the tube core positive electrode contact metal and the tube core negative electrode contact metal are led out from the first side face. The high-frequency pulse current and surge current can be reduced better, the stress of the tube core is small, and the integrated packaging is convenient.

Description

Schottky diode core, diode and photovoltaic module

Technical Field

The disclosure relates to the technical field of photovoltaic power generation, in particular to a Schottky diode core, a diode and a photovoltaic module.

Background

A schottky diode is a hot carrier diode, also called a metal-semiconductor (contact) diode or a surface barrier diode, fabricated on the basis of the metal-semiconductor junction principle, in which a metal is in contact with a semiconductor. The Schottky diode is mainly applied to the field of photovoltaic power generation by utilizing the advantage of lower forward conduction voltage drop of the Schottky diode to achieve the purpose of less electric energy loss, so that the Schottky diode is widely applied to photovoltaic modules and used as a bypass diode. Due to the particularity of the low voltage, large current and lightning induction risk of the photovoltaic module in the installation place, the bypass diode is required to have strong overcurrent capacity, surge current resistance and certain reverse voltage resistance.

In order to overcome the defect that the reverse withstand voltage of the Schottky diode is low, the power-level Schottky diode in the prior art adopts a groove type Schottky diode structure for controlling PN junctions, Metal-Oxide-Semiconductor (MOS) field effect is utilized, gaps among the control PN junctions are pinched off before the surface voltage of the Schottky diode reaches the breakdown voltage, and the control PN junctions replace the Schottky barrier junctions to bear the reverse voltage, so that the reverse breakdown voltage of the Schottky diode is greatly improved.

An additional benefit of the trench controlled PN junction structure is the increased surge current resistance of the schottky diode.

For example, shanghai advanced semiconductor manufacturing limited, in integrated circuit application No. 33, No. 8 (total No. 275), 2016, 8/month "trench schottky diode process study," a schottky diode structure and method of fabrication is described: "introduce trench design, product structure changed from planar to vertical, … …". Its main features are that with the rise of reverse voltage, the grooves are pinched off in advance by MOS effect, the electric field strength is reduced to zero before reaching the silicon surface, so avoiding the breakdown on the surface and improving the blocking ability. In addition, it has other incomparable advantages compared with the plane diode, mainly manifested in the enhancement of ESD (Electro-Static discharge) and anti-surge current capability, … … ″.

The main process characteristics for manufacturing the device are as follows:

(1) etching the groove;

(2) and (5) carrying out polycrystalline etching back. After the groove is etched, filling polycrystalline silicon, and reversely etching the polycrystalline silicon;

(3) etching a contact hole;

(4) and (4) barrier metal process.

The defects of the prior art are as follows:

(1) the trenches in the trench schottky diode create stress in the silicon wafer that makes the die susceptible to cracking. In order to overcome the defect, in the prior art, after the groove is doped, the groove is backfilled by polysilicon, so that the process cost is increased;

(2) because the conductivity of the backfilled polysilicon is poorer than that of metal, the capability of improving the surge current of the Schottky diode in the prior art is adversely affected;

(3) the arrangement of the trenches increases the local current density, and the flow of the substrate lateral current must bypass the 'isolation wall' formed by the trenches, thereby increasing the series resistance of the device;

(4) considering the skin effect of high-frequency current, the diode core with the groove type layout is superior to the diode core with the plane layout in the aspect of quickly eliminating the induction voltage of the high-frequency lightning inductor, but the novel point type layout has better high-frequency current dispersion capability;

(5) another disadvantage of the prior art is that the cathode of the schottky diode is led out from the substrate surface, and for the bypass diode packaged in the photovoltaic module, the thicknesses of the double-sided outgoing line, the tube core and the device are increased, which is not favorable for integrated packaging.

SUMMERY OF THE UTILITY MODEL

The schottky diode die, the schottky diode and the photovoltaic module are provided, so that the schottky diode has better surge current resistance, reverse blocking voltage of the schottky diode is improved, and leakage current is reduced, and the schottky diode die has the advantages of small mechanical stress of a chip, low manufacturing cost, thin thickness of the chip and convenience in integrated packaging.

In order to achieve the above purpose, the technical scheme adopted by the disclosure is as follows:

in a first aspect, the present disclosure provides a schottky diode die, including a single-crystal silicon substrate, a schottky barrier junction, a control PN junction, a protection PN junction, an isolation medium, a die positive electrode contact metal, and a die negative electrode contact metal:

a plurality of etch pits are arranged on the first side surface of the monocrystalline silicon substrate, the etch pits are regularly arranged on the first side surface of the monocrystalline silicon substrate, and the control PN junction is arranged on the etch pit walls;

the Schottky barrier junction is arranged on a plane of the first side face of the monocrystalline silicon substrate adjacent to the control PN junction, the protection PN junction is arranged on the edge of the Schottky barrier junction which is not adjacent to the control PN junction, and the edge of the Schottky barrier junction is jointed with the control PN junction or the protection PN junction;

the tube core positive electrode contact metal is in ohmic contact with the positive electrode of the Schottky barrier junction, the positive electrode of the control PN junction and the positive electrode of the protection PN junction, the tube core negative electrode contact metal is in ohmic contact with the monocrystalline silicon substrate, and the tube core positive electrode contact metal and the tube core negative electrode contact metal are both led out from the first side surface of the monocrystalline silicon substrate;

the isolation medium covers the area of the first side surface of the monocrystalline silicon substrate except for the electrode contact area, the electrode contact area comprises the contact metal of the positive electrode of the tube core and the area of the positive electrode of the Schottky barrier junction, the positive electrode of the control PN junction and the positive electrode of the protection PN junction, and the contact metal of the negative electrode of the tube core and the area of the monocrystalline silicon substrate.

Optionally, the cathode of the schottky barrier junction, the cathode of the control PN junction, and the cathode of the protection PN junction are led out through the first side surface of the single crystal silicon substrate.

Optionally, the single-crystal silicon substrate comprises a plurality of conductive vias penetrating through the single-crystal silicon substrate, the die negative electrode contact metal extends to the conductive vias and a second side of the single-crystal silicon substrate opposite to the first side, and the negative electrode of the schottky barrier junction, the negative electrode of the control PN junction, and the negative electrode of the protection PN junction are led to the first side of the single-crystal silicon substrate through the single-crystal silicon substrate, the ohmic contact, and the die negative electrode contact metal.

Optionally, the first side of the single crystal silicon substrate is provided with an epitaxial layer, the epitaxial layer is the same as the single crystal silicon substrate in material and conductivity type and is doped with less impurities than the single crystal silicon substrate, and the schottky barrier junction is arranged on the epitaxial layer.

Optionally, when the crystal plane of the monocrystalline silicon substrate is {111}, the etch pits are in an inverted triangular pyramid structure.

Optionally, when the crystal plane of the monocrystalline silicon substrate is {100}, the etch pits are groove-shaped structures surrounded by two trapezoidal planes and two triangular planes.

Optionally, when the crystal plane of the monocrystalline silicon substrate is {100}, the etch pits are of an inverted rectangular pyramid structure.

In a second aspect, the present disclosure is directed to a schottky diode having disposed therein a schottky diode die as in any of the first aspects.

In a third aspect, the present disclosure provides a photovoltaic module having the schottky diode of the second aspect integrated therein.

Compared with the prior art, the schottky diode die provided by the present disclosure has the following advantages:

⑴ compared with the control PN junction with the groove-shaped structure, the control PN junction 3 with the scattered three-dimensional structure increases the area and the capacitance of the control PN junction 3, thereby being more beneficial to reducing the high-frequency pulse current and the surge current and reducing the over-current damage probability of the Schottky diode;

⑵ the control PN junction 3 with the interspersed three-dimensional structure has lower substrate lateral resistance than the control PN junction with the groove-like structure;

⑶ compared with the control PN junction of the groove-shaped structure, the control PN junction 3 of the scattered three-dimensional structure leaves larger plane area for the Schottky barrier junction 4, so the present disclosure can obtain lower on-resistance and lower turn-on threshold voltage of the Schottky diode;

⑷ compared with the control PN junction with the groove structure, the control PN junction 3 with the scattered three-dimensional structure makes the stress of the Schottky diode chip more uniform and is not easy to crack, therefore, the corrosion pit does not need to be refilled by polysilicon, and the production process cost is reduced;

⑸ the on-resistance of the chip is reduced by replacing the backfilled polysilicon with the die positive electrode contact metal 7.

⑹ because the die positive electrode contact metal 7 and the die negative electrode contact metal 8 are arranged on the same side of the monocrystalline silicon substrate 1, the packaging thickness of the Schottky diode is reduced, the Schottky diode and the photovoltaic assembly are integrated and packaged, the cost of the photovoltaic assembly is reduced, and the performance and the use safety of the product are improved.

⑺ the control PN junction 3 has three-dimensional structure, so when the Schottky diode is in reverse bias, the control PN junction 3 is expanded, the channel between the control PN junctions 3 is pinched off, the control PN junction 3 bears reverse voltage, the reverse breakdown voltage of the Schottky diode can be improved, and the reverse leakage current is reduced.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. The objectives and other advantages of the disclosure may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

To more clearly illustrate the technical solutions of the present disclosure, the drawings needed for the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present disclosure, and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 shows a schematic structural diagram of a first example schottky diode die provided by the present disclosure;

fig. 2 shows a schematic structural diagram of a second schottky diode die provided by the present disclosure;

fig. 3 shows a schematic structural diagram of a third schottky diode die provided by the present disclosure;

fig. 4 is a flow chart illustrating a first exemplary method of manufacturing a schottky diode die provided by the present disclosure;

fig. 5 shows a schematic structural diagram of a single crystal silicon substrate of a first example schottky diode die provided by the present disclosure;

fig. 6 is a schematic diagram illustrating a first intermediate piece of a first example schottky diode die provided by the present disclosure;

fig. 7 is a schematic diagram illustrating a second intermediate piece of a first example schottky diode die provided by the present disclosure;

fig. 8 is a schematic diagram illustrating a third intermediate piece of the first example schottky diode die provided by the present disclosure;

fig. 9 is a schematic diagram illustrating a fourth intermediate piece of the first example schottky diode die provided by the present disclosure;

fig. 10 is a schematic diagram illustrating a fifth example schottky diode die intermediate structure provided by the present disclosure;

fig. 11 is a schematic diagram illustrating a sixth intermediate piece of a first example schottky diode die provided by the present disclosure;

fig. 12 is a schematic diagram illustrating a seventh interposer of a first example schottky diode die provided by the present disclosure;

fig. 13 is a schematic diagram illustrating an eighth interposer of a first example schottky diode die provided by the present disclosure;

fig. 14 is a schematic diagram illustrating a ninth interposer of a first example schottky diode die provided by the present disclosure;

fig. 15 is a schematic diagram illustrating a tenth interposer of a first example schottky diode die provided by the present disclosure;

fig. 16 shows a cross-sectional schematic view of a first example schottky diode die provided by the present disclosure;

fig. 17 shows a schematic structural view of a monocrystalline silicon substrate of a second schottky diode die provided by the present disclosure;

fig. 18 shows a second example schottky diode die cross-sectional schematic view provided by the present disclosure;

fig. 19 is a flow chart of a method of making a third schottky diode die provided by the present disclosure;

fig. 20 shows a schematic structural view of a single crystal silicon substrate of a third schottky diode die provided by the present disclosure;

fig. 21 shows a schematic diagram of a first intermediate piece of a third schottky diode die provided by the present disclosure;

fig. 22 shows a schematic diagram of a second intermediate piece of a third schottky diode die provided by the present disclosure;

fig. 23 illustrates a schematic diagram of a third intermediate piece of a third schottky diode die provided by the present disclosure;

fig. 24 is a schematic diagram illustrating a fourth intermediate piece of a third schottky diode die provided by the present disclosure;

fig. 25 illustrates a schematic diagram of a fifth intermediate piece of a third schottky diode die provided by the present disclosure;

fig. 26 shows a schematic diagram of a sixth intermediate piece of a third schottky diode die provided by the present disclosure;

fig. 27 is a schematic diagram illustrating a seventh interposer of a third schottky diode die provided by the present disclosure;

fig. 28 shows a schematic diagram of an eighth interposer of a third schottky diode die provided by the present disclosure;

fig. 29 illustrates a schematic diagram of a ninth interposer of a third schottky diode die provided by the present disclosure;

fig. 30 shows a schematic diagram of a tenth interposer of a third schottky diode die provided by the present disclosure;

fig. 31 is a schematic diagram illustrating an eleventh interposer of a third schottky diode die provided by the present disclosure;

fig. 32 shows a cross-sectional schematic view of a third example schottky diode die provided by the present disclosure.

Reference numbers: 1-a monocrystalline silicon substrate; 2-substrate heavily doped region; 3-controlling PN junction; a 4-Schottky barrier junction; 5-protecting PN junction; 6-isolating the dielectric process layer; 61-a separating medium; 7-die positive electrode contact metal; 8-die negative electrode contact metal; 9-etching pits; 10-an epitaxial layer; 11-schottky metal; 12-a conductive via; 13-contact metal; 31-etching pits/controlling doping process windows of PN junctions; 32-process window for protecting PN junction; 34-the process window of the schottky junction; 35-process window of die positive electrode contact metal; 36-process window for die negative electrode contact metal; 101-a first side; 102-second side.

Detailed Description

The technical solution in the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the present disclosure.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

Example 1:

fig. 1 is a schematic structural diagram of a schottky diode die according to the present disclosure. The Schottky diode tube core comprises a monocrystalline silicon substrate 1, a Schottky barrier junction 4, a control PN junction 3, a protection PN junction 5, an isolation medium 61, a tube core positive electrode contact metal 7 and a tube core negative electrode contact metal 8, wherein a plurality of etch pits 9 are arranged on a first side surface 101 of the monocrystalline silicon substrate 1, the plurality of etch pits 9 are regularly arranged on the first side surface 101 of the monocrystalline silicon substrate 1, the control PN junction 3 is arranged on the pit wall of the etch pit 9, the Schottky barrier junction 4 is arranged on the plane of the first side surface 101 of the monocrystalline silicon substrate 1 adjacent to the control PN junction 3, the protection PN junction 5 is arranged on the edge of the Schottky barrier junction 4 which is not adjacent to the control PN junction 3, the edge of the Schottky barrier junction 4 is connected with the control PN junction 3 or the protection PN junction 5, the tube core positive electrode contact metal 7 is in ohmic contact with the positive electrode of the Schottky barrier junction 4, the positive electrode of the control PN junction 3 and the positive electrode of the protection PN junction 5, the tube core negative electrode contact metal 8 is in ohmic contact with the monocrystalline silicon substrate 1, the tube core positive electrode contact metal 7 and the tube core negative electrode contact metal 8 are both led out from the first side surface 101 of the monocrystalline silicon substrate 1, the isolation medium 61 covers the region of the first side surface 101 of the monocrystalline silicon substrate 1 except for an electrode contact region, and the electrode contact region comprises the tube core positive electrode contact metal 7, the positive electrode of the Schottky barrier junction 4, the positive electrode of the control PN junction 3, the region of the positive electrode contact of the protection PN junction 5, and the region of the tube core negative electrode contact metal 8 in contact with the monocrystalline silicon substrate 1.

The monocrystalline silicon substrate 1 is an N-type substrate silicon wafer.

Etch pits 9 have a recessed structure, and a plurality of etch pits 9 are regularly arranged on side surface 101 of single-crystal silicon substrate 1 in a specific arrangement. The specific arrangement mode may include a matrix arrangement mode or a ring arrangement mode, and of course, in practical applications, the specific arrangement mode may also be a regular arrangement mode in other modes, and the mode of the regular arrangement of the plurality of etch pits 9 in the embodiment of the present disclosure is not particularly limited.

It should be noted that the inner surface of the etch pit 9 may be flat, or may be rough, or may be provided with a specific texture.

A control PN junction 3 is disposed in each etch pit 9. Since the etch pits 9 have a scattered three-dimensional structure, the control PN junctions 3 provided in the etch pits 9 also have a scattered three-dimensional structure.

In practical application, different forms of etch pits 9 (such as an inverted cone structure, an inverted frustum structure or an inverted step structure) can be obtained on different crystal plane single crystal silicon substrates 1 under different etching conditions.

Alternatively, when the crystal plane of the single-crystal silicon substrate 1 is {111}, the etch pit 9 has an inverted triangular pyramid structure using an alkaline anisotropic etch solution; when the crystal face of the monocrystalline silicon substrate 1 is {100}, the etch pit 9 is of a groove-shaped structure surrounded by two trapezoidal faces and two triangular faces; or when the crystal plane of the monocrystalline silicon substrate 1 is {100}, the etch pits 9 are in an inverted rectangular pyramid structure.

Optionally, the isolation dielectric 61 is a silicon dioxide, silicon nitride or aluminum oxide layer.

Alternatively, referring to fig. 2, monocrystalline silicon substrate 1 is a monocrystalline silicon epitaxial wafer, and epitaxial layer 10 is N^-To realize the die negative electrode contact metal8 ohmic contact with the monocrystalline silicon substrate 1, provided with a substrate N⁺The heavily doped region 2, the schottky barrier junction 4 is disposed in the epitaxial layer 10, and the substrate heavily doped region 2 penetrates the epitaxial layer 10.

When epitaxial layer 10 is provided on side 101 of single-crystal silicon substrate 1, etch pits 9 may penetrate through epitaxial layer 10, or of course may not penetrate through epitaxial layer 10.

Alternatively, referring to fig. 1 and 2, the cathode of the schottky barrier junction 4, the cathode of the control PN junction 3, and the cathode of the protection PN junction 5 are led out through the first side surface 101 of the single crystal silicon substrate 1.

Alternatively, referring to fig. 3, the single-crystal silicon substrate 1 includes a plurality of conductive vias 12 penetrating the single-crystal silicon substrate, the die negative electrode contact metal 8 extends to the conductive vias 12 and a second side 102 opposite to the first side 101 of the single-crystal silicon substrate 1, and the negative electrode of the schottky barrier junction 4, the negative electrode of the control PN junction 3, and the negative electrode of the protection PN junction 5 are led to the first side 101 of the single-crystal silicon substrate 1 through the single-crystal silicon substrate 1, the ohmic contact, and the die negative electrode contact metal 8.

Example 2:

referring to fig. 1, fig. 4, and fig. 5 to fig. 16, fig. 4 is a flowchart illustrating a method for manufacturing a schottky diode die according to the present disclosure, and fig. 5 to fig. 16 are schematic diagrams illustrating various process steps.

Step 101, adopting an N-type (100) monocrystalline silicon substrate 1, as shown in FIG. 5;

step 102, preparing an isolation medium process layer 6 on the first side 101 and the second side 102 of the monocrystalline silicon substrate 1 to obtain a first intermediate piece shown in fig. 6;

103, preparing an etch pit 9/doping process window 31 for controlling the PN junction 3 on the isolation medium process layer 6 to obtain a second intermediate piece as shown in fig. 7;

step 104, preparing an etch pit 9 by using an alkaline anisotropic etching solution through the etch pit 9/doping process window 31 for controlling the PN junction 3, so as to obtain a third intermediate member shown in fig. 8;

step 105, preparing a process window 32 for protecting the PN junction 5 on the isolation medium process layer 6 to obtain a fourth middleware shown in fig. 9;

106, preparing a control PN junction 3 and a protection PN junction 5 by doping the etch pit 9/the doping process window 31 for controlling the PN junction 3 and the doping process window 32 for protecting the PN junction 5; repairing the isolation medium process layer 6 to obtain a fifth intermediate member as shown in fig. 10;

step 107, preparing a process window 34 of the schottky barrier junction 4 on the isolation dielectric process layer 6 to obtain a sixth intermediate component shown in fig. 11;

step 108, depositing a schottky metal 11 through the process window 34 of the schottky barrier junction 4 to obtain a seventh intermediate component as shown in fig. 12;

step 109, sintering to form a schottky barrier junction 4, and removing the redundant schottky metal 11 to obtain an eighth intermediate member shown in fig. 13;

step 110, preparing a process window 35 of a die positive electrode contact metal 7 and a process window 36 of a die negative electrode contact metal 8 on the isolation medium process layer 6, and forming an isolation medium 61 to obtain a ninth middleware shown in fig. 14;

step 111, depositing a contact metal 13 through the process window 35 of the die positive electrode contact metal 7 and the process window 36 of the die negative electrode contact metal 8, and forming ohmic contact to obtain a tenth intermediate piece as shown in fig. 15;

step 112, dividing the contact metal 13 to form a die positive electrode contact metal 7 and a die negative electrode contact metal 8, and obtaining a die cross-sectional schematic diagram as shown in fig. 16, wherein fig. 1 is a structural schematic diagram thereof.

Example 3:

please refer to fig. 2, 17, and 18.

The present embodiment is different from embodiment 2 in that:

referring to fig. 17, an N-type (100) silicon epitaxial wafer is used as a single crystal silicon substrate 1, and an epitaxial layer 10 is N^-Silicon with a thickness of 2 mu to 20 mu;

in order to achieve ohmic contact of the die negative electrode contact metal 8 with the monocrystalline silicon substrate 1, it is necessary to deposit the contact metal 13 through N before the process window 36 of said die negative electrode contact metal 8⁺Silicon doping prepares the substrate heavily doped region 2. The process for preparing the substrate heavily doped region 2 is a conventional process in the prior art, and thus, is not described in detail.

In this embodiment, the schottky barrier junction 4 is disposed in the epitaxial layer 10, the heavily doped substrate region 2 penetrates the epitaxial layer 10, and the etch pits 9 may or may not penetrate the epitaxial layer 10.

Example 4:

referring to fig. 3, 19, and 20-32, fig. 19 is a flowchart illustrating a method for manufacturing a schottky diode die according to the present disclosure, and fig. 20-32 are schematic diagrams illustrating various process steps.

Step 301, adopting an N-type (100) epitaxial wafer single crystal silicon substrate 1, as shown in FIG. 20;

step 302, preparing a conductive through hole 12 on a monocrystalline silicon substrate 1 to obtain a first intermediate piece as shown in fig. 21;

step 303, preparing an isolation medium process layer 6 on the first side 101 and the second side 102 of the monocrystalline silicon substrate 1 to obtain a second intermediate piece as shown in fig. 22;

step 304, preparing an etch pit 9/doping process window 31 for controlling the PN junction 3 on the isolation medium process layer 6 to obtain a third intermediate member as shown in fig. 23;

step 305, preparing an etch pit 9 through the etch pit 9/doping process window 31 of the PN junction 3 by using an alkaline anisotropic etching solution, so as to obtain a fourth intermediate member shown in fig. 24;

step 306, preparing a process window 32 for protecting the PN junction 5 on the isolation medium process layer 6 to obtain a fifth middleware shown in fig. 25;

307, doping the etch pit 9/the doping process window 31 for controlling the PN junction 3 and the process window 32 for protecting the PN junction 5 to prepare a control PN junction 3 and a protection PN junction 5; repairing the isolation medium process layer 6 to obtain a sixth intermediate member as shown in fig. 26;

step 308, preparing a process window 34 of the schottky barrier junction 4 on the isolation dielectric process layer 6 to obtain a seventh intermediate component shown in fig. 27;

step 309, depositing a schottky metal 11 through the process window 34 of the schottky barrier junction 4 to obtain an eighth intermediate member as shown in fig. 28;

step 310, sintering to form a schottky barrier junction 4, and removing the redundant schottky metal 11 to obtain a ninth intermediate member as shown in fig. 29;

step 311, preparing a process window 35 of the die positive electrode contact metal 7 and a process window 36 of the die negative electrode contact metal 8 on the isolation medium process layer 6, and forming an isolation medium 61 to obtain a tenth intermediate piece as shown in fig. 30;

step 312, depositing a contact metal 13 through the process window 35 of the die positive electrode contact metal 7 and the process window 36 of the die negative electrode contact metal 8, and sintering to form an ohmic contact, thereby obtaining an eleventh intermediate component as shown in fig. 31, and it is noted that in this embodiment, the die negative electrode contact metal 8 is located on both the first side 101 and the second side 102 of the die;

step 313, the contact metal 13 is divided to form a die positive electrode contact metal 7 and a die negative electrode contact metal 8, so as to obtain a die cross section as shown in fig. 32, and fig. 3 is a schematic structural diagram thereof.

The beneficial effects of the embodiment of the preparation method of the Schottky diode core are the same as those of the Schottky diode core, and are not repeated here.

Example 5

The present disclosure also provides a schottky diode having any of the above schottky diode dies disposed therein.

The beneficial effects of the schottky diode are similar to those of the schottky diode core, and are not repeated here.

Example 6

The present disclosure also provides a photovoltaic module having any of the above schottky diodes disposed therein.

The beneficial effects of the photovoltaic module are similar to those of the Schottky diode core, and are not repeated here.

In the several embodiments provided in the present disclosure, it should be understood that the above-described apparatus embodiments are merely illustrative, and the disclosed apparatus and method may be implemented in other ways. For example, the division of the unit is only a logical function division, and in actual implementation, there may be another division manner, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or may not be executed, for example, each unit may be integrated into one processing unit, each unit may exist alone physically, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It should be further noted that the process steps in example 2, example 3 and example 4 are within the scope of the prior art, and the sequence thereof can be adjusted, combined or split.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A Schottky diode tube core comprises a monocrystalline silicon substrate, a Schottky barrier junction, a control PN junction, a protection PN junction, an isolation medium, a tube core positive electrode contact metal and a tube core negative electrode contact metal, and is characterized in that:

2. The schottky diode die of claim 1 wherein the cathode of the schottky barrier junction, the cathode of the control PN junction, and the cathode of the protection PN junction exit through the first side of the single crystal silicon substrate.

3. The schottky diode die of claim 2 wherein the single crystal silicon substrate includes a plurality of conductive vias penetrating the single crystal silicon substrate, the die negative electrode contact metal extends to the conductive vias and to a second side of the single crystal silicon substrate opposite the first side, and the cathode of the schottky barrier junction, the cathode of the control PN junction, the cathode of the protection PN junction are directed to the first side of the single crystal silicon substrate through the single crystal silicon substrate, ohmic contact, and the die negative electrode contact metal.

4. The schottky diode die of claim 1 wherein the first side of the single-crystal silicon substrate is provided with an epitaxial layer of the same material and conductivity type as the single-crystal silicon substrate and less doped than the single-crystal silicon substrate, the schottky barrier junction being provided on the epitaxial layer.

5. The schottky diode die of claim 1 wherein the etch pits are of inverted triangular pyramid configuration when the crystal plane of the single crystal silicon substrate is {111 }.

6. The schottky diode die of claim 1 wherein the etch pits are trench-shaped structures bounded by two trapezoidal faces and two triangular faces when the crystallographic plane of the single-crystal silicon substrate is {100 }.

7. The schottky diode die of claim 1 wherein the etch pits are inverted rectangular pyramid structures when the crystal plane of the single crystal silicon substrate is {100 }.

8. A schottky diode wherein the schottky diode die of any of claims 1-7 is disposed therein.

9. A photovoltaic module having integrated therein the schottky diode of claim 8.