CN212725323U - Silicon carbide MPS device - Google Patents
Silicon carbide MPS device Download PDFInfo
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- CN212725323U CN212725323U CN202021269885.2U CN202021269885U CN212725323U CN 212725323 U CN212725323 U CN 212725323U CN 202021269885 U CN202021269885 U CN 202021269885U CN 212725323 U CN212725323 U CN 212725323U
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Abstract
The utility model relates to a silicon carbide MPS device, which comprises a SiC substrate, a SiC epitaxial layer, a Schottky metal layer, a first ohmic contact metal layer and a second ohmic contact metal layer; the active region is provided with P-type regions with two specifications, the surface of the first P-type region with larger surface area and more margin is covered with a second ohmic contact metal layer, and the second ohmic contact metal layer is positioned between the first P-type region and the Schottky metal layer; and the surface of the second P-type region with smaller surface area and narrower width is not provided with a second ohmic contact metal layer. Under the condition of small current, current passes through the N-type region of the active region; under the condition of large current, the forward voltage of the diode rises, a PiN diode barrier formed by covering the ohmic contact on the surface of the first P-type region is opened, and current can pass through the region, so that the surge current capability of the diode is improved.
Description
Technical Field
The utility model relates to a semiconductor device technical field, more specifically say, relate to a carborundum MPS device.
Background
Compared with the traditional Si-based device, the SiC device has the characteristics of faster working frequency, smaller working loss, higher working temperature and the like, and the SiC diode is used as a representative device of the SiC power device and is widely applied to the fields of power supplies, new energy automobiles and the like.
The SiC SBD (Schottky Barrier Diode) has low forward voltage, high working frequency and no reverse recovery time and loss of a Pin Diode, but the working voltage can only be below 200V due to poor reverse blocking characteristics, and the requirement in the high-voltage field of 650V/1200V cannot be met.
SiC JBS (Junction Barrier Schottky) is used as an improved structure of the SiC SBD, and P-type injection of an active region is added on the basis of the structure of the SBD device. By adjusting parameters such as PN ratio, doping concentration and dosage, leakage current can be greatly reduced, reverse blocking characteristics of the JBS device are improved, and meanwhile reliability of the JBS device can be improved. However, due to the poor surge capability and instability of the JBS, the JBS cannot meet customer requirements in an application environment with high surge requirements such as a partial outdoor lightning stroke resistance test.
SiC MPS (large PiN Schottky) is a new diode structure that combines the characteristics of JBS and PiN diodes by forming an ohmic contact on top of the P-type implanted region of the active region. Under the condition of large current, the potential barrier of the Pin diode is opened, so that the surge current of the device can be further improved, and the requirements of the higher-end field are met.
In the prior art, SiC MPS usually forms a plurality of P-type injection regions in an active region, and ohmic contact metal grows on each P-type injection region, but due to the limitations of the existing equipment (lithography machine) and etching process, in order to better etch the P-type injection regions and facilitate the growth of ohmic contact metal, it is necessary to increase the area of the P-type injection regions appropriately to achieve a better process window, otherwise, an excessively high aspect ratio is not favorable for the performance of the relevant processes such as etching, metal growth, etching and the like; in addition, in order to ensure that the surge current of the device is large enough and the current is stable enough, enough P-type injection regions need to be arranged, so that the N-type conduction region is directly reduced, the forward conduction voltage drop is increased, and the conduction loss of the device is increased. Therefore, the number of P-type implanted regions is required to be in contradiction with the miniaturization design direction while ensuring the size of the N-type conductive region.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome prior art's is not enough, provides a carborundum MPS device, has guaranteed simultaneously that the MPS device possesses good forward surge ability and forward conduction characteristic, has avoided ohmic contact's the narrow technological problem who causes of process window partially simultaneously.
The technical scheme of the utility model as follows:
a silicon carbide MPS device comprises a SiC substrate, a SiC epitaxial layer, a Schottky metal layer, a first ohmic contact metal layer and a second ohmic contact metal layer; the SiC epitaxial layer is arranged on the first surface of the SiC substrate; the Schottky metal layer is arranged on the surface of the active region of the SiC epitaxial layer; the first ohmic contact metal layer is arranged on the second surface of the SiC substrate; the second ohmic contact metal layer is arranged between the SiC epitaxial layer and the Schottky metal layer; the SiC epitaxial layer is provided with an active region, and the active region comprises at least one first P-type region, a plurality of second P-type regions and an N-type region; the surface of the first P-type region is provided with a second ohmic contact metal layer, the second ohmic contact metal layer is positioned between the first P-type region and the Schottky metal layer, and the second P-type region is not provided with an ohmic contact metal layer.
Preferably, the first P-type region and the second P-type region are both strip-shaped, and the width of any one first P-type region surface is greater than the width of any one second P-type region surface.
Preferably, the first P-type regions have the same width and are arranged at equal intervals; or the widths of the first P-type regions are not all the same, and the distances between the opposite sides of the adjacent first P-type regions are the same.
Preferably, the first P-type region and the second P-type region are both block-shaped regions, and the planar area of any one first P-type region surface is larger than that of any one second P-type region surface.
Preferably, the first P-type region and the second P-type region are rectangular regions, trapezoidal regions, regular polygonal regions, circular regions, irregular regions or a combination thereof.
Preferably, the first P-type region and the second P-type region are a combination of strip-shaped and block-shaped regions; when the first P-type region is a strip-shaped region and the second P-type region is a block-shaped region, the plane area of the surface of the first P-type region is larger than that of the surface of the second P-type region; when the first P-type area is a block-shaped area and the second P-type area is a strip-shaped area, the radial width of any direction of the surface of the first P-type area is larger than that of the surface of the second P-type area.
Preferably, the total planar area of the N-type region surface is 1 to 10 times the total planar area of the first P-type region surface and the second P-type region surface; the surface width value of any one first P-type area is 1-10 mu m, the number is more than or equal to 2, and the surface width value of any one second P-type area is more than or equal to 0.1 mu m.
Preferably, the first P-type region is spaced apart from the second P-type region.
Preferably, the second ohmic contact metal layer completely covers the first P-type region.
Preferably, the second ohmic contact metal layer is a bulk metal layer that does not completely cover the first P-type region.
The utility model has the advantages as follows:
carborundum MPS device, set up the P type district of two kinds of specifications roughly, surface area is great, more abundant first P type district surface covers ohmic contact metal, ohmic contact metal is not established on surface area less, narrower narrow and small second P type district surface. Under the condition of small current, current passes through the N-type region of the active region; under the condition of large current, the forward voltage of the diode rises, a PiN diode barrier formed by covering the ohmic contact on the surface of the first P-type region is opened, and current can pass through the region, so that the surge current capability of the diode is improved.
Drawings
Fig. 1 is a schematic structural diagram of an active region according to the first embodiment (the second ohmic contact metal layer completely covers the first P-type region);
FIG. 2 is a schematic cross-sectional view of the first embodiment (the second ohmic contact metal layer completely covers the first P-type region);
fig. 3 is a schematic structural diagram of an active region according to the first embodiment (the second ohmic contact metal layer is a bulk metal layer);
fig. 4 is a schematic structural view of an active region of the reference example;
FIG. 5 is a schematic cross-sectional view of a reference example;
FIG. 6 is a schematic diagram showing the I-V characteristic curves of the present invention in comparison with those of the reference examples;
FIG. 7 is a schematic structural diagram of an active region according to the second embodiment;
fig. 8 is a schematic structural view of an active region in the third embodiment;
in the figure: 10 is a SiC substrate, 20 is a SiC epitaxial layer, 21 is an active region, 22 is a first P-type region, 23 is a second P-type region, 24 is an N-type region, 25 is a termination region, 26 is a termination structure, 30 is a schottky metal layer, 40 is a first electrode layer, 50 is a first ohmic contact metal layer, 60 is a second electrode layer, 70 is a second ohmic contact metal layer, 81 is a first passivation layer, and 82 is a second passivation layer.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
The utility model discloses a solve the forward surge ability that prior art's MPS device exists and forward conduction characteristic difficult compromise, ohm process window can't accomplish not enough such as narrow enough (because need compromise ohm metal deposition's effect), provide a carborundum MPS device and preparation method, especially MPS device to improve the technology compatibility, simplify the complexity of technology, realize low forward conduction voltage drop, high reverse voltage, high surge current's characteristic.
Example one
As shown in fig. 1 and fig. 2, the silicon carbide MPS device of the present invention at least includes:
a SiC substrate 10;
a SiC epitaxial layer 20 disposed on a first surface of the SiC substrate 10, the SiC epitaxial layer 20 being provided with an active region 21;
a Schottky metal layer 30 arranged on the surface of the active region 21 of the SiC epitaxial layer 20;
and a first ohmic contact metal layer 50 provided on the second surface of the SiC substrate 10.
The electrode can also comprise a first electrode layer 40 and a second electrode layer 60; the first electrode layer 40 is disposed on the surface of the schottky metal layer 30; and a second electrode layer 60 disposed on the surface of the first ohmic contact metal layer 50.
The active region 21 includes at least one first P-type region 22, a plurality of second P-type regions 23, and an N-type region 24; the surface of the first P-type region 22 is provided with a second ohmic contact metal layer 70, i.e. the first P-type region 22 and the second ohmic contact metal layer 70 are in ohmic contact, the second ohmic contact metal layer 70 is located between the first P-type region 22 and the schottky metal layer 30, and the second P-type region 23 is not provided with an ohmic contact metal layer, i.e. is directly covered by the schottky metal layer 30. The second ohmic contact metal layer 70 is formed on the surface of the first P-type region 22, and the ohmic contact metal layer is not formed on the second P-type region 23. Wherein the active region of SiC epitaxial layer 20 is given the size (including but not limited to surface area) of first P-type region 22, then the size (including but not limited to surface area) of second P-type region 23 is set minimally, and the size (including but not limited to surface area) of N-type region 24 is set maximally. Also, given the size (including but not limited to surface area) of the first P-type region 22 that is provided, it is provided wider (including but not limited to width) than the size (including but not limited to surface area) of the second P-type region 23.
The utility model discloses in, the width in second P type district 23 can be implemented as narrow as possible, under the certain circumstances of active area 21 size, the accessible reduces the total plane area on first P type district 22 and second P type district 23 surface for the plane area on 24 surfaces in N type district increases, and then under the circumstances that does not increase the device area, can reduce forward pressure drop, improves forward conduction characteristic. The utility model discloses in, the effective range size that the available supply current of first P type district 22 within range passes through is in fact formed crossing scope size and decision by first P type district 22 and second ohmic contact metal layer 70, and then, on the basis that any one first P type district 22 is all enough big, can make second ohmic contact metal layer 70's shape have the diversification, and satisfy good forward surge ability, second P type district 23 can be as narrow as far as possible simultaneously. In the present invention, the relationship between the sizes of the first P-type region 22 and the second P-type region 23 can be selected by the following principle, that is, under the condition that the surface of any one of the first P-type regions 22 completely covers or partially covers the ohmic contact, assuming that the surface of any one of the second P-type regions 23 completely covers the ohmic contact, the amount of current passing through the first P-type region 22 is certainly larger than the second P-type region 23.
In specific implementations, the second ohmic contact metal layer 70 may be implemented to cover the first P-type region 22 beyond the range, or substantially coincide with the first P-type region 22, or slightly smaller than the first P-type region 22, or only cover a partial region of the first P-type region 22.
In this embodiment, the first P-type regions 22 and the second P-type regions 23 are both stripe-shaped, and the width of any one surface of the first P-type region 22 is greater than that of any one surface of the second P-type region 23. When the first P-type region 22 and the second P-type region 23 are both in the shape of a strip, and the length difference between the first P-type region 22 and the second P-type region 23 is small, the size relationship of the difference between the planar areas of the surfaces of the first P-type region 22 and the second P-type region 23 can be determined by representing the width value. The utility model discloses in, first P type district 22 sets up with 23 intervals in second P type district, avoids adjacent second ohmic contact metal level 70 to influence each other because of the heat formation that work produced, and then influences the whole heat dissipation of device, leads to the unstable performance of device.
In this embodiment, the first P-type regions 22 have the same width and are disposed at equal intervals; or, the widths of the first P-type regions 22 are not all the same, and the distances between the opposite sides of the adjacent first P-type regions 22 are the same; furthermore, the heat generated by the second ohmic contact metal layer 70 due to the operation is uniformly distributed, which is not only beneficial to heat dissipation, but also effectively controls the overall temperature rise and ensures the stability of the device operation. In one embodiment, the geometric center distance between adjacent first P-type regions 22 is 10 μm to 300 μm.
In specific implementation, the first P-type region 22 and the second P-type region 23 can be implemented as rectangular strips, trapezoidal strips, regular hexagons, irregular strips (such as wedge-shaped or other strips with irregular long edges), or a combination thereof. In this embodiment, the second ohmic contact metal layer 70 completely covers the first P-type region 22 and is implemented as a rectangular strip.
As another embodiment, as shown in fig. 3, the second ohmic contact metal layer 70 is a bulk metal layer that does not completely cover the first P type regions 22, and at least one second ohmic contact metal layer 70 is disposed on each first P type region 22. When the second ohmic contact metal layer 70 is a bulk metal layer, the centroid distance of the adjacent second ohmic contact metal layers 70 is 10 μm to 300 μm; and the second ohmic contact metal layer 70 is uniformly arranged, which is not only beneficial to uniform heat dissipation, but also effectively controls the whole temperature rise and ensures the working stability of the device.
The utility model discloses a balanced good forward surge ability and forward conduction characteristic of compromise, the total planar area of 24 tables in N type district is 1 to 10 times of the total planar area on first P type district 22 surface and second P type district 23 surface, preferably, the total planar area of 24 tables in N type district is 3 times of the total planar area on first P type district 22 surface and second P type district 23 surface. Moreover, the surface width of any one first P-type region 22 is 1-10 μm, the number is not less than 2, and the surface width of any one second P-type region 23 is not less than 0.1 μm.
As an active region delimiting the active region 21, the SiC epitaxial layer 20 is further provided with a termination region 25, the termination region 25 surrounding the active region 21 and being provided with a first passivation layer 81 on the surface of the termination region 25, the first passivation layer 81 covering the surface edge of the first electrode layer 40. Further, the first passivation layer 81 covers the second passivation layer 82 on the surface. In this embodiment, the first passivation layer 81 is a dielectric layer made of silicon oxide or silicon nitride; the second passivation layer 82 is a PI layer made of polyimide.
In order to ensure good ohmic characteristics between the first ohmic contact metal layer 50 and the SiC substrate 10, between the second ohmic contact metal layer 70 and the first P-type region 22, the first ohmic contact metal layer 50 and the second ohmic contact metal layer 70 are any one or a combination of Ti, Ni, Al, Au, Ta or W. In this embodiment, the first ohmic contact metal layer 50 and the second ohmic contact metal layer 70 are a multilayer metal of Ti/Ni combination.
In order to ensure good schottky characteristics between the schottky metal and the N-type region 24, the schottky metal layer 30 is any one or a combination of Ti, W, Ta, Ni, Mo, or Pt. In this embodiment, the schottky metal layer 30 is a multilayer metal of Ti/Ni/Ag combination.
Compare with reference example (as shown in fig. 4, fig. 5) based on prior art, suppose that the utility model discloses the area with reference example active area 21 is the same, and is provided with the same P type district of quantity, and the P type district of reference example all covers ohmic contact metal layer, in the utility model, only first P type district 22 covers second ohmic contact metal layer 70, and second P type district 23 covers second ohmic contact metal layer 70.
The utility model discloses guaranteeing to possess under the condition of the same forward surge ability with the reference example, the partial plane area of first P type district 22 and second P type district 23 is less than the total plane area of the P type district of reference example, then the utility model discloses a plane area of N type district 24 is greater than the plane area of the N type district 24 of reference example, the utility model discloses possess better forward conduction characteristic than the reference example.
Through the experiment, under the circumstances of leading to forward heavy current, the P type district of reference example can all lead to the heavy current with N type district 24, the utility model discloses the total plane area that covers second ohmic contact metal level 70 can lead to the heavy current with N type district 24, the utility model discloses possess the same forward surge ability with the reference example.
Under the circumstances of leading to forward undercurrent, reference example with the utility model discloses a 24 undercurrents that lead to in N type district, because the utility model discloses a plane area in N type district 24 is greater than reference example, and current density is higher, and then the utility model discloses compare reference example and possess better forward conduction characteristic.
As shown in fig. 6, in the present invention, under the condition of small current, the current passes through the N-type region of the active region; under the condition of large current, the forward voltage of the diode rises, a PiN diode barrier formed by covering the ohmic contact on the surface of the first P-type region is opened, and current can pass through the region, so that the surge current capability of the diode is improved.
Example two
The difference between this embodiment and the first embodiment is that the surface shapes of the first P-type region 22 and the second P-type region 23 are different, as shown in fig. 7, in this embodiment, both the first P-type region 22 and the second P-type region 23 are block-shaped regions. For the same reason as the embodiment, in the present embodiment, the planar area of the surface of any one of the first P-type regions 22 is larger than the planar area of the surface of any one of the second P-type regions 23.
In specific implementation, the first P-type region 22 and the second P-type region 23 are rectangular regions, trapezoidal regions, regular polygonal regions, circular regions, irregular regions or a combination thereof, the second ohmic contact metal layer 70 usually completely covers the first P-type region 22, and the shape of the second ohmic contact metal layer 70 is the same as that of the first P-type region 22.
The other parts are the same as the first embodiment.
EXAMPLE III
The difference between the first embodiment and the first embodiment is that the surface shapes of the first P-type region 22 and the second P-type region 23 are different, as shown in fig. 8, in the present embodiment, the first P-type region 22 and the second P-type region 23 are a combination of stripe-shaped and block-shaped regions. Like the embodiment, in the embodiment, when the first P-type region 22 is a strip-shaped region and the second P-type region 23 is a block-shaped region, the planar area of the surface of the first P-type region 22 is larger than the planar area of the surface of the second P-type region 23; when the first P-type region 22 is a block-shaped region and the second P-type region 23 is a strip-shaped region, the radial width of the first P-type region 22 in any direction is greater than the width of the second P-type region 23 in any direction.
In specific implementation, the first P-type region 22 and the second P-type region 23 are rectangular strips, trapezoidal strips, special-shaped strips, rectangular regions, regular polygonal regions, circular regions, special-shaped regions or a combination thereof, in this embodiment, the first P-type region 22 is a rectangular region, and the second P-type region 23 is a rectangular strip; and the second ohmic contact metal layer 70 generally completely covers the first P type region 22, and thus the shape of the second ohmic contact metal layer 70 is the same as that of the first P type region 22.
The other parts are the same as the first embodiment.
The utility model discloses a preparation method of carborundum MPS device specifically as follows:
1) growing SiC epitaxy having N-type active region 21 on first surface of SiC substrate 10A layer 20; specifically, RCA cleaning process is carried out on the SiC substrate 10, the crystal form of the SiC substrate 10 is 4H-SiC, the thickness is 350 μm, and the doping concentration is 1E19-1E20/cm3(ii) a Growing an N-type SiC epitaxial layer 20 on the first surface of the N-type SiC substrate 10 by using MOCVD, wherein the thickness of the SiC epitaxial layer 20 is 5-80 mu m, and the doping concentration is 1E14-5E16/cm3。
2) Depositing a protective film on the surface of the SiC epitaxial layer 20, wherein the deposition mode can be PVD or CVD, opening a plurality of spaced injection windows in the injection region of the terminal region 25 and the N-type active region 21 by dry etching, and performing ion injection on the injection region of the terminal region 25 and the injection windows of the N-type active region 21; by high temperature activation, the termination region 25 forms a termination structure 26, and the N-type active region 21 forms a plurality of first P-type regions 22 and a plurality of second P-type regions 23 arranged at intervals.
3) Covering a metal layer on the second surface of the SiC substrate 10, covering the whole or part of the surface of the first P-type region 22 with a metal layer, and not covering the surface of the second P-type region with a metal layer; through high-temperature annealing, a first ohmic contact metal layer 50 is formed on the second surface of the SiC substrate 10, and a second ohmic contact metal layer 70 is formed on the surface of the first P-type region 22.
Wherein, a metal layer is formed on the second surface of the SiC substrate 10 by deposition or sputtering, and a metal layer is formed in the first P-type region 22 by deposition or sputtering; and forming a high-temperature annealing process of the first ohmic contact metal layer 50 and the second ohmic contact metal layer 70 at the temperature of 800-1100 ℃ for 60-300 s.
4) Covering a metal layer on the surface of the SiC epitaxial layer 20, forming a Schottky metal layer 30 through high-temperature annealing, and depositing a first electrode layer 40 on the Schottky metal layer 30.
Wherein, a metal layer is formed on the surface of the SiC epitaxial layer 20 by deposition or sputtering, and a high-temperature annealing process of the Schottky metal layer 30 is formed, wherein the temperature is 300-500 ℃, and the time is 60-300 s. Continuously depositing a 2-5 mu m first electrode layer 40 on the Schottky metal layer 30 to be used as an anode electrode; the schottky metal layer 30 and the first electrode layer 40 covering the terminal structure 26 are removed by an etching method (i.e. the metal inevitably remained on the surface of the terminal structure 26 from the schottky metal layer 30 and the first electrode layer 40 in the preparation process).
5) Growing a 0.5-3 mu m dielectric layer on the surface of the terminal structure 26 by CVD or PVD to serve as a first passivation layer 81, and coating 2-5 mu m Polyimide on the surface of the first passivation layer 81 to serve as a second passivation layer; etching by a wet or dry etching method to obtain a contact region of the first electrode layer 40; and depositing a 2-5 μm second electrode layer 60 on the surface of the first ohmic contact metal layer 50 to serve as a cathode electrode.
In this embodiment, the first ohmic contact metal layer 50 in step 3) may also be prepared in step 5); the second electrode layer 60 in step 5) may be prepared continuously after the first ohmic contact metal layer 50 in step 3) is prepared, or may be prepared at intervals from the first ohmic contact metal layer 50 in step 3).
Wherein, in the step 1), the doping concentration of the SiC substrate 10 is preferably 2E19/cm3(ii) a The thickness of the SiC epitaxial layer 20 is preferably 10 μm, and the doping concentration is preferably 1E16/cm3。
In step 3), the first ohmic contact metal layer 50 and the second ohmic contact metal layer 70 are preferably multilayer metals of Ti/Ni combination; the process temperature is preferably 950 ℃ and the time is preferably 100 s;
in the step 4), the schottky metal layer 30 is preferably Ti; the process temperature is preferably 450 ℃ and the time is preferably 100 s; the first electrode layer 40 is preferably Al and preferably 4 μm thick.
In step 5), the first passivation layer 81 is preferably silicon oxide SiO2The thickness is preferably 1.2 μm, and the thickness of the second passivation layer 82 is preferably 5 μm; the second electrode layer 60 is preferably a multilayer metal of Ti/Ni/Ag combination, preferably 2 μm thick.
Based on the above-described manufacturing method, the silicon carbide MPS devices according to the first, second, and third embodiments can be manufactured according to the structures described in the first, second, and third embodiments.
The above embodiments are merely illustrative, and not restrictive, of the present invention. Changes, modifications, etc. to the above-described embodiments are intended to fall within the scope of the claims of the present invention, as long as they are in accordance with the technical spirit of the present invention.
Claims (10)
1. The silicon carbide MPS device is characterized by comprising a SiC substrate, a SiC epitaxial layer, a Schottky metal layer, a first ohmic contact metal layer and a second ohmic contact metal layer; the SiC epitaxial layer is arranged on the first surface of the SiC substrate; the Schottky metal layer is arranged on the surface of the active region of the SiC epitaxial layer; the first ohmic contact metal layer is arranged on the second surface of the SiC substrate; the second ohmic contact metal layer is arranged between the SiC epitaxial layer and the Schottky metal layer; the SiC epitaxial layer is provided with an active region, and the active region comprises at least one first P-type region, a plurality of second P-type regions and an N-type region; the surface of the first P-type region is provided with a second ohmic contact metal layer, the second ohmic contact metal layer is positioned between the first P-type region and the Schottky metal layer, and the second P-type region is not provided with an ohmic contact metal layer.
2. The silicon carbide MPS device of claim 1, wherein the first P-type region and the second P-type region are both stripe shaped, and wherein a width of a surface of any one of the first P-type regions is greater than a width of a surface of any one of the second P-type regions.
3. The silicon carbide MPS device of claim 2, wherein the first P-type regions are of equal width and are equally spaced; or the widths of the first P-type regions are not all the same, and the distances between the opposite sides of the adjacent first P-type regions are the same.
4. The silicon carbide MPS device of claim 1, wherein the first and second P-type regions are both bulk regions, and wherein a planar area of a surface of any one of the first P-type regions is greater than a planar area of a surface of any one of the second P-type regions.
5. The silicon carbide MPS device of claim 4, wherein the first P-type region, the second P-type region is a rectangular region, a trapezoidal region, a regular polygonal region, a circular region, a shaped region or a combination thereof.
6. The silicon carbide MPS device of claim 1, wherein the first P-type region and the second P-type region are a combination of stripe and bulk regions; when the first P-type region is a strip-shaped region and the second P-type region is a block-shaped region, the plane area of the surface of the first P-type region is larger than that of the surface of the second P-type region; when the first P-type area is a block-shaped area and the second P-type area is a strip-shaped area, the radial width of any direction of the surface of the first P-type area is larger than that of the surface of the second P-type area.
7. The silicon carbide MPS device of any of claims 1 to 6, wherein the total planar area of the N-type region surface is 1 to 10 times the total planar area of the first and second P-type region surfaces; the surface width value of any one first P-type area is 1-10 mu m, the number is more than or equal to 2, and the surface width value of any one second P-type area is more than or equal to 0.1 mu m.
8. The silicon carbide MPS device of any one of claims 1 to 6, wherein the first P-type region is spaced apart from the second P-type region.
9. The silicon carbide MPS device of any of claims 1 to 6, wherein the second ohmic contact metal layer completely covers the first P-type region.
10. The silicon carbide MPS device of any of claims 1 to 6, wherein the second ohmic contact metal layer is a bulk metal layer not completely covering the first P-type region.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021269885.2U CN212725323U (en) | 2020-07-01 | 2020-07-01 | Silicon carbide MPS device |
| US16/928,373 US11437525B2 (en) | 2020-07-01 | 2020-07-14 | Silicon carbide power diode device and fabrication method thereof |
| PCT/CN2021/103440 WO2022002111A1 (en) | 2020-07-01 | 2021-06-30 | Silicon carbide power diode device and fabrication method thereof |
| JP2022580919A JP2023532305A (en) | 2020-07-01 | 2021-06-30 | Silicon carbide power diode device and manufacturing method thereof |
| EP21182970.0A EP3933934A1 (en) | 2020-07-01 | 2021-06-30 | Silicon carbide power diode device and fabrication method thereof |
| US17/828,782 US11967651B2 (en) | 2020-07-01 | 2022-05-31 | Silicon carbide power diode device and fabrication method thereof |
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| CN202021269885.2U CN212725323U (en) | 2020-07-01 | 2020-07-01 | Silicon carbide MPS device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022002111A1 (en) * | 2020-07-01 | 2022-01-06 | Xiamen Sanan Integrated Circuit Co., Ltd. | Silicon carbide power diode device and fabrication method thereof |
| US11437525B2 (en) | 2020-07-01 | 2022-09-06 | Hunan Sanan Semiconductor Co., Ltd. | Silicon carbide power diode device and fabrication method thereof |
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2020
- 2020-07-01 CN CN202021269885.2U patent/CN212725323U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022002111A1 (en) * | 2020-07-01 | 2022-01-06 | Xiamen Sanan Integrated Circuit Co., Ltd. | Silicon carbide power diode device and fabrication method thereof |
| US11437525B2 (en) | 2020-07-01 | 2022-09-06 | Hunan Sanan Semiconductor Co., Ltd. | Silicon carbide power diode device and fabrication method thereof |
| US11967651B2 (en) | 2020-07-01 | 2024-04-23 | Xiamen Sanan Integrated Circuit Co., Ltd. | Silicon carbide power diode device and fabrication method thereof |
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