CN117059653A - Field limiting ring terminal structure, preparation method and semiconductor power device - Google Patents
Field limiting ring terminal structure, preparation method and semiconductor power device Download PDFInfo
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- CN117059653A CN117059653A CN202311248565.7A CN202311248565A CN117059653A CN 117059653 A CN117059653 A CN 117059653A CN 202311248565 A CN202311248565 A CN 202311248565A CN 117059653 A CN117059653 A CN 117059653A
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- 230000000670 limiting effect Effects 0.000 title claims abstract description 120
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000407 epitaxy Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- 230000005684 electric field Effects 0.000 description 19
- 235000012239 silicon dioxide Nutrition 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 10
- 230000008901 benefit Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The application relates to a field limiting ring terminal structure and a preparation method thereof in the technical field of semiconductors, and a semiconductor power device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a field limiting ring terminal structure, a preparation method and a semiconductor power device.
Background
In various power device structures, the JBS has the advantages of obvious simple process and reliable structure, and in the same device, the JBS combines a PiN device and a schottky diode (SBD), and by properly optimizing parameters (such as spacing) between the PiN device and the SBD device, the JBS can simultaneously have: (1) high forward bias high current characteristics; (2) low turn-on voltage of SBD (schottky junction) devices; and (3) the three advantages of reverse low leakage and high voltage resistance.
However, in the edge portion of the JBS device, the device is often broken down at the edge portion due to surface defects and concentrated surface electric fields caused by the process, so that in order to improve the voltage-resistant performance of the edge of the device, a special termination technology, such as a trench termination, an oblique angle termination, a junction termination, a floating field limiting ring, and the like, is developed in the prior art.
For floating field limiting rings, since the general field limiting ring structure comprises a plurality of sets of ring structures, the optimization is always very challenging, the ideal situation is that the potential of the first-stage ring (counted from the edge of the ingot zone outwards) is lower than that of the second-stage ring, the second-stage ring is lower than that of the third-stage ring, and the like, the potential of the ring of the outermost stage is close to the voltage of the forward bias, but because the upper part of the ring structure is floating, the realization of uniform voltage successive transition is not easy
Disclosure of Invention
Aiming at the defects in the prior art, the application provides a field limiting ring terminal structure, a preparation method and a semiconductor power device, and solves the problems of uneven field distribution and poor voltage resistance of the field limiting ring of the conventional power device.
In order to solve the technical problems, the application is solved by the following technical scheme:
the utility model provides a field limit ring terminal structure, includes cathode layer, substrate layer, epitaxy drift layer and anode layer, the substrate layer sets up on the cathode layer, epitaxy drift layer sets up on the substrate layer keeps away from the terminal surface of cathode layer, be provided with insulating medium layer on the terminal surface that the substrate layer was kept away from to the epitaxy drift layer, just the anode layer sets up in insulating medium layer, and with epitaxy drift layer contact setting, be provided with doping region, main junction region and field limit ring structure in the epitaxy drift layer, main junction region is located the intermediate position of epitaxy drift layer, and with anode layer contact setting, the doping region is located between main junction region and the field limit ring structure, and with anode layer contact setting, the field limit ring structure is contactless with the anode layer sets up, be provided with the field plate structure on the lateral wall of anode layer, the field plate structure with there is not electric contact between the field limit ring structure, wherein, epitaxy drift layer, be first doping type, main junction region, doping region, field limit ring structure are the second doping type and the opposite doping type.
Optionally, the field limiting ring structure comprises more than two groups of field limiting rings, and each group of field limiting rings are arranged at intervals.
Optionally, the coverage area of the field plate structure in the length direction is between a first-stage field limiting ring and a last-stage field limiting ring, wherein the length direction of the field plate structure is a direction parallel to the main junction area to the field limiting ring structure, the first-stage field limiting ring is a field limiting ring closest to the main junction area, and the last-stage field limiting ring is a field limiting ring farthest from the main junction area.
Optionally, the coverage area of the field plate structure in the length direction is between a first-stage field limiting ring and a second-stage field limiting ring, wherein the second-stage field limiting ring is a field limiting ring close to the main junction area.
Optionally, the vertical distance between the field plate structure and the field limiting ring structure is set in the following range: 400 nm-1000 nm.
Optionally, the vertical distance between the field plate structure and the field limiting ring structure is 800nm.
Optionally, the insulating medium layer is oxide.
A semiconductor power device comprising a field limiting ring termination structure as claimed in any one of the preceding claims.
A method of preparing a field limiting ring terminal structure, the method being used to prepare a field limiting ring terminal structure as defined in any one of the preceding claims.
Compared with the prior art, the technical scheme provided by the application has the following beneficial effects:
through the setting of field plate structure, the setting of perpendicular interval between field plate structure and the field limit ring structure, the setting of the coverage area of field plate structure in the length direction, the peak electric field of restraining first order field limit ring for the holistic withstand voltage performance of device improves.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a block diagram of a field limiting ring terminal structure according to a first embodiment;
fig. 2 is an equivalent circuit diagram of the device according to the first embodiment in blocking;
FIG. 3 is a graph showing the relationship between the voltage resistance and the thickness of the insulating dielectric layer between the field plate structure and the field limiting ring structure according to the first embodiment;
FIG. 4 is a graph showing a lateral electric field distribution of a device according to one embodiment of the present application at 0.4 μm below the surface of the field plate structure;
FIG. 5 is a graph showing electric field distribution in silicon dioxide for devices with different thickness of silicon dioxide according to the first embodiment;
fig. 6 is a diagram showing the effect of different widths of the coverage area of the field plate structure in the length direction on the device voltage withstanding characteristic according to the first embodiment.
Detailed Description
The present application will be described in further detail with reference to the following examples, which are illustrative of the present application and are not intended to limit the present application thereto.
Example 1
As shown in fig. 1, a Field limiting ring terminal structure includes a Cathode layer (Cathode), a substrate layer, an epitaxial drift layer (n-drift layer) and an Anode layer (Anode), the substrate layer is disposed on the Cathode layer, the epitaxial drift layer is disposed on an end surface of the substrate layer far away from the Cathode layer, an insulating dielectric layer is disposed on an end surface of the epitaxial drift layer far away from the substrate layer, the insulating dielectric layer is oxide, and the Anode layer is disposed in the insulating dielectric layer and is in contact with the epitaxial drift layer, a doped region (p+ area), a Main Junction region (Main Junction) and a Field limiting ring structure (Floating Guard Rings) are disposed in the epitaxial drift layer, the Main Junction region is disposed in a middle position of the epitaxial drift layer and is in contact with the Anode layer, the doped region is disposed between the Main Junction region and the Field limiting ring structure and is disposed in contact with the Anode layer, the Field limiting ring structure is disposed in a non-contact with the Anode layer, and a Field Plate structure (Field Plate) is disposed on a side wall of the Anode layer.
The substrate layer and the epitaxial drift layer are of a first doping type, the main junction region, the doping region and the field limiting ring structure are of a second doping type, and the first doping type is opposite to the second doping type, namely: when the first doping type is N-type doping, the second doping type is P-type doping; when the first doping type is P-type doping, the second doping type is N-type doping, and the doping type can be flexibly set in practical application, but the doping concentration does not change with the change of the doping type, in this embodiment, the first doping type is N-type doping, the second doping type is P-type doping, and the substrate layer is N-type heavy doping with the doping concentration of 1×10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The epitaxial drift layer is lightly doped with N-type material with doping concentration of 1×10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The main junction region, the doped region and the field limiting ring structure are all P-type heavy doping, and the doping concentration is 1 multiplied by 10 20 cm -3 。
The field limiting ring structure comprises more than two groups of field limiting rings, each group of field limiting rings are arranged at intervals, in this embodiment, the field limiting ring structure comprises six groups of field limiting rings, and at this time, the field limiting rings are sequentially marked as a first-stage field limiting ring, a second-stage field limiting ring, a third-stage field limiting ring, a fourth-stage field limiting ring, a fifth-stage field limiting ring and a sixth-stage field limiting ring according to the distance from the main junction region.
When the device is in the blocking mode, the bottom (i.e., drain) of the device is high voltage and the other electrodes are all grounded to zero, as shown in fig. 2, the potential of the first-stage field limiting ring (the other field limiting rings are similar) is closely related to the environment in which the first-stage field limiting ring is located, especially the field plate structure located above the first-stage field limiting ring, specifically, the potential of the first-stage field limiting ring directly determines the electric field between the edge (at zero potential) of the main device and the first-stage field limiting ring, and the area is often where the strongest electric field is located.
More specifically, as shown in FIG. 2, the potential distribution under blocking bias can be approximated first-order by a capacitive network model, under which the potential V of the first-order field-limiting ring R1 The expression can be as follows:wherein V is Cathode ' is the value after subtracting the voltage required for the widest depletion layer from the reverse bias voltage, C DPLT The depletion layer capacitance, C, seen by the first-stage field-limiting ring FF The first-stage field limiting ring is the capacitance with the outside, and when the field limiting ring is not arranged, the capacitance is almost zero, thus the V R1 Along with C FF And the electric field between the main device and the first-stage field limiting ring becomes smaller.
Further, as shown in fig. 1, the vertical spacing (Oxide Thickness under the plate) between the field plate structure and the field limiting ring structure is set in the following range: 400 nm-1000 nm, and the optimal vertical distance between the field plate structure and the field limiting ring structure is 800nm; the coverage area (Field Plate Width) of the field plate structure in the length direction is between a first-stage field limiting ring and a last-stage field limiting ring, wherein the length direction of the field plate structure is the direction parallel to the main junction area to the field limiting ring structure, the first-stage field limiting ring is the field limiting ring closest to the main junction area, the last-stage field limiting ring is the field limiting ring farthest from the main junction area, and the coverage area of the field plate structure in the length direction is between the first-stage field limiting ring and a second-stage field limiting ring, and the second-stage field limiting ring is the field limiting ring second close to the main junction area.
As shown in fig. 3, the insulating dielectric layer is illustrated by taking a silicon dioxide material as an example in this embodiment, the thickness of the insulating dielectric layer between the field plate structure and the field limiting ring structure is simply referred to as the silicon dioxide thickness, at this time, the field limiting ring structure is provided and includes ten groups of field limiting rings, it can be seen that the relationship between the voltage resistance performance of the device and the silicon dioxide thickness is that the voltage resistance performance of the device is firstly high and then low along with the increase of the silicon dioxide thickness, where "928V w/o FP" refers to the voltage resistance value of 928V in the case of no field plate structure, and the case of no field plate structure actually corresponds to the case of having a field plate structure, but the sandwiched silicon dioxide is extremely thick, so that, in the case of having a field plate structure, the voltage resistance value of 928V is the highest voltage resistance of 1080V, the lifting amount is 152V, which is equivalent to the voltage resistance performance of the device being improved by 16%.
Further, as shown in fig. 4, the lateral electric field distribution of the device at 0.4 micron below the surface of the field plate structure is shown, the peak electric fields of the first-stage field limiting ring and the second-stage field limiting ring are reduced, the peak electric fields corresponding to the other-stage field limiting rings are raised, specifically, fig. 3 shows the value of the electric field in the device along y= -0.4 micron (0.4 micron below the surface of the field plate structure) when the bias is blocked by 900V, and the peak electric fields at the first-stage field limiting ring and the second-stage field limiting ring are effectively inhibited by the field plate structure; meanwhile, the peak electric fields corresponding to the field limiting rings of other stages are pulled up, and as long as the highest peak value does not exceed a threshold value in all regions, the device can stably operate, and the peak electric fields caused by the field limiting rings of the first stage and the second stage are the highest in all rings, so that the voltage withstanding property of the device can be generally improved only by inhibiting the peak electric field of the field limiting ring of the first stage, namely the voltage withstanding property of the whole device is improved by inhibiting the peak electric field of the field limiting ring of the first stage.
On the other hand, the electric field distribution in the device silicon dioxide is different due to the difference of the thickness of the silicon dioxide layer, as shown in fig. 5, by taking the electric field distribution when the thickness of the silicon dioxide layer is 100nm (over-thin) and 800nm (optimal thickness) as an example, the reverse bias voltage is 900V, and as can be seen from fig. 5 (a), when the field plate structure is too close to the field limiting ring structure, the electric potential of the first-stage field limiting ring and the second-stage field limiting ring can be excessively clamped at the low level, so that the electric field between the second-stage field limiting ring and the third-stage field limiting ring can be enhanced, and the electric breakdown first occurs between the second-stage field limiting ring and the third-stage field limiting ring.
As shown in fig. 6, the effect of the range width of the coverage area of the field plate structure in the length direction on the device voltage-withstanding characteristic is shown, wherein "no FP" is a conventional structure, and no field plate structure is provided; "FP, cross FGR 1-2" is the field limiting ring of the first to second stage of the field limiting ring of the field plate structure in the coverage area in the length direction; "FP, cross fgr 1 to 4" is a field plate structure having a coverage area in the length direction in the range of the first to fourth field limiting rings, and as can be seen from fig. 6, it is sufficient that the field plate structure spans the first and second field limiting rings, and no significant performance improvement is brought about by the field plate structure spanning the first to fourth field limiting rings, so that the coverage area in the length direction of the field plate structure is set between the first and second field limiting rings.
Example two
A semiconductor power device including a field-limiting ring termination structure as described in embodiment one, for example, for use in a silicon carbide, silicon-based, or the like semiconductor power device.
Example III
A method for preparing a field limiting ring terminal structure according to any of the embodiments, which is not further described in this embodiment, is a method for preparing a field limiting ring terminal structure according to any of the embodiments, which is an existing semiconductor preparation process.
While the application has been described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and additions may be made without departing from the scope of the application. Equivalent embodiments of the present application will be apparent to those skilled in the art having the benefit of the teachings disclosed herein, when considered in the light of the foregoing disclosure, and without departing from the spirit and scope of the application; meanwhile, any equivalent changes, modifications and evolution of the above embodiments according to the essential technology of the present application still fall within the scope of the technical solution of the present application.
Claims (9)
1. The utility model provides a field limit ring terminal structure, its characterized in that includes cathode layer, substrate layer, epitaxy drift layer and anode layer, the substrate layer sets up on the cathode layer, epitaxy drift layer sets up on the substrate layer keeps away from the terminal surface of cathode layer, be provided with insulating medium layer on the terminal surface that the substrate layer was kept away from to the epitaxy drift layer, just the anode layer sets up in insulating medium layer, and with epitaxy drift layer contact setting, be provided with doping district, main junction district and field limit ring structure in the epitaxy drift layer, main junction district is located the intermediate position of epitaxy drift layer, and with anode layer contact setting, the doping district is located between main junction district and the field limit ring structure, and with anode layer contact setting, field limit ring structure and anode layer contactless setting, be provided with the field plate structure on the lateral wall of anode layer, the field plate structure with there is not electric contact between the field limit ring structure, wherein, epitaxial drift layer is first doping type, main junction district, doping district, second doping type are the opposite doping type.
2. The field limiting ring terminal structure according to claim 1, wherein the field limiting ring structure comprises more than two groups of field limiting rings, and each group of field limiting rings are arranged at intervals.
3. The field limiting ring terminal structure according to claim 2, wherein a coverage area of the field plate structure in a length direction is between a first-stage field limiting ring and a last-stage field limiting ring, wherein the length direction of the field plate structure is a direction parallel to a main junction region to the field limiting ring structure, the first-stage field limiting ring is a field limiting ring closest to the main junction region, and the last-stage field limiting ring is a field limiting ring farthest from the main junction region.
4. A field limiting ring termination structure according to claim 3, wherein the field plate structure has a lengthwise coverage area between a first level field limiting ring and a second level field limiting ring, wherein the second level field limiting ring is a second field limiting ring adjacent to the main junction region.
5. The field limiting ring terminal structure according to claim 1, wherein the vertical spacing between the field plate structure and the field limiting ring structure is set in the range of: 400 nm-1000 nm.
6. The field stop collar termination structure of claim 5 wherein the vertical spacing between the field plate structure and the field stop collar structure is 800nm.
7. The field limiting ring termination structure of claim 1, wherein the insulating dielectric layer is an oxide.
8. A semiconductor power device, characterized in that it comprises a field limiting ring termination structure according to any of claims 1-7.
9. A method for preparing a field limiting ring terminal structure, wherein the method is used for preparing a field limiting ring terminal structure according to any one of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311248565.7A CN117059653A (en) | 2023-09-26 | 2023-09-26 | Field limiting ring terminal structure, preparation method and semiconductor power device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311248565.7A CN117059653A (en) | 2023-09-26 | 2023-09-26 | Field limiting ring terminal structure, preparation method and semiconductor power device |
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| CN117059653A true CN117059653A (en) | 2023-11-14 |
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| CN202311248565.7A Pending CN117059653A (en) | 2023-09-26 | 2023-09-26 | Field limiting ring terminal structure, preparation method and semiconductor power device |
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