CN114497182A - Power device based on in-vivo multi-region terminal structure and preparation method - Google Patents
Power device based on in-vivo multi-region terminal structure and preparation method Download PDFInfo
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- 238000001727 in vivo Methods 0.000 title claims abstract description 34
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 239000002344 surface layer Substances 0.000 claims description 3
- 238000002161 passivation Methods 0.000 abstract description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 18
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000000137 annealing Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 229910052759 nickel Inorganic materials 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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Abstract
The invention relates to a power device based on an in-vivo multi-region terminal structure and a preparation method thereof, wherein the power device comprises: the device comprises a first electrode, a substrate area, an epitaxial area, a plurality of terminal structures, an oxide layer and a second electrode, wherein the first electrode, the substrate area and the epitaxial area are sequentially stacked; the plurality of terminal structures are embedded in the epitaxial region at intervals and are positioned in the terminal region, and the terminal structure close to one side of the active region is adjacent to the active region; the oxide layer is positioned on the epitaxial region and above the terminal structures; the second electrode is located on the epitaxial region and in the active region, and the second electrode is adjacent to the oxide layer. According to the power device, the plurality of terminal structures are buried in the epitaxial region, so that the terminal structures are far away from the surface of the device in space and are not easily influenced by charges inside a surface passivation layer, the influence of the charges on the voltage-resistant characteristic of the terminal structures on the interface of the device is reduced, and the power device has better charge-resistant characteristic and better stability.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a power device based on an in-vivo multi-region terminal structure and a preparation method thereof.
Background
The third generation wide bandgap semiconductor material silicon carbide (SiC) has many advantages, such as large bandgap width, high critical breakdown field strength, large thermal conductivity, high saturated electron drift velocity and low dielectric constant, and these advantages make the silicon carbide power device have obvious advantages in reducing the conversion loss of the converter, increasing the power density of the device, reducing the heat dissipation requirement, reducing the size and complexity of the system, and improving the performance of the system, so that more and more researches adopt the silicon carbide power device to replace the power device made of silicon material.
Modern power devices are made by connecting several cell structures in parallel on a silicon chip, the surface voltages of the cell structures in the active area are approximately the same, but the voltage difference between the terminal (outermost end) and the substrate is large, so measures are needed to reduce the surface electric field and improve the breakdown voltage. This technique is called a termination technique. The terminal technology arranges an extension structure at the edge of an active region, and expands a main junction depletion region outwards to improve the voltage-resistant level of the device, so that the grid of the power device is prevented from being broken down, and the purpose of protecting the chip device is achieved.
At present, a common SiC power device terminal structure is a surface terminal, however, the pressure resistance of the surface terminal structure is easily affected by surface charges, so that the pressure bearing stability of the device is reduced.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a power device based on an in-vivo multi-region terminal structure and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a power device based on an in-vivo multi-region terminal structure, which comprises: a first electrode, a substrate region, an epitaxial region, a plurality of termination structures, an oxide layer, and a second electrode,
the first electrode, the substrate region and the epitaxial region are sequentially stacked;
the terminal structures are embedded in the epitaxial region at intervals and positioned in the terminal region, and the terminal structure close to one side of the active region is adjacent to the active region;
the oxide layer is positioned on the epitaxial region and above the terminal structures;
the second electrode is located on the epitaxial region and in the active region, and the second electrode is adjacent to the oxide layer.
In one embodiment of the invention, the material of the substrate region comprises first N-type SiC with a doping concentration of 1 x 1018cm-3～1×1020cm-3The thickness is 50-400 μm;
the material of the epitaxial region comprises second N-type SiC with the doping concentration of 1 x 1014cm-3～5×1016cm-3The thickness is 5-200 μm.
In one embodiment of the present invention, each of the termination structures has a doping concentration of 5 × 1016cm-3～1×1020cm-3The width is 2-5 μm, and the thickness is 0.5-1.5 μm.
In one embodiment of the invention, the distance from the top of the terminal structure to the top of the epitaxial region is 0.5-5 μm;
the distance between two adjacent terminal structures is 1-5 μm.
In one embodiment of the invention, the number of the terminal structures is 10-200.
In one embodiment of the invention, the plurality of terminal structures are non-equidistantly distributed.
In one embodiment of the invention, the termination structure comprises a field limiting ring termination structure or a junction termination extension structure.
Another embodiment of the present invention provides a method for manufacturing a power device based on an in-vivo multi-region termination structure, including the steps of:
s1, preparing an epitaxial region and a plurality of terminal structures on the surface of the substrate region, and enabling the terminal structures to be embedded in the epitaxial region at intervals and to be located in the terminal region, wherein the terminal structure close to one side of the active region is adjacent to the active region;
s2, preparing an oxidation layer on the surface of the epitaxial region, and enabling the oxidation layer to be located above the terminal structures;
s3, depositing a metal layer on the back of the substrate area to form a first electrode;
and S4, depositing a metal layer on the surface of the epitaxial region, and forming a second electrode which is positioned in the active region and adjacent to the oxide layer.
In one embodiment of the present invention, step S1 includes:
s11, epitaxially growing the first epitaxial region on the surface of the substrate region;
s12, performing ion implantation in the surface layer of the first epitaxial region to form a plurality of terminal structures which are arranged at intervals and are positioned in the terminal region;
and S13, epitaxially growing a second epitaxial region on the surfaces of the first epitaxial region and the terminal structures to form an epitaxial region, wherein the material of the second epitaxial region is the same as that of the first epitaxial region.
In one embodiment of the present invention, step S1 includes:
s11, epitaxially growing the first epitaxial region on the surface of the substrate region;
s12, growing a target epitaxial region on the surface of the first epitaxial region, wherein the doping type of the target epitaxial region is opposite to that of the first epitaxy;
s13, etching the target epitaxial region to form a plurality of terminal structures which are arranged at intervals and are positioned in the terminal region;
and S14, growing a second epitaxial region on the target epitaxial region and the terminal structures to form an epitaxial region, wherein the material of the second epitaxial region is the same as that of the first epitaxial region.
Compared with the prior art, the invention has the following beneficial effects:
according to the power device, the plurality of terminal structures are embedded in the epitaxial region, so that the terminal structures are far away from the surface of the device in space and are not easily influenced by charges in the surface passivation layer, the influence of the device interface charges on the voltage-resistant characteristic of the terminal structures is reduced, and the power device has better charge-resistant characteristic and better stability.
Drawings
Fig. 1 is a schematic structural diagram of a power device based on an in-vivo multi-zone terminal structure according to an embodiment of the present invention;
FIGS. 2 a-2 b are schematic diagrams of two power devices based on in-vivo multi-zone termination structures according to embodiments of the present invention;
fig. 3 is a schematic flowchart of a method for manufacturing a power device based on an in-vivo multi-zone terminal structure according to an embodiment of the present invention;
FIGS. 4 a-4 f are schematic process diagrams of a method for manufacturing a power device based on an in-vivo multi-region termination structure according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of another method for manufacturing a power device based on an in-vivo multi-zone termination structure according to an embodiment of the present invention;
fig. 6a to fig. 6g are schematic process diagrams of another method for manufacturing a power device based on an in-vivo multi-region termination structure according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a power device based on an in-vivo multi-zone terminal structure according to an embodiment of the present invention. The power device based on the in-vivo multi-region terminal structure comprises: a first electrode 1, a substrate region 2, an epitaxial region 3, a plurality of terminal structures 4, an oxide layer 5 and a second electrode 6.
Wherein the first electrode 1, the substrate region 2 and the epitaxial region 3 are sequentially stacked. The plurality of terminal structures 4 are embedded in the epitaxial region 3 at intervals and are located in the terminal region, and the terminal structure 4 close to one side of the active region is adjacent to the active region. An oxide layer 5 is located on the epitaxial region 3 and above the plurality of terminal structures 4. A second electrode 6 is located on the epitaxial region 3 and in the active region, the second electrode 6 being adjacent to the oxide layer 5.
Specifically, in the power device, a side region where the second electrode 6 is located is an active region, a side region where the plurality of terminal structures 4 are located is a terminal region, the active region and the terminal region are adjacent, so that a part of the epitaxial region 3 is located in the active region, and another part is located in the terminal region; the oxide layer 5 is located in the termination region because the oxide layer 5 is located above the plurality of termination structures 4.
Further, a plurality of source region structures (not shown in the figure) are further disposed in the epitaxial region 3 located in the active region, and the source region structures may be a JBS structure, a MOSFET structure, a PiN structure, and the like, and may be located on the surface of the epitaxial region 3 or inside the epitaxial region 3. Furthermore, because the terminal structure 4 close to the active region is adjacent to the active region, the terminal structure 4 close to the active region may overlap with the active region structure or may be connected to the active region structure, so as to achieve the purpose that the terminal structure 4 extends the depletion layer at the edge of the active region of the device.
In a specific embodiment, the first electrode 1 is an ohmic contact electrode, and the material thereof includes one or more of Ni, Ti, Al, Ag, Au, and the like. The material of the substrate region 2 comprises a first N-type SiC with a doping concentration of 1X 1018cm-3～1×1020cm-3The thickness is 50-400 μm. The material of the epitaxial region 3 comprises a second N-type SiC with a doping concentration of 1X 1014cm-3～5×1016cm-3The thickness is 5-200 μm. It will be appreciated that the material of the substrate region 2 is N + SiC and the material of the epitaxial region 3 is N-SiC. The material of the oxide layer 5 may be SiO2It may also be a high-k material, such as Al2O3. According to different types of power devices, the second electrode 6 may be an ohmic contact electrode or a schottky contact electrode, and the material thereof includes one or more of Ni, Ti, Al, Ag, Au, and the like.
In one embodiment, the material of the termination structure 4 is P-type SiC with a doping concentration of 5 × 1016cm-3～1×1020cm-3Which forms a pn junction with the N-epitaxial region 3. Each terminal knotThe width of the structure 4 is 2-5 μm, and the thickness is 0.5-1.5 μm. The distance between the top of the terminal structure 4 and the top of the epitaxial region 3 is 0.5-5 μm; the distance between two adjacent terminal structures 4 is 1 μm to 5 μm.
In this embodiment, the distance from the top of the termination structure 4 to the top of the epitaxial region 3 is 0.5 μm to 5 μm, at which the effect of oxide layer charges on the termination can be ignored.
Furthermore, the number of the terminal structures 4 is 10-200. The plurality of terminal structures 4 may be distributed at equal intervals or at unequal intervals, and preferably at unequal intervals.
In a specific embodiment, the plurality of terminal structures 4 includes a field limiting ring terminal structure or a junction termination extended JTE structure, i.e., the plurality of terminal structures 4 are all field limiting ring terminal structures, or the plurality of terminal structures 4 are all JTE structures, but the type of terminal structure is not limited thereto. Referring to fig. 2 a-2 b, fig. 2 a-2 b are schematic diagrams of two power devices based on in-vivo multi-zone termination structures according to embodiments of the present invention, in which the termination structure in fig. 2a is an in-vivo field-limiting ring termination, and the termination structure in fig. 2b is an in-vivo multi-zone JTE termination.
When the power device based on the in-vivo multi-region terminal structure works, when the power device is detected to bear high bias voltage, the in-vivo terminal structure can extend a depletion layer at the edge of an active region of the device, and reduce the electric field concentration effect at the edge of the active region, so that the voltage resistance of the device is improved, wherein the multi-region structure is mutually coupled, and the voltage resistance of the device is improved by extending the action of the depletion layer; meanwhile, because the terminal structure of the device is positioned in the body, the terminal structure is not easily influenced by charges in the surface oxide layer, and therefore compared with the traditional plane terminal structure, the terminal structure in the body has better charge resistance and stability.
In summary, in the power device of the embodiment, the plurality of terminal structures are embedded in the epitaxial region, so that the terminal structures are spatially far away from the surface of the device, the influence of the interface charges of the device on the voltage withstanding property of the terminal structures is reduced, and the power device has better charge withstanding property and better stability.
Example two
On the basis of the first embodiment, please refer to fig. 3 and fig. 4a to 4f, fig. 3 is a schematic flow chart of a method for manufacturing a power device based on an in-vivo multi-zone terminal structure according to an embodiment of the present invention, and fig. 4a to 4f are schematic process diagrams of a method for manufacturing a power device based on an in-vivo multi-zone terminal structure according to an embodiment of the present invention. The preparation method comprises the following steps:
s1, preparing an epitaxial region 3 and a plurality of terminal structures 4 on the surface of the substrate region 2, so that the terminal structures 4 are embedded in the epitaxial region 3 at intervals and are located in the terminal region, and the terminal structure 4 close to one side of the active region is adjacent to the active region.
In this embodiment, the method of chemical vapor deposition and ion implantation is used to form the epitaxial region 3 and the terminal structure 4, and specifically includes the following steps:
s11, epitaxially growing a first epitaxial region 31 on the surface of the substrate region 2, as shown in fig. 4 a.
Specifically, a first epitaxial region 31 is grown on the surface of the N + SiC substrate region 2 by a Chemical Vapor Deposition (CVD) method, the material of the first epitaxial region 31 is N-SiC, and the growth temperature is 1600 ℃ to 1900 ℃.
S12, performing ion implantation on the surface layer of the first epitaxial region 31 to form a plurality of terminal structures 4 arranged at intervals and located in the terminal region, as shown in fig. 4 b.
Specifically, a plurality of terminal structures arranged at intervals are formed on the surface of the first epitaxial region 31 by ion implantation, the implanted ions are Al, and the implantation energy range is 10keV to 800 keV. The prepared terminal structure 4 may be a field limiting ring terminal structure or a JTE terminal structure.
S13, epitaxially growing a second epitaxial region 32 on the first epitaxial region 31 and the surfaces of the terminal structures 4 to form an epitaxial region 3, wherein the material of the second epitaxial region 32 is the same as the material of the first epitaxial region 31, see fig. 4 c.
Specifically, the second epitaxial region 32 is epitaxially grown again on the surfaces of the first epitaxial region 31 and the plurality of terminal structures 4 by a CVD method, the growth temperature is 1600 ℃ to 1900 ℃, and the second epitaxial region 32 and the first epitaxial region 31 together form the epitaxial region 3. Wherein, the material of the second epitaxial region 32 may be the same as the material of the first epitaxial region 31, and is N — SiC.
S2, preparing an oxide layer 5 on the surface of the epitaxial region 3, such that the oxide layer 5 is located above the plurality of terminal structures 4, as shown in fig. 4 d.
Specifically, an oxide layer 5 is formed on the surface of the epitaxial region 3 by a thermal oxidation process, wherein the oxidation temperature is 1100-1400 ℃.
S3, a metal layer is deposited on the back surface of the substrate region 2 to form the first electrode 1, as shown in fig. 4 e.
Specifically, a metal layer is deposited on the back surface of the substrate region 2, the first electrode 1 is formed through an annealing process, the material of the first electrode 1 can be Ti, Ni and the like, and the annealing temperature is 400-1000 ℃.
S4, depositing a metal layer on the surface of the epitaxial region 3, and forming a second electrode 6 in the active region and adjacent to the oxide layer 5, as shown in fig. 4 f.
Specifically, the second electrode 6 is formed on the surface electrode metal layer of the epitaxial region 3 through an annealing process, the first electrode 6 may be made of Ti, Ni, or the like, and the annealing temperature is 400 ℃ to 1000 ℃.
The preparation method of the embodiment grows the first epitaxial region first, performs ion implantation to form a plurality of terminal structures, and then grows the second epitaxial region, so that the terminal structures are buried in the epitaxial region, the terminal structures are spatially far away from the surface of the device and are not easily influenced by charges in a surface passivation layer, the influence of the charges on the interface of the device on the voltage-resistant characteristic of the terminal structures is reduced, and the power device has better charge-resistant characteristic and better stability.
EXAMPLE III
On the basis of the first embodiment, please refer to fig. 5 and fig. 6a to 6g, fig. 5 is a schematic flow chart of a method for manufacturing a power device based on an in-vivo multi-zone termination structure according to another embodiment of the present invention, and fig. 6a to 6g are schematic process diagrams of a method for manufacturing a power device based on an in-vivo multi-zone termination structure according to another embodiment of the present invention. The preparation method comprises the following steps:
s1, preparing an epitaxial region 3 and a plurality of terminal structures 4 on the surface of the substrate region 2, so that the terminal structures 4 are embedded in the epitaxial region 3 at intervals and are located in the terminal region, and the terminal structure 4 close to one side of the active region is adjacent to the active region.
In this embodiment, the method of chemical vapor deposition and photolithography etching is used to form the epitaxial region 3 and the terminal structure 4, and specifically includes the steps of:
s11, epitaxially growing a first epitaxial region 31 on the surface of the substrate region 2, as shown in fig. 6 a.
Specifically, a first epitaxial region 31 is grown on the surface of the N + SiC substrate region 2 by a chemical vapor deposition method, the material of the first epitaxial region 31 is N-SiC, and the growth temperature is 1600-1900 ℃.
S12, growing the target epitaxial region 32 on the surface of the first epitaxial region 31, wherein the doping type of the target epitaxial region 32 is opposite to that of the first epitaxial region 31, please refer to fig. 6 b.
Specifically, the target epitaxial region 32 is grown on the surface of the first epitaxial region 31 by a chemical vapor deposition method. The doping type of the target epitaxial region 32 is opposite to the doping type of the first epitaxial region 31, that is, the material of the first epitaxial region 31 is N-SiC, and the material of the target epitaxial region 32 is P-SiC.
S13, etching the target epitaxial region 32 to form a plurality of terminal structures 4 arranged at intervals and located in the terminal region, as shown in fig. 6 c.
Specifically, the target epitaxial region 32 is etched by photolithography and ICP (Inductively Coupled Plasma) etching to form a plurality of terminal structures 4 arranged at intervals and located in the terminal region. The prepared terminal structure 4 is located on the surface of the first epitaxial region 31, and the type of the terminal structure may be a field limiting ring terminal structure or a JTE terminal structure.
S14, growing a second epitaxial region 33 on the target epitaxial region 32 and the terminal structures 4 to form an epitaxial region 3, wherein the material of the second epitaxial region 33 is the same as that of the first epitaxial region 31, see fig. 6 d.
Specifically, the second epitaxial region 33 is epitaxially grown again on the target epitaxial region 32 and the plurality of terminal structures 4 by a CVD method, the growth temperature is 1600 ℃ to 1900 ℃, and the second epitaxial region 33 and the first epitaxial region 31 together form the epitaxial region 3. The material of the second epitaxial region 33 is the same as that of the first epitaxial region 31, and may be N — SiC.
Thereafter, the surface of the epitaxial region 3, i.e., the surface of the second epitaxial region 33, is planarized by a chemical-mechanical polishing (CMP) method.
S2, preparing an oxide layer 5 on the surface of the epitaxial region 3, such that the oxide layer 5 is located above the plurality of terminal structures 4, as shown in fig. 6 e.
Specifically, an oxide layer 5 is formed on the surface of the epitaxial region 3 by a thermal oxidation process, wherein the oxidation temperature is 1100-1400 ℃.
S3, depositing a metal layer on the back of the substrate region 2 to form the first electrode 1, as shown in fig. 6 f.
Specifically, a metal layer is deposited on the back surface of the substrate region 2, the first electrode 1 is formed through an annealing process, the material of the first electrode 1 can be Ti, Ni and the like, and the annealing temperature is 400-1000 ℃.
S4, depositing a metal layer on the surface of the epitaxial region 3, and forming a second electrode 6 in the active region and adjacent to the oxide layer 5, as shown in fig. 6 g.
Specifically, the second electrode 6 is formed on the surface electrode metal layer of the epitaxial region 3 through an annealing process, the first electrode 6 may be made of Ti, Ni, or the like, and the annealing temperature is 400 ℃ to 1000 ℃.
According to the preparation method, the first epitaxial region is grown, the target epitaxial region is etched to form the terminal structure, and then the second epitaxial region is grown, so that the terminal structures are buried in the epitaxial region, the terminal structures are far away from the surface of the device in space and are not easily affected by charges inside a surface passivation layer, the influence of interface charges of the device on the voltage-resistant characteristic of the terminal structure is reduced, and the power device has better charge-resistant characteristic and better stability.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A power device based on an in-vivo multi-zone termination structure, comprising: a first electrode (1), a substrate region (2), an epitaxial region (3), a plurality of termination structures (4), an oxide layer (5) and a second electrode (6), wherein,
the first electrode (1), the substrate region (2) and the epitaxial region (3) are sequentially laminated;
the terminal structures (4) are embedded in the epitaxial region (3) at intervals and are positioned in the terminal region, and the terminal structure (4) close to one side of the active region is adjacent to the active region;
the oxidation layer (5) is positioned on the epitaxial region (3) and above the plurality of terminal structures (4);
the second electrode (6) is located on the epitaxial region (3) and in the active region, the second electrode (6) being adjacent to the oxide layer (5).
2. The in-vivo multi-zone termination structure-based power device of claim 1,
the material of the substrate region (2) comprises first N-type SiC with a doping concentration of 1 x 1018cm-3～1×1020cm-3The thickness is 50-400 μm;
the material of the epitaxial region (3) comprises second N-type SiC with the doping concentration of 1 x 1014～5×1016cm-3The thickness is 5-200 μm.
3. The in-vivo multi-zone termination structure-based power device according to claim 1, wherein each of said termination structures (4) has a doping concentration of 5 x 1016cm-3～1×1020cm-3The width is 2-5 μm, and the thickness is 0.5-1.5 μm.
4. The in-vivo multi-zone termination structure based power device according to claim 1, characterized in that the top of the termination structure (4) is at a distance of 0.5-5 μ ι η from the top of the epitaxial zone (3);
the distance between two adjacent terminal structures (4) is 1-5 μm.
5. The power device based on in-vivo multi-zone terminal structure according to claim 1, characterized in that the number of terminal structures (4) is 10-200.
6. The in-vivo multi-zone termination structure-based power device according to claim 1, wherein the several termination structures (4) are non-equidistantly distributed.
7. The in-vivo multi-zone termination structure based power device according to claim 1, characterized in that the termination structure (4) comprises a field-limiting ring termination structure or a junction termination extension structure.
8. A preparation method of a power device based on an in-vivo multi-region terminal structure is characterized by comprising the following steps:
s1, preparing an epitaxial region (3) and a plurality of terminal structures (4) on the surface of a substrate region (2), and enabling the terminal structures (4) to be embedded in the epitaxial region (3) at intervals and located in the terminal region, wherein the terminal structure (4) close to one side of an active region is adjacent to the active region;
s2, preparing an oxide layer (5) on the surface of the epitaxial region (3) so that the oxide layer (5) is located above the terminal structures (4);
s3, depositing a metal layer on the back of the substrate area (2) to form a first electrode (1);
s4, depositing a metal layer on the surface of the epitaxial region (3) to form a second electrode (6) which is positioned in the active region and adjacent to the oxide layer (5).
9. The method for preparing a power device based on in-vivo multi-region termination structure according to claim 8, wherein the step S1 comprises:
s11, epitaxially growing a first epitaxial region (31) on the surface of the substrate region (2);
s12, performing ion implantation in the surface layer of the first epitaxial region (31) to form a plurality of terminal structures (4) which are arranged at intervals and are positioned in the terminal region;
s13, epitaxially growing a second epitaxial region (32) on the surfaces of the first epitaxial region (31) and the terminal structures (4) to form an epitaxial region (3), wherein the material of the second epitaxial region (32) is the same as that of the first epitaxial region (31).
10. The method for preparing a power device based on in-vivo multi-region termination structure according to claim 8, wherein the step S1 comprises:
s11, epitaxially growing a first epitaxial region (31) on the surface of the substrate region (2);
s12, growing a target epitaxial region (32) on the surface of the first epitaxial region (31), wherein the doping type of the target epitaxial region (32) is opposite to that of the first epitaxial region (31);
s13, etching the target epitaxial region (32) to form a plurality of terminal structures (4) which are arranged at intervals and are positioned in the terminal region;
s14, growing a second epitaxial region (33) on the target epitaxial region (32) and the terminal structures (4) to form an epitaxial region (3), wherein the material of the second epitaxial region (33) is the same as that of the first epitaxial region (31).
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