CN102664197A - JFET (Junction Field Effect Transistor) and manufacturing method thereof, and micro inverter using JFET - Google Patents
JFET (Junction Field Effect Transistor) and manufacturing method thereof, and micro inverter using JFET Download PDFInfo
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Abstract
The invention discloses a JFET (Junction Field Effect Transistor) and a manufacturing method thereof, and a micro inverter using the JFET. The JFET comprises a drain ohmic contact electrode, a substrate, a SiC drift layer, an N-type SiC channel layer, an N-type SiC ohmic contact layer and two gate Schottky contact electrodes. The manufacturing method comprises the following steps of providing the substrate; forming a SiC epitaxial layer; forming the N-type SiC channel layer and the SiC drift layer; forming the N-type SiC ohmic contact layer; forming drain and source ohmic contact electrodes; and forming the two gate Schottky contact electrodes. The micro inverter comprises capacitors C1, C2 and C3, an inductor L1, a JFET1, a JFET2 and a JFET3, and silicon carbide Schottky diodes D1, D2, D3 and D4. According to the JFET, the manufacturing method thereof, and the micro inverter, the realization is convenient, the cost is low, the working frequency and the working reliability of the micro inverter are improved, the loss and the price of electric energy are reduced, and the practicality is high.
Description
Technical field
The present invention relates to semiconductor device and semiconductor process techniques field, the miniature inverter that especially relates to a kind of JFET and manufacturing approach thereof and use this JFET.
Background technology
Photovoltaic power generation technology is considered to new energy technology the most promising in the world today.Inverter is the key equipment in the solar energy photovoltaic system.The combining inverter product mainly is a centralized inverter in the market, and it is with after the photovoltaic cell connection in series-parallel, reaches a HVDC, converts interchange into through inverter again.Because the drawback that unbalanced, local shade of battery panel performance or dirt, different degree of aging etc. cause system mismatch to cause delivery efficiency to descend easily, and then cause whole power output significantly to reduce.This is the insoluble problem of centralized inverter.
Miniature inverter is mounted in the small-sized inversion device on each battery component, is optimized through the power output to each piece battery, makes whole electric energy power output maximize.Even the part cell panel is because a variety of causes causes decreased performance like this, miniature inverter still can be followed the tracks of best local MPPT (maximum power point), can retrieve a considerable amount of energy output.
The operational environment of miniature inverter and application background make it need have high frequency, high efficiency, high power density, characteristics such as highly reliable.One of key factor that influences miniature inverter is a power semiconductor, because the energy loss that produces on state resistance, leakage current and the switching process of power device can cause quite a few energy loss, thereby reduces the service efficiency of the energy content of battery.The raising of power device blocking voltage can cause the rising of device on state resistance, and the raising of operating frequency also can cause the further increase of power consumption.
The power device that uses at present mainly is traditional material semiconductor device such as silicon, owing to receive the restriction of material property, the electric property of device has not had too big raising space.Be difficult to satisfy the growth requirement of miniature inverter.The carbofrax material energy gap is big, critical breakdown electric field is higher, thermal conductivity is high; Have the operating frequency higher, higher puncture voltage and working temperature ability to bear with its power semiconductor of processing, have lower switching loss and homomorphism resistance ratio simultaneously again than Si device.Therefore, adopt silicon carbide power device can significantly improve the performance of miniature inverter.
Along with the maturation gradually of technology and device, the SiC power device has begun to be applied in the power electronic technology.Aspect power diode, SiC Schottky diode (SBD) commercialization for many years, many companies can provide the commercial SiC SBD of different electric pressures.But the SiC power device also has a lot of problems to need to solve at present, and wherein maximum problem is that the development of SiC full-control type power device is relatively slow.Have only fewer companies can provide kind more single SiC full-control type power device in the market, and expensive, be difficult to be widely used in the such civil area of photovoltaic.
Summary of the invention
Technical problem to be solved by this invention is to above-mentioned deficiency of the prior art, provide a kind of simple in structure, volume is little, convenient processing and manufacture and the good JFET (junction field effect transistor junction field effect transistor) of electrology characteristic.
For solving the problems of the technologies described above; The technical scheme that the present invention adopts is: a kind of JFET; It is characterized in that: comprise the substrate that constitutes by N type SiC substrate and be arranged on the SiC epitaxial loayer on the said substrate top surface; The first half of said SiC epitaxial loayer is step-like and is the N type SiC channel layer of said JFET; The latter half of said SiC epitaxial loayer is the SiC drift layer of said JFET; The top of said N type SiC channel layer is provided with N type SiC ohmic contact layer, and the bottom of said substrate is provided with the drain electrode Ohm contact electrode, and the top of said N type SiC ohmic contact layer is provided with the source electrode Ohm contact electrode; One side sidewall of one upper lateral part of said SiC drift layer and said N type SiC channel layer is provided with first grid schottky junctions touched electrode, and the opposite side sidewall of the opposite side top of said SiC drift layer and said N type SiC channel layer is provided with second grid schottky junctions touched electrode.
Above-mentioned JFET is characterized in that: the thickness of said SiC epitaxial loayer is 5 μ m～20 μ m; The width of said N type SiC channel layer is that 0.5 μ m～2 μ m, thickness are 1 μ m～3 μ m.
Above-mentioned JFET; It is characterized in that: said drain electrode Ohm contact electrode and source electrode Ohm contact electrode constitute by from top to bottom a Ni layer and Pt layer successively; The thickness of a said Ni layer is 200nm～400nm, and the thickness of said Pt layer is 50nm～200nm.
Above-mentioned JFET; It is characterized in that: said first grid schottky junctions touched electrode and said second grid schottky junctions touched electrode constitute by from top to bottom the 2nd Ni layer and Al layer successively; The thickness of said the 2nd Ni layer is 50nm～500nm, and the thickness of said Al layer is 1000nm～5000nm.
The present invention provides also that a kind of technological process is simple, the method for the above-mentioned JFET of manufacturing that is easy to realize and realize that cost is low, it is characterized in that this method may further comprise the steps:
Step 1, substrate is provided, said substrate is made up of N type SiC substrate;
Step 5, adopt electron beam evaporated metal Ni and Pt successively on the top of the bottom of said substrate and said N type SiC channel layer, and at N
2Carry out temperature under the atmosphere and be 950 ℃～1050 ℃ thermal annealing 2 minutes; The drain electrode Ohm contact electrode that is made up of a Ni layer and Pt layer is formed at the bottom at said substrate, and forms the source electrode Ohm contact electrode that is made up of a Ni layer and Pt layer on the top of said N type SiC ohmic contact layer; Wherein, the thickness of a said Ni layer is 200nm～400nm, and the thickness of said Pt layer is 50nm～200nm;
Step 6, on a side sidewall of upper lateral part of said SiC drift layer and said N type SiC channel layer splash-proofing sputtering metal Ni and Al successively; The first grid schottky junctions touched electrode that formation is made up of the 2nd Ni layer and Al layer; Splash-proofing sputtering metal Ni and Al on the opposite side sidewall of the opposite side top of said SiC drift layer and said N type SiC channel layer form the second grid schottky junctions touched electrode that is made up of the 2nd Ni layer and Al layer; Wherein, the thickness of said the 2nd Ni layer is 50nm～500nm, and the thickness of said Al layer is 1000nm～5000nm.
The present invention provides also that a kind of compact conformation, switching characteristic are good, the miniature inverter of high efficiency, electric energy loss is low and functional reliability the is high above-mentioned JFET of use; It is characterized in that: comprise the capacitor C 1, C2 and the C3 that are used for filtering; The inductance L 1 that is used to boost; Be used for JFET1, JFET2 and the JFET3 of on-off action, and the silicon carbide schottky diode D1, D2, D3 and the D4 that have been used for rectification and afterflow effect; One end of said capacitor C 1 an and end of inductance L 1 joins and be the dc voltage electrode input V+ of said miniature inverter; The positive pole of the negative pole of the other end of said inductance L 1 and the drain electrode of JFET1, silicon carbide schottky diode D1 and silicon carbide schottky diode D2 joins; The drain electrode of the negative pole of said silicon carbide schottky diode D2 and an end of capacitor C 2, JFET2 and the negative pole of silicon carbide schottky diode D3 join; One end of the other end of said capacitor C 2 and capacitor C 3 joins and is an ac voltage output OUT1 of said miniature inverter; The negative pole of the positive pole of the source electrode of said JFET2 and silicon carbide schottky diode D3, the drain electrode of JFET3 and silicon carbide schottky diode D4 joins and is another ac voltage output OUT2 of said miniature inverter; The source electrode of the positive pole of the other end of said capacitor C 1 and the source electrode of JFET1, silicon carbide schottky diode D1, the other end of capacitor C 3, JFET3 and the positive pole of silicon carbide schottky diode D4 join and are the direct voltage negative input V-of said miniature inverter, and the grid of the grid of said JFET1, the grid of JFET2 and JFET3 all joins with the output of inverter control circuit.
The present invention compared with prior art has the following advantages:
1, the JFET among the present invention is processed by the SiC material, has effectively utilized the good characteristic of SiC material, and is simple in structure, volume is little, convenient processing and manufacture and electrology characteristic are good.
2, the manufacturing approach of JFET among the present invention; The ion that the simple ripe schottky junctions touched electrode of adopting process has substituted the loaded down with trivial details difficulty of technology injects the grid of formation PN junction as JFET; Avoided repeatedly energetic ion to inject and high-temperature annealing process; Simplified device preparation technology, reduced the lens lesion that ion implantation technology is brought, and reduced cost.
3, use the miniature inverter of JFET among the present invention, adopted the topological structure of DC/DC/AC, with the decreased number of JFET to three; Do not adopt transformer; Simplified the structure of miniature inverter as much as possible, made that miniature inverter structure of the present invention is compact, advantages of small volume.
4, the present invention adopts the grid of schottky junctions touched electrode as JFET, can be with comparatively the technology of ripe silicon carbide schottky diode is compatible mutually at present; Inject preparation P+ district than ion, the preparation technology of schottky junctions touched electrode is ripe relatively, and these characteristics help reducing the cost of JFET and the cost of miniature inverter, also helps integratedly, reduces the volume of miniature inverter, raising packaging density.
5, than PN junction gate, the width that Schottky gate can the attenuate raceway groove helps improving the power density of JFET, reduces the electric energy loss of miniature inverter, reduces electricity price.
6, the schottky junctions touched electrode has the transient response better than PN junction, therefore adopts the JFET of schottky junctions touched electrode to have better switching characteristic, helps improving miniature inverter operating frequency, and reduced volume improves the reliability of work.
7, of the present invention practical, can be widely used in the solar energy power generating field, application value is high.
In sum, novel and reasonable design of the present invention, realization is convenient and realize that cost is low, helps improving miniature inverter operating frequency and functional reliability, reduces electric energy loss and electricity price, and practical, application value is high.
Through accompanying drawing and embodiment, technical scheme of the present invention is done further detailed description below.
Description of drawings
Fig. 1 is the structural representation of JFET of the present invention.
Fig. 2 is the method flow diagram of the manufacturing approach of JFET of the present invention.
Fig. 3 a is the structural representation of JFET when step 2 is accomplished in the various embodiments of the present invention.
Fig. 3 b is the structural representation of JFET when step 3 is accomplished in the various embodiments of the present invention.
Fig. 3 c is the structural representation of JFET when step 4 is accomplished in the various embodiments of the present invention.
Fig. 3 d is the structural representation of JFET when step 5 is accomplished in the various embodiments of the present invention.
Fig. 4 is the circuit theory diagrams of the miniature inverter of the present invention.
Description of reference numerals:
Embodiment
As shown in Figure 1; JFET of the present invention; Comprise the substrate 2 that constitutes by N type SiC substrate and be arranged on the SiC epitaxial loayer 3 on said substrate 2 upper surfaces; The first half of said SiC epitaxial loayer 3 is step-like and is the N type SiC channel layer 3-1 of said JFET; The latter half of said SiC epitaxial loayer 3 is the SiC drift layer 3-2 of said JFET; The top of said N type SiC channel layer 3-1 is provided with N type SiC ohmic contact layer 4, and the bottom of said substrate 2 is provided with drain electrode Ohm contact electrode 1, and the top of said N type SiC ohmic contact layer 4 is provided with source electrode Ohm contact electrode 5; The side sidewall of the upper lateral part of said SiC drift layer 3-2 and said N type SiC channel layer 3-1 is provided with first grid schottky junctions touched electrode 6-1, and the opposite side sidewall of the opposite side top of said SiC drift layer 3-2 and said N type SiC channel layer 3-1 is provided with second grid schottky junctions touched electrode 6-2.
Wherein, the thickness of said SiC epitaxial loayer 3 is 5 μ m～20 μ m; The width of said N type SiC channel layer 3-1 is that 0.5 μ m～2 μ m, thickness are 1 μ m～3 μ m.Said drain electrode Ohm contact electrode 1 and source electrode Ohm contact electrode 5 are by from top to bottom a Ni layer and Pt layer formation successively, and the thickness of a said Ni layer is 200nm～400nm, and the thickness of said Pt layer is 50nm～200nm.Said first grid schottky junctions touched electrode 6-1 and said second grid schottky junctions touched electrode 6-2 constitute by from top to bottom the 2nd Ni layer and Al layer successively; The thickness of said the 2nd Ni layer is 50nm～500nm, and the thickness of said Al layer is 1000nm～5000nm.
Embodiment 1
In conjunction with Fig. 2, the manufacturing approach of JFET of the present invention may further comprise the steps:
Step 1, substrate 2 is provided, said substrate is made up of N type SiC substrate;
Step 5, adopt electron beam evaporated metal Ni and Pt successively on the top of the bottom of said substrate 2 and said N type SiC channel layer 3-1, and at N
2Carry out temperature under the atmosphere and be 950 ℃ thermal annealing 2 minutes; The drain electrode Ohm contact electrode 1 that is made up of a Ni layer and Pt layer is formed at the bottom at said substrate 2, and forms the source electrode Ohm contact electrode 5 that is made up of a Ni layer and Pt layer on the top of said N type SiC ohmic contact layer 4; Wherein, the thickness of a said Ni layer is 200nm, and the thickness of said Pt layer is 50nm; The structural representation of JFET was shown in Fig. 3 d when step 5 was accomplished;
Step 6, on the side sidewall of the upper lateral part of said SiC drift layer 3-2 and said N type SiC channel layer 3-1 splash-proofing sputtering metal Ni and Al successively; The first grid schottky junctions touched electrode 6-1 that formation is made up of the 2nd Ni layer and Al layer; Splash-proofing sputtering metal Ni and Al on the opposite side sidewall of the opposite side top of said SiC drift layer 3-2 and said N type SiC channel layer 3-1 form the second grid schottky junctions touched electrode 6-2 that is made up of the 2nd Ni layer and Al layer; Wherein, the thickness of said the 2nd Ni layer is 50nm, and the thickness of said Al layer is 1000nm.
In the made JFET of above step, the thickness of said SiC epitaxial loayer 3 is 5 μ m; The width of said N type SiC channel layer 3-1 is that 0.5 μ m, thickness are 1 μ m.The thickness of a said Ni layer is 200nm, and the thickness of said Pt layer is 50nm.The thickness of said the 2nd Ni layer is 50nm, and the thickness of said Al layer is 1000nm.
What present embodiment and embodiment 1 were different is: adopt low pressure hot wall chemical vapor deposition method epitaxial growth doping content 12 * 10 on the upper surface of said substrate 2 in the step 2
16Cm
-3, thickness is the SiC epitaxial loayer 3 of 10 μ m; Adopt reactive ion dry etching method in the step 3 and adopt SF
6It is that 0.9 μ m, thickness are the step of 1.5 μ m that the plasma that gas produces etches width in the first half of said SiC epitaxial loayer 3; Adopt ion injection method to form doping content 3 * 10 in the step 4 on the top of said N type SiC channel layer 3-1
18Cm
-3N type SiC ohmic contact layer 4, and under Ar atmosphere, to carry out temperature be 1575 ℃ thermal annealing 10 minutes; Adopt electron beam evaporated metal Ni and Pt successively in the bottom of said substrate 2 and the top of said N type SiC channel layer 3-1 in the step 5, and at N
2Carry out temperature under the atmosphere and be 975 ℃ thermal annealing 2 minutes, the thickness of a said Ni layer is 250nm, and the thickness of said Pt layer is 90nm; The thickness of the 2nd Ni layer described in the step 6 is 160nm, and the thickness of said Al layer is 2000nm.All the other manufacturing approaches are all identical with embodiment 1.
In the made JFET of above step, the thickness of said SiC epitaxial loayer 3 is 10 μ m; The width of said N type SiC channel layer 3-1 is that 0.9 μ m, thickness are 1.5 μ m.The thickness of a said Ni layer is 250nm, and the thickness of said Pt layer is 90nm.The thickness of said the 2nd Ni layer is 275nm, and the thickness of said Al layer is 2000nm.
What present embodiment and embodiment 1 were different is: adopt low pressure hot wall chemical vapor deposition method epitaxial growth doping content 20 * 10 on the upper surface of said substrate 2 in the step 2
16Cm
-3, thickness is the SiC epitaxial loayer 3 of 15 μ m; Adopt reactive ion dry etching method in the step 3 and adopt SF
6It is that 1.25 μ m, thickness are the step of 2 μ m that the plasma that gas produces etches width in the first half of said SiC epitaxial loayer 3; Adopt ion injection method to form doping content 5 * 10 in the step 4 on the top of said N type SiC channel layer 3-1
18Cm
-3N type SiC ohmic contact layer 4, and under Ar atmosphere, to carry out temperature be 1600 ℃ thermal annealing 10 minutes; Adopt electron beam evaporated metal Ni and Pt successively in the bottom of said substrate 2 and the top of said N type SiC channel layer 3-1 in the step 5, and at N
2Carry out temperature under the atmosphere and be 1000 ℃ thermal annealing 2 minutes, the thickness of a said Ni layer is 300nm, and the thickness of said Pt layer is 125nm; The thickness of the 2nd Ni layer described in the step 6 is 275nm, and the thickness of said Al layer is 3000nm.All the other manufacturing approaches are all identical with embodiment 1.
In the made JFET of above step, the thickness of said SiC epitaxial loayer 3 is 15 μ m; The width of said N type SiC channel layer 3-1 is that 1.25 μ m, thickness are 2 μ m.The thickness of a said Ni layer is 300nm, and the thickness of said Pt layer is 125nm.The thickness of said the 2nd Ni layer is 275nm, and the thickness of said Al layer is 3000nm.
What present embodiment and embodiment 1 were different is: adopt low pressure hot wall chemical vapor deposition method epitaxial growth doping content 35 * 10 on the upper surface of said substrate 2 in the step 2
16Cm
-3, thickness is the SiC epitaxial loayer 3 of 18 μ m; Adopt reactive ion dry etching method in the step 3 and adopt SF
6It is that 1.6 μ m, thickness are the step of 2.5 μ m that the plasma that gas produces etches width in the first half of said SiC epitaxial loayer 3; Adopt ion injection method to form doping content 8 * 10 in the step 4 on the top of said N type SiC channel layer 3-1
18Cm
-3N type SiC ohmic contact layer 4, and under Ar atmosphere, to carry out temperature be 1625 ℃ thermal annealing 10 minutes; Adopt electron beam evaporated metal Ni and Pt successively in the bottom of said substrate 2 and the top of said N type SiC channel layer 3-1 in the step 5, and at N
2Carry out temperature under the atmosphere and be 1025 ℃ thermal annealing 2 minutes, the thickness of a said Ni layer is 350nm, and the thickness of said Pt layer is 170nm; The thickness of the 2nd Ni layer described in the step 6 is 370nm, and the thickness of said Al layer is 4000nm.All the other manufacturing approaches are all identical with embodiment 1.
In the made JFET of above step, the thickness of said SiC epitaxial loayer 3 is 18 μ m; The width of said N type SiC channel layer 3-1 is that 1.6 μ m, thickness are 2.5 μ m.The thickness of a said Ni layer is 350nm, and the thickness of said Pt layer is 170nm.The thickness of said the 2nd Ni layer is 370nm, and the thickness of said Al layer is 4000nm.
Embodiment 5
What present embodiment and embodiment 1 were different is: adopt low pressure hot wall chemical vapor deposition method epitaxial growth doping content 5 * 10 on the upper surface of said substrate 2 in the step 2
17Cm
-3, thickness is the SiC epitaxial loayer 3 of 20 μ m; Adopt reactive ion dry etching method in the step 3 and adopt SF
6It is that 2 μ m, thickness are the step of 3 μ m that the plasma that gas produces etches width in the first half of said SiC epitaxial loayer 3; Adopt ion injection method to form doping content 1 * 10 in the step 4 on the top of said N type SiC channel layer 3-1
19Cm
-3N type SiC ohmic contact layer 4, and under Ar atmosphere, to carry out temperature be 1650 ℃ thermal annealing 10 minutes; Adopt electron beam evaporated metal Ni and Pt successively in the bottom of said substrate 2 and the top of said N type SiC channel layer 3-1 in the step 5, and at N
2Carry out temperature under the atmosphere and be 1050 ℃ thermal annealing 2 minutes, the thickness of a said Ni layer is 400nm, and the thickness of said Pt layer is 200nm; The thickness of the 2nd Ni layer described in the step 6 is 500nm, and the thickness of said Al layer is 5000nm.All the other manufacturing approaches are all identical with embodiment 1.
In the made JFET of above step, the thickness of said SiC epitaxial loayer 3 is 20 μ m; The width of said N type SiC channel layer 3-1 is that 2 μ m, thickness are 3 μ m.The thickness of a said Ni layer is 400nm, and the thickness of said Pt layer is 200nm.The thickness of said the 2nd Ni layer is 500nm, and the thickness of said Al layer is 5000nm.
In conjunction with Fig. 4; A kind of miniature inverter that uses JFET according to the invention; Comprise the capacitor C 1, C2 and the C3 that are used for filtering; The inductance L 1 that is used to boost has been used for JFET1, JFET2 and the JFET3 of on-off action, and the silicon carbide schottky diode D1, D2, D3 and the D4 that have been used for rectification and afterflow effect; One end of said capacitor C 1 an and end of inductance L 1 joins and be the dc voltage electrode input V+ of said miniature inverter; The positive pole of the negative pole of the other end of said inductance L 1 and the drain electrode of JFET1, silicon carbide schottky diode D1 and silicon carbide schottky diode D2 joins; The drain electrode of the negative pole of said silicon carbide schottky diode D2 and an end of capacitor C 2, JFET2 and the negative pole of silicon carbide schottky diode D3 join; One end of the other end of said capacitor C 2 and capacitor C 3 joins and is an ac voltage output OUT1 of said miniature inverter; The negative pole of the positive pole of the source electrode of said JFET2 and silicon carbide schottky diode D3, the drain electrode of JFET3 and silicon carbide schottky diode D4 joins and is another ac voltage output OUT2 of said miniature inverter; The source electrode of the positive pole of the other end of said capacitor C 1 and the source electrode of JFET1, silicon carbide schottky diode D1, the other end of capacitor C 3, JFET3 and the positive pole of silicon carbide schottky diode D4 join and are the direct voltage negative input V-of said miniature inverter, and the grid of the grid of said JFET1, the grid of JFET2 and JFET3 all joins with the output of inverter control circuit 7.Said inverter control circuit 7 adopts inverter control circuit commonly known in the art to get final product.
Use the miniature inverter of JFET among the present invention, adopted the topological structure of DC/DC/AC, the decreased number of JFET to three, is not adopted transformer, compact conformation; Adopt the grid of schottky junctions touched electrode as JFET, can be with comparatively the technology of ripe silicon carbide schottky diode be compatible mutually at present; Help reducing the cost of JFET and the cost of miniature inverter, also help integratedly, reduce the volume of miniature inverter, improve packaging density, and can reduce the electric energy loss of miniature inverter, the reduction electricity price.
The above; It only is preferred embodiment of the present invention; Be not that the present invention is done any restriction, every technical spirit changes any simple modification, change and the equivalent structure that above embodiment did according to the present invention, all still belongs in the protection range of technical scheme of the present invention.
Claims (6)
1. JFET; It is characterized in that: comprise the substrate (2) that constitutes by N type SiC substrate and be arranged on the SiC epitaxial loayer (3) on said substrate (2) upper surface; The first half of said SiC epitaxial loayer (3) is step-like and is the N type SiC channel layer (3-1) of said JFET; The latter half of said SiC epitaxial loayer (3) is the SiC drift layer (3-2) of said JFET; The top of said N type SiC channel layer (3-1) is provided with N type SiC ohmic contact layer (4); The bottom of said substrate (2) is provided with drain electrode Ohm contact electrode (1); The top of said N type SiC ohmic contact layer (4) is provided with source electrode Ohm contact electrode (5); One side sidewall of one upper lateral part of said SiC drift layer (3-2) and said N type SiC channel layer (3-1) is provided with first grid schottky junctions touched electrode (6-1), and the opposite side sidewall of the opposite side top of said SiC drift layer (3-2) and said N type SiC channel layer (3-1) is provided with second grid schottky junctions touched electrode (6-2).
2. according to the described JFET of claim 1, it is characterized in that: the thickness of said SiC epitaxial loayer (3) is 5 μ m～20 μ m; The width of said N type SiC channel layer (3-1) is that 0.5 μ m～2 μ m, thickness are 1 μ m～3 μ m.
3. according to the described JFET of claim 1; It is characterized in that: said drain electrode Ohm contact electrode (1) and source electrode Ohm contact electrode (5) constitute by from top to bottom a Ni layer and Pt layer successively; The thickness of a said Ni layer is 200nm～400nm, and the thickness of said Pt layer is 50nm～200nm.
4. according to the described JFET of claim 1; It is characterized in that: said first grid schottky junctions touched electrode (6-1) and said second grid schottky junctions touched electrode (6-2) constitute by from top to bottom the 2nd Ni layer and Al layer successively; The thickness of said the 2nd Ni layer is 50nm～500nm, and the thickness of said Al layer is 1000nm～5000nm.
5. make the method for JFET according to claim 1 for one kind, it is characterized in that this method may further comprise the steps:
Step 1, substrate (2) is provided, said substrate is made up of N type SiC substrate;
Step 2, employing low pressure hot wall chemical vapor deposition method epitaxial growth doping content on the upper surface of said substrate (2) are 5 * 10
16Cm
-3～5 * 10
17Cm
-3, thickness is the SiC epitaxial loayer (3) of 5 μ m～20 μ m, epitaxially grown temperature is 1570 ℃, epitaxially grown pressure is 100mbar, epitaxially grown gas is that volume ratio is the C of 2:1:4
3H
8, SiH
4And H
2Mist;
Step 3, employing reactive ion dry etching method also adopt SF
6It is that 0.5 μ m～2 μ m, thickness are the step of 1 μ m～3 μ m that the plasma that gas produces etches width in the first half of said SiC epitaxial loayer (3); Make the SiC epitaxial loayer (3) that is positioned at step part constitute the N type SiC channel layer (3-1) of said JFET, SiC epitaxial loayer (3) the latter half that is positioned at the step bottom constitutes the SiC drift layer (3-2) of said JFET;
Step 4, employing ion injection method form doping content 1 * 10 on the top of said N type SiC channel layer (3-1)
18Cm
-3～1 * 10
19Cm
-3N type SiC ohmic contact layer (4), and under Ar atmosphere, to carry out temperature be 1550 ℃～1650 ℃ thermal annealing 10 minutes;
Step 5, adopt electron beam evaporated metal Ni and Pt successively on the top of the bottom of said substrate (2) and said N type SiC channel layer (3-1), and at N
2Carry out temperature under the atmosphere and be 950 ℃～1050 ℃ thermal annealing 2 minutes; The drain electrode Ohm contact electrode (1) that is made up of a Ni layer and Pt layer is formed at the bottom at said substrate (2), and forms the source electrode Ohm contact electrode (5) that is made up of a Ni layer and Pt layer on the top of said N type SiC ohmic contact layer (4); Wherein, the thickness of a said Ni layer is 200nm～400nm, and the thickness of said Pt layer is 50nm～200nm;
Step 6, on a side sidewall of upper lateral part of said SiC drift layer (3-2) and said N type SiC channel layer (3-1) splash-proofing sputtering metal Ni and Al successively; The first grid schottky junctions touched electrode (6-1) that formation is made up of the 2nd Ni layer and Al layer; Splash-proofing sputtering metal Ni and Al on the opposite side sidewall of the opposite side top of said SiC drift layer (3-2) and said N type SiC channel layer (3-1) form the second grid schottky junctions touched electrode (6-2) that is made up of the 2nd Ni layer and Al layer; Wherein, the thickness of said the 2nd Ni layer is 50nm～500nm, and the thickness of said Al layer is 1000nm～5000nm.
6. one kind is used the miniature inverter of JFET according to claim 1; It is characterized in that: comprise the capacitor C 1, C2 and the C3 that are used for filtering; The inductance L 1 that is used to boost; Be used for JFET1, JFET2 and the JFET3 of on-off action, and the silicon carbide schottky diode D1, D2, D3 and the D4 that have been used for rectification and afterflow effect; One end of said capacitor C 1 an and end of inductance L 1 joins and be the dc voltage electrode input V+ of said miniature inverter; The positive pole of the negative pole of the other end of said inductance L 1 and the drain electrode of JFET1, silicon carbide schottky diode D1 and silicon carbide schottky diode D2 joins; The drain electrode of the negative pole of said silicon carbide schottky diode D2 and an end of capacitor C 2, JFET2 and the negative pole of silicon carbide schottky diode D3 join; One end of the other end of said capacitor C 2 and capacitor C 3 joins and is an ac voltage output OUT1 of said miniature inverter; The negative pole of the positive pole of the source electrode of said JFET2 and silicon carbide schottky diode D3, the drain electrode of JFET3 and silicon carbide schottky diode D4 joins and is another ac voltage output OUT2 of said miniature inverter; The source electrode of the positive pole of the other end of said capacitor C 1 and the source electrode of JFET1, silicon carbide schottky diode D1, the other end of capacitor C 3, JFET3 and the positive pole of silicon carbide schottky diode D4 join and are the direct voltage negative input V-of said miniature inverter, and the grid of the grid of said JFET1, the grid of JFET2 and JFET3 all joins with the output of inverter control circuit (7).
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