CN109509749A - A kind of unidirectional negative resistance TVS device and preparation method thereof using silicon-controlled Dual Gated and anode in short circuit structure - Google Patents
A kind of unidirectional negative resistance TVS device and preparation method thereof using silicon-controlled Dual Gated and anode in short circuit structure Download PDFInfo
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- CN109509749A CN109509749A CN201811283080.0A CN201811283080A CN109509749A CN 109509749 A CN109509749 A CN 109509749A CN 201811283080 A CN201811283080 A CN 201811283080A CN 109509749 A CN109509749 A CN 109509749A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 45
- 239000010703 silicon Substances 0.000 title claims abstract description 45
- 230000009977 dual effect Effects 0.000 title claims abstract description 44
- 238000002360 preparation method Methods 0.000 title abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000000463 material Substances 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 238000000605 extraction Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 30
- 235000012431 wafers Nutrition 0.000 claims description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000001039 wet etching Methods 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 4
- 229910019213 POCl3 Inorganic materials 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 230000002633 protecting effect Effects 0.000 abstract description 6
- 238000007599 discharging Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 17
- 230000000694 effects Effects 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- VMXJCRHCUWKQCB-UHFFFAOYSA-N NPNP Chemical group NPNP VMXJCRHCUWKQCB-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
Abstract
The invention discloses a kind of unidirectional negative resistance TVS devices and preparation method thereof using silicon-controlled Dual Gated and anode in short circuit structure, including a P type substrate material, there are n-type doping region and P-doped zone domain in P type substrate material front, and metal extraction is done in the positive n-type doping region of P type substrate material；There are n-type doping region and P-doped zone domain, the n-type doping region region Zhong YouP+ in the P type substrate material back side, and P-doped zone domain, P type substrate material, n-type doping region and the region P+ at the back side are done interconnection metal and drawn；In all or part of overleaf n-type doping region of the P+ regional location.Device architecture front of the invention carries out charge discharging resisting using NPN structure to the back side, has more outstanding performance for protection next stage OVP circuit；Back-to-front utilizes PPN parallel connection P+NPN structure, obtains the performance of preferably positive residual voltage, plays preferably protecting effect to rear end OVP circuit.
Description
Technical field
It is the present invention relates to technical field of semiconductors, in particular to a kind of to utilize silicon-controlled Dual Gated and anode in short circuit structure
Unidirectional negative resistance structure TVS (Transient Voltage Suppressors) device and preparation method thereof.
Background technique
With constantly increasing for all kinds of ESD circuit integrated levels, the line width of integrated circuit also reduces therewith.With electrostatic in circuit
Therefore transient overshoot voltage existing for electric discharge (ESD) or other forms is also easier to damage electronic device.Two-way TVS bis-
Pole pipe can release the surge pulse from data line both ends positive and negative anodes, so that it is various forms of to protect system to protect against
The impact of high voltage transient.And unidirectional TVS diode, when protecting positive surge, relatively two-way TVS diode effect can be poor, and
It is bad to the positive protecting effect of OVP (overvoltage protection IC) with ultralow residual voltage when protection negative sense surge, negative sense is protected
It works well.And conventional unidirectional negative resistance structure TVS diode, as shown in Figure 1, the positive protection with two-way TVS diode
The characteristics of effect, negative sense have the advantages that partially unidirectional TVS diode, but relative to unidirectional TVS diode residual voltage or mistake
Height, protecting effect are bad.In order to improve the above problem, this patent structure is on the basis of conventional unidirectional negative resistance structure TVS diode
On reverse geometry is improved, as shown in Fig. 2, in the case where guaranteeing that positive protecting effect is constant, to VF directional current
Channel carries out special designing, and opposite to scheme there was only IF1 electric current leakage path in A structure, the electric current that this patent structure increases IF2 is let out
Channel is put, so that negative sense has lower residual voltage when by surge impact, reaches guarantor identical with conventional unidirectionally TVS diode
Effect is protected, protection OVP circuit is particularly suitable for, with very good positive and negative two-way overvoltage protection effect.
Summary of the invention
It is an object of the invention to solve above-mentioned deficiency in the prior art, provide a kind of using silicon-controlled Dual Gated and positive
Unidirectional negative resistance TVS device of extremely short line structure and preparation method thereof.
In order to solve the above technical problems, the technical solution adopted by the present invention is that:
A kind of unidirectional negative resistance TVS device using silicon-controlled Dual Gated and anode in short circuit structure, which is characterized in that its feature
It is, including a P type substrate material, there are n-type doping region and P-doped zone domain, P type substrate material in P type substrate material front
Expect that metal extraction is done in positive n-type doping region；There are n-type doping region and P-doped zone domain, N-type in the P type substrate material back side
There is the region P+ in doped region, interconnection gold is done in P-doped zone domain, P type substrate material, n-type doping region and the region P+ at the back side
Belong to and drawing；The P+ regional location can be completely or partially overleaf in n-type doping region.
The above-mentioned preparation method using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure includes following
Step:
Step (1): oxide layer is grown simultaneously in P type substrate material wafers piece front and back；
Step (2): n-type doping regional window is outputed in wafer front and back oxide layer；
Step (3): the oxide layer in removal wafer front and back n-type doping regional window；
Step (4): two-sided N-type element doping is carried out with the mode of diffusing, doping；
Step (5): P-doped zone domain window is outputed in wafer front and back oxide layer；
Step (6): the oxide layer in removal front and back P-doped zone domain window；
Step (7): two-sided p-type element doping is carried out with the mode of diffusing, doping；
Step (8): high temperature pushes away trap；
Step (9): P+ regional window is outputed in the oxide layer at the P type substrate material wafers piece back side；
Step (10): the oxide layer in removal back side P+ regional window；
Step (11): back side face p-type element doping is carried out with the mode of diffusing, doping；
Step (12): high temperature pushes away trap；
Step (13): it in wafer front n-type doping region opening contact hole window, connects the wafer back side is fully open
Contact hole；
Step (14): the oxide layer of removal front and back contact hole regional window；
Step (15): the contact bore region of front and back does metal line extraction.
Preferably, in step (1), P type substrate resistivity is 0.1~1 Ω CM, thickness 180-220um, the oxidation of growth
Layer thickness range is 0.5~2 μm.
Preferably, step (2), (5), exposure mask outputs doped region window with photoresist in (9)；Step (4), (7), (11)
In, photoresist is first removed, is then diffused doping again；Phosphorus diffusion doping is carried out in step (4), using POCl3Technique, temperature
Range is 950~1100 DEG C, the time 1~3 hour；Step (7) carries out boron diffusing, doping in (11), and temperature range is 950~
1150 DEG C, the time 1~3 hour.
Preferably, step (3), (6), the oxide layer in doped region window is gone with the method for wet etching in (10)
It removes.
Preferably, the process conditions of trap are pushed away in step (8) are as follows: 1150~1250 DEG C of temperature range, push away the trap time 48~96
Hour, 25~35 μm of junction depth range.
Preferably, the process conditions of trap are pushed away in step (12) are as follows: 1150~1250 DEG C of temperature range, push away the trap time 24~48
Hour, 10~20 μm of junction depth range.
In step (13), in wafer front mask with photoresist, contact hole window is only outputed on n-type doping region；
Without photoresist mask, the back side is fully open at the back side.
In step (14), the oxide layer of oxide layer and back side exposing in front window is gone with the method for wet etching
It removes.
In step (15), wafer front metal only draws n-type doping region；Back metal does whole face wiring, while by N
Type doped region, P-doped zone domain and the region P+ are drawn.
The beneficial effects of the present invention are: the unidirectional negative resistance of the invention using silicon-controlled Dual Gated and anode in short circuit structure
TVS device uses P type substrate material piece, is spread simultaneously using two-sided, forms N+/P substrate/N+/P+ structure, forms silicon-controlled knot
Structure；It is adulterated using back side N-type heavy doping, P heavy doping and P+, forms respectively silicon-controlled two gate poles and grid, pass through gold
Belong to and silicon-controlled Dual Gated is all guided into the back side, and connect with anode, forms silicon-controlled Dual Gated and anode in short circuit structure, i.e., simultaneously
PN diode, NPN structure and the PNPN structure of connection, obtain unidirectional negative resistance TVS device, which has protection OVP circuit
More outstanding performance: outstanding positive surge protection ability can be both provided, while outstanding reverse surge can also be provided
Protective capability；PNPN structure is capable of providing bigger through-current capability and lower residual voltage on triggering, to the negative sense mistake of IC new film
Pressure impact has more reliable protecting effect.Power consumption and heat dissipation advantage of the ultralow leakage current of the NPN+NPNP structure to device itself
Obviously.
Detailed description of the invention
Fig. 1 is conventional unidirectional negative resistance TVS cross-sectional view of the structure and VF directional current IF access diagram.
Fig. 2 is that Dual Gated is shown with the unidirectional negative resistance TVS cross-sectional view of the structure of anode in short circuit and the channel VF directional current IF1 and IF2
It is intended to.
Fig. 3, Fig. 4 are a kind of circuit knots using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
Composition.
Fig. 5 is preparation method of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of step (1).
Fig. 6, Fig. 7 are preparation of the present invention using the unidirectional negative resistance TVS device of silicon-controlled Dual Gated and anode in short circuit structure
The status diagram of method and step (2).
Fig. 8 is preparation method of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of step (3).
Fig. 9 is preparation method of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of step (4).
Figure 10, Figure 11 are system of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of Preparation Method step (5).
Figure 12 is preparation method of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of step (6).
Figure 13 is preparation method of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of step (7).
Figure 14 is preparation method of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of step (8).
Figure 15 is preparation method of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of step (9).
Figure 16 is preparation method of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of step (10).
Figure 17 is preparation method of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of step (11).
Figure 18 is preparation method of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of step (12).
Figure 19 is preparation method of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of step (13).
Figure 20 is preparation method of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of step (14).
Figure 21 is preparation method of the present invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
The status diagram of step (15).
Figure 22 is the unidirectional negative resistance TVS that another in the embodiment of the present invention utilizes silicon-controlled Dual Gated and anode in short circuit structure
Device architecture schematic diagram (back side region P+ part including n-type doping region, partially in P type substrate material).
Specific embodiment
Present pre-ferred embodiments are provided with reference to the accompanying drawing, in order to explain the technical scheme of the invention in detail.
It is the electricity of the invention using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure shown in Fig. 4
Line structure figure.
Embodiment 1:
Unidirectional negative resistance TVS device structure such as Figure 18 institute using silicon-controlled Dual Gated and anode in short circuit structure of the present embodiment
Showing, including a P type substrate material 22, P type substrate material front is equipped with N type doped region 31 and P-doped zone domain 32,
The P type substrate material back side is equipped with n-type doping region 31 and P-doped zone domain 32, and back side n-type doping region 31 is equipped with
The extraction of metal 41, the N at the P type substrate material back side are in the region P+ 33, the positive n-type doping region of P type substrate material
Type doped region, P-doped zone domain and the region P+ are done interconnection metal 41 and are drawn.
Its preparation process is as shown in Fig. 5-21:
Step (1): oxide layer 21 and oxide layer 23, temperature are grown simultaneously in 22 front and back of P type substrate material disk
1100-1200 DEG C, the time 6~8 hours, thickness 0.5-2um；
Step (2): 24 and 25 exposure masks output n-type doping region with photoresist in wafer front and back oxide layer
Window；
Step (3): with the oxidation in the method removal wafer front and back n-type doping regional window of wet etching
Layer；
Step (4): carrying out two-sided N-type element doping with the mode of diffusing, doping in boiler tube, specially progress phosphorus diffusion
Doping, using POCl3Technique, temperature range are 950~1100 DEG C, the time 1~3 hour；
Step (5): 26 and 27 exposure masks output P-doped zone domain with photoresist in wafer front and back oxide layer
Window；
Step (6): with the oxide layer in the method removal front and back P-doped zone domain window of wet etching；
Step (7): two-sided p-type element doping is carried out with the mode of diffusing, doping in boiler tube；Specially carry out boron diffusion
Doping, temperature range are 950~1150 DEG C, the time 1~3 hour；
Step (8): high temperature is carried out in boiler tube board and pushes away trap, process conditions are as follows: 1150~1250 DEG C of temperature range, is pushed away
The trap time 48~96 hours, 20~35 μm of junction depth range；
Step (9): exposure mask outputs P+ regional window with photoresist on wafer backside oxide layer；
Step (10): with the oxide layer in the method removal back side P+ regional window of wet etching；
Step (11): p-type element doping is carried out with the mode of diffusing, doping in boiler tube；Boron diffusion is specially carried out to mix
Miscellaneous, temperature range is 950~1150 DEG C, the time 1~3 hour；
Step (12): high temperature is carried out in boiler tube board and pushes away trap, process conditions are as follows: 1150~1250 DEG C of temperature range, is pushed away
The trap time 24~48 hours, 10~20 μm of junction depth range；
Step (13): in wafer front 28 mask with photoresist, only outputing contact hole window on n-type doping region,
To the wafer back side without photoresist mask, i.e. the back side is fully open；
Step (14): with the oxide layer of oxide layer and back side exposing in the method removal front window of wet etching；
Step (15): n-type doping region is only drawn in the wiring of wafer front metal；Whole face metal line is done at the back side, simultaneously
N-doped zone, P-doped zone domain and the region P+ are drawn.
Embodiment 2:
As shown in figure 22, the unidirectional negative resistance TVS device using silicon-controlled Dual Gated and anode in short circuit structure of the present embodiment
Structure difference from example 1 is that: the back side region P+ part is including n-type doping region, partially in P type substrate material
Material.Its preparation process is same as Example 1.
The present invention is elaborated above, but preferable embodiment described above, only of the invention, should not be limited
Determine the range that the present invention is implemented.That is, equivalent changes and modifications made by all application ranges according to the present invention etc., all should still belong to
In in patent covering scope of the invention.
Claims (13)
1. a kind of unidirectional negative resistance TVS device using silicon-controlled Dual Gated and anode in short circuit structure, which is characterized in that including one
There are n-type doping region and P-doped zone domain in P type substrate material, P type substrate material front, and the positive N-type of P type substrate material is mixed
Do metal extraction in miscellaneous region；There are n-type doping region and P-doped zone domain in the P type substrate material back side, and n-type doping has P+ in region
Region, P-doped zone domain, P type substrate material, n-type doping region and the region P+ at the P type substrate material back side are done interconnection metal and are drawn
Out；In all or part of overleaf n-type doping region of the P+ regional location.
2. the manufacturing method of the unidirectional negative resistance TVS device of silicon-controlled Dual Gated and anode in short circuit structure is utilized described in claim 1,
Characterized by comprising the following steps:
Step (1): oxide layer is grown simultaneously in P type substrate material wafers piece front and back；
Step (2): n-type doping regional window is outputed in wafer front and back oxide layer；
Step (3): the oxide layer in removal wafer front and back n-type doping regional window；
Step (4): two-sided N-type element doping is carried out with the mode of diffusing, doping；
Step (5): P-doped zone domain window is outputed in wafer front and back oxide layer；
Step (6): the oxide layer in removal front and back P-doped zone domain window；
Step (7): two-sided p-type element doping is carried out with the mode of diffusing, doping；
Step (8): high temperature pushes away trap；
Step (9): P+ regional window is outputed in the oxide layer at the P type substrate material wafers piece back side；
Step (10): the oxide layer in removal back side P+ regional window；
Step (11): back side face p-type element doping is carried out with the mode of diffusing, doping；
Step (12): high temperature pushes away trap；
Step (13): it in wafer front n-type doping region opening contact hole window, contacts the wafer back side is fully open
Hole；
Step (14): the oxide layer of removal front and back contact hole regional window；
Step (15): the contact bore region of front and back does metal line extraction.
3. the system according to claim 2 using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
Make method, it is characterised in that: in step (1), P type substrate resistivity be 0.1~1 Ω CM, thickness 180-220um, growth
Oxidated layer thickness range is 0.5~2 μm.
4. the system according to claim 2 using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
Make method, it is characterised in that: step (2), (5), exposure mask outputs doped region window with photoresist in (9).
5. the system according to claim 2 using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
Make method, it is characterised in that: step (3), (6), (10) middle wet etching method by front and back doped region window
Interior oxide layer removal.
6. the system according to claim 2 using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
Make method, it is characterised in that: step (4), in (11), first removes photoresist, then carries out elements diffusion doping again (7).
7. the system according to claim 6 using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
Make method, it is characterised in that: phosphorus diffusion doping is carried out in step (4), using POCl3 technique, temperature range is 950~1100
℃。
8. the system according to claim 6 using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
Make method, it is characterised in that: boron diffusing, doping is carried out in step (7), (11), temperature range is 950~1150 DEG C.
9. the system according to claim 2 using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
Make method, it is characterised in that: the process conditions of trap are pushed away in step (8) are as follows: 1150~1250 DEG C of temperature range, push away the trap time 12~
30 hours, 20~35 μm of junction depth range.
10. the system according to claim 2 using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
Make method, it is characterised in that: the process conditions of trap are pushed away in step (12) are as follows: 1150~1250 DEG C of temperature range, push away the trap time 6~
12 hours, 10~15 μm of junction depth range.
11. the system according to claim 2 using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
Make method, it is characterised in that: in step (13), in wafer front mask with photoresist, only output on N-type heavily doped region
Contact hole window；The back side is without photoresist mask, the i.e. fully open progress metal contact in the back side.
12. the system according to claim 2 using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
Make method, it is characterised in that: in step (14), with the method for wet etching by front window oxide layer and the back side expose
Oxide layer removal.
13. the system according to claim 2 using silicon-controlled Dual Gated and the unidirectional negative resistance TVS device of anode in short circuit structure
Make method, it is characterised in that: in step (15), wafer front metal only draws N-type heavily doped region；Back metal makees whole face cloth
Line, while N-type heavily doped region, p-type heavily doped region and the region P+ being drawn.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113270318A (en) * | 2021-05-27 | 2021-08-17 | 江苏晟驰微电子有限公司 | Manufacturing process of unidirectional negative resistance type TVS chip |
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| CN105226053A (en) * | 2014-06-26 | 2016-01-06 | 意法半导体(图尔)公司 | Overvoltage protection parts |
| CN104637997A (en) * | 2015-01-28 | 2015-05-20 | 电子科技大学 | Dual-mode reverse conducting gate commutated thyristor and manufacturing method thereof |
| CN108417613A (en) * | 2017-05-16 | 2018-08-17 | 上海长园维安微电子有限公司 | A kind of two-way TVS device and preparation method thereof with anti-paralleled diode |
| CN209119101U (en) * | 2018-10-31 | 2019-07-16 | 上海长园维安微电子有限公司 | A kind of unidirectional negative resistance TVS device using silicon-controlled Dual Gated and anode in short circuit structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113270318A (en) * | 2021-05-27 | 2021-08-17 | 江苏晟驰微电子有限公司 | Manufacturing process of unidirectional negative resistance type TVS chip |
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