CN111785717B - SCR electrostatic protection structure and forming method thereof - Google Patents

SCR electrostatic protection structure and forming method thereof Download PDF

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Publication number
CN111785717B
CN111785717B CN201910272299.9A CN201910272299A CN111785717B CN 111785717 B CN111785717 B CN 111785717B CN 201910272299 A CN201910272299 A CN 201910272299A CN 111785717 B CN111785717 B CN 111785717B
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doped region
well
type doped
type well
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CN111785717A (en
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杜飞波
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Abstract

An SCR electrostatic protection structure and a forming method thereof, the structure comprises: a first unit and a second unit; the first unit includes: the first P-type doped region is positioned at the top of the first N-type well; the first N-type doped region is positioned at the top of the first P-type well; the second unit includes: the second P-type doped region and the third N-type doped region are positioned at the top part in the second N-type well; the second N-type doped region and the third P-type doped region are positioned at the top part in the second P-type well; bridging the doping group; the bridging doping group includes: the fourth P-type doped regions are arranged along the second direction, are positioned at the top of part of the second N-type well and extend to the top of part of the second P-type well, and the second direction is perpendicular to the first direction; a fourth N-type doped region between adjacent fourth P-type doped regions; and the conductive structure is electrically connected with the fourth N-type doped region and the fourth P-type doped region. The performance of the SCR electrostatic protection structure is improved.

Description

SCR electrostatic protection structure and forming method thereof
Technical Field
The present disclosure relates to electrostatic protection, and more particularly, to an SCR electrostatic protection structure and a method for forming the same.
Background
In the fabrication and application of integrated circuit chips, with the continuous improvement of the process technology of ultra-large scale integrated circuits, the current CMOS integrated circuit fabrication technology has entered a deep submicron stage, the size of the MOS device is continuously reduced, the thickness of the gate oxide layer is thinner, the voltage endurance capability of the MOS device is obviously reduced, and the hazard of electrostatic discharge (Electrostatic Discharge, ESD) to the integrated circuit is more and more remarkable. Thus, ESD protection of integrated circuits becomes particularly important.
In order to enhance the capability of protecting static electricity, an electrostatic protection circuit is usually connected to an input/output interface (I/O pad) of a chip, where the electrostatic protection circuit is a discharging path for providing an electrostatic current to an internal circuit in the chip, so as to avoid the breakdown of the internal circuit of the chip by static electricity.
However, the existing electrostatic protection structure has poor performance.
Disclosure of Invention
The invention solves the problem of providing an SCR electrostatic protection structure and a forming method thereof, so as to improve the performance of the SCR electrostatic protection structure.
In order to solve the above problems, the present invention provides an SCR electrostatic protection structure, comprising: a semiconductor substrate; a first unit and a second unit which are separated and positioned in the semiconductor substrate; the first unit includes: a first N-type well and a first P-type well in the semiconductor substrate, the first P-type well being located at a side of the first N-type well along a first direction and being adjacent to the first N-type well; the first P-type doped region is positioned at the top of the first N-type well; the first N-type doped region is positioned at the top of the first P-type well; the second unit includes: the second P-type well is positioned at the side part of the second N-type well along the first direction and is adjacent to the second N-type well; the second P type doped region and the third N type doped region are positioned at the top of the second N type well and are separated from each other; the second N-type doped region and the third P-type doped region are positioned at the top of the second P-type well and are separated from each other; bridging the doping group; for the adjacent first unit and second unit, the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected; the set of crossover doping includes: a plurality of discrete fourth P-type doped regions arranged along the second direction, each fourth P-type doped region being located at the top of a portion of the second N-type well and extending to the top of a portion of the second P-type well, the second direction being perpendicular to the first direction; the fourth N-type doped region is positioned between the adjacent fourth P-type doped regions and is adjacent to the fourth P-type doped region, and the fourth N-type doped region is positioned at the top of part of the second N-type well and extends to the top of part of the second P-type well; and the conductive structure is positioned on the semiconductor substrate and electrically connected with the fourth N-type doped region and the fourth P-type doped region.
Optionally, the number of the second units is one; the second N-type doped region and the third P-type doped region are connected with cathode potential.
Optionally, the number of the second units is a plurality; the plurality of second units are respectively a first-stage second unit to a Q-th-stage second unit, and Q is an integer greater than or equal to 2; the second N-type doped region and the third P-type doped region in the ith second unit are electrically connected with the second P-type doped region and the third N-type doped region in the (i+1) th second unit, i is an integer greater than or equal to 1 and less than or equal to Q-1, the second N-type doped region and the third P-type doped region in the (Q) -th second unit are connected with cathode potentials, and the first N-type doped region is electrically connected with the second P-type doped region and the third N-type doped region in the first second unit.
Optionally, the first P-type doped region is connected to an anode potential.
Optionally, the first unit further includes: the fifth N-type doped region is positioned at the top of the first N-type well, the fifth N-type doped region and the first P-type doped region are mutually separated, and the fifth N-type doped region is electrically connected with the first P-type doped region.
Optionally, the first unit further includes: the fifth P-type doped region is positioned at the top of the first P-type well, the fifth P-type doped region and the first N-type doped region are mutually separated, and the fifth P-type doped region is electrically connected with the first N-type doped region.
Optionally, the first unit further includes: and a first isolation group layer in the semiconductor substrate between the first P-type doped region and the first N-type doped region, the first isolation group layer being located on top of a portion of the first N-type well and extending to top of a portion of the first P-type well.
Optionally, the first isolation group layer includes a sixth P-type doped region and first isolation insulation layers respectively located at two sides of the sixth P-type doped region along the first direction, the sixth P-type doped region is located at the top of part of the first N-type well and extends to the top of part of the first P-type well, the first isolation insulation layer at one side of the sixth P-type doped region is located in the first N-type well, and the first isolation insulation layer at the other side of the sixth P-type doped region is located in the first P-type well.
Optionally, the first isolation group layer has a single-layer structure, and the material of the first isolation group layer includes silicon oxide.
Optionally, the first unit further includes: a first side isolation well in the semiconductor substrate, the first side isolation well being located at a side of the first P-type well along a first direction and being adjacent to the first P-type well, the first P-type well being located between the first side isolation well and the first N-type well, the first side isolation well being of an N-type conductivity type; the first bottom isolation well is positioned at the bottom of the first P-type well and is adjacent to the first P-type well, the first bottom isolation well is also respectively connected with the bottom of the first N-type well and the bottom of the first side isolation well, and the conductivity type of the first bottom isolation well is N-type.
Optionally, the second unit further includes: the second side isolation well is positioned in the semiconductor substrate, is positioned at the side part of the second P-type well along the first direction and is adjacent to the second P-type well, the second P-type well is positioned between the second side isolation well and the second N-type well, and the conductivity type of the second side isolation well is N-type; the second bottom isolation well is positioned at the bottom of the second P-type well and is adjacent to the second P-type well, the second bottom isolation well is also connected with the bottom of the second N-type well and the bottom of the second side isolation well respectively, and the conductivity type of the second bottom isolation well is N-type.
Optionally, the method further comprises: and the seventh P-type doped regions are positioned at the top part of the semiconductor substrate, are respectively positioned between the adjacent first unit and the second unit and are respectively grounded at two sides of the second unit along the first direction.
Optionally, the conductive structure is located on the surface of the fourth N-type doped region and extends to the surface of the fourth P-type doped region; the conductive structure is made of metal silicide.
Optionally, the semiconductor substrate is provided with substrate trap ions, and the conductivity type of the substrate trap ions is P-type.
The invention also provides a method for forming the SCR electrostatic protection structure, which comprises the following steps: providing a semiconductor substrate; forming discrete first and second cells in a semiconductor substrate; the method of forming the first unit includes: forming a first N-type well in a semiconductor substrate; forming a first P-type well adjacent to the first N-type well at the side part of the first N-type well along the first direction; forming a first P-type doped region on top of the first N-type well; forming a first N-type doped region on top of the first P-type well; the method of forming the second unit includes: forming a second N-type well in the semiconductor substrate; forming a second P-type well adjacent to the second N-type well at the side part of the second N-type well along the first direction; forming a second P-type doped region and a third N-type doped region which are mutually separated on the top in the second N-type well; forming a second N-type doped region and a third P-type doped region which are mutually separated on the top in the second P-type well; forming a bridging doping group; for the adjacent first unit and second unit, the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected; the method for forming the bridging doping group comprises the following steps: forming a plurality of discrete fourth P-type doped regions arranged along a second direction, wherein each fourth P-type doped region is positioned at the top of part of the second N-type well and extends to the top of part of the second P-type well, and the second direction is perpendicular to the first direction; forming a fourth N-type doped region adjacent to the fourth P-type doped region between the adjacent fourth P-type doped regions, wherein the fourth N-type doped region is positioned at the top of part of the second N-type well and extends to the top of part of the second P-type well; and forming a conductive structure on the semiconductor substrate, wherein the conductive structure is electrically connected with the fourth N-type doped region and the fourth P-type doped region.
Optionally, the method of forming the first unit further comprises: forming a fifth N-type doped region positioned at the top of the first N-type well, wherein the fifth N-type doped region and the first P-type doped region are separated from each other, and the fifth N-type doped region is electrically connected with the first P-type doped region; and forming a fifth P-type doped region positioned at the top of the first P-type well, wherein the fifth P-type doped region and the first N-type doped region are mutually separated, and the fifth P-type doped region is electrically connected with the first N-type doped region.
Optionally, the method of forming the first unit further comprises: a first isolation group layer is formed in the semiconductor substrate between the first P-type doped region and the first N-type doped region, the first isolation group layer being located on top of a portion of the first N-type well and extending to top of a portion of the first P-type well.
Optionally, the method of forming the first unit further comprises: before forming the first P-type doped region and the first N-type doped region, forming a first side isolation well and a first bottom isolation well in the semiconductor substrate, wherein the first side isolation well is positioned on the side of the first P-type well along a first direction and is adjacent to the first P-type well, the first P-type well is positioned between the first side isolation well and the first N-type well, the first bottom isolation well is positioned at the bottom of the first P-type well and is adjacent to the first P-type well, the first bottom isolation well is also connected with the bottom of the first N-type well and the bottom of the first side isolation well respectively, and the conductivity types of the first side isolation well and the first bottom isolation well are N-type.
Optionally, the method of forming the second unit further comprises: before forming the second P-type doped region, the second N-type doped region, the third N-type doped region and the third P-type doped region, a second side isolation well and a second bottom isolation well are formed in the semiconductor substrate, the second side isolation well is located at the side part of the second P-type well along the first direction and is adjacent to the second P-type well, the second P-type well is located between the second side isolation well and the second N-type well, the second bottom isolation well is located at the bottom of the second P-type well and is adjacent to the second P-type well, the second bottom isolation well is also connected with the bottom of the second N-type well and the bottom of the second side isolation well respectively, and the conductivity types of the second side isolation well and the second bottom isolation well are N-type.
Optionally, the method further comprises: and forming a seventh P-type doped region on the top of part of the semiconductor substrate, wherein the seventh P-type doped region is respectively positioned between the adjacent first unit and the second unit and at two sides of the second unit along the first direction, and each seventh P-type doped region is grounded.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the SCR electrostatic protection structure provided by the technical scheme of the present invention, the SCR electrostatic protection structure includes a first current discharge structure and a second current discharge structure. The first current discharging structure is a PNPN structure, the first current discharging structure comprises a first PNP tube and a first NPN tube, the first P-type doped region is used as an emitter of the first PNP tube, the first N-type well at the bottom of the first P-type doped region is used as a base electrode of the first PNP tube, the first P-type well at the bottom of the first N-type doped region is used as a collector electrode of the first PNP tube, the first N-type well at the bottom of the first P-type doped region is used as a collector electrode of the first NPN tube, the first P-type well at the bottom of the first N-type doped region is used as a base electrode of the first NPN tube, and the first N-type doped region is used as an emitter electrode of the first NPN tube. The second current discharging structure is a PNPN structure, the second current discharging structure comprises a second PNP tube and a second NPN tube, the second P-type doped region is used as an emitter of the second PNP tube, the second N-type well at the bottom of the second P-type doped region is used as a base electrode of the second PNP tube, the second P-type well at the bottom of the second N-type doped region is used as a collector electrode of the second PNP tube, the second N-type well at the bottom of the second P-type doped region is used as a collector electrode of the second NPN tube, the second P-type well at the bottom of the second N-type doped region is used as a base electrode of the second NPN tube, and the second N-type doped region is used as an emitter of the second NPN tube. The second current drain structures in the second units of each stage are connected in series. The SCR electrostatic protection structure also comprises a resistance diversion structure, and the resistance diversion structure comprises: the third N-type doped region, the second N-type well, the bridging doped group, the second P-type well and the third P-type doped region. The first current drain path corresponds to the first current drain structure, and the second current drain path corresponds to the second current drain structure. The resistance water conservancy diversion structure has resistance water conservancy diversion route, and resistance water conservancy diversion route includes: the third N-type doped region is connected with the second N-type well, the second N-type well is connected with the fourth N-type doped region in the bridging doped group, the fourth N-type doped region is connected with the fourth P-type doped region through the conductive structure, the fourth P-type doped region is connected with the second P-type well, and the second P-type well is connected with the third P-type doped region. The resistive diversion paths in the second units of each stage are connected in series. The first current discharging path and the second current discharging path are overlapped in series, so that the holding voltage of the SCR electrostatic protection structure is increased, and the holding voltage of the SCR electrostatic protection structure is the sum of the holding voltage of the first current discharging structure and the holding voltage of the second current discharging structure, so that the holding voltage of the SCR electrostatic protection structure is increased. Since the holding voltage of the SCR electrostatic protection structure is increased, the range of the normal operating voltage of the semiconductor device is expanded for the semiconductor device protected by the SCR electrostatic protection structure. And applying trigger voltage to the cathode and the anode, wherein in the initial stage, a second current discharging path in the second unit is not conducted, a resistance diversion structure in the second unit is conducted, the voltage drop on the second unit is smaller, at the moment, most of the trigger voltage is applied to the first unit, and most of the trigger voltage is applied to the first unit to conduct a first current discharging path in the first unit, so that the first current discharging path is triggered to conduct, and then, the conduction of the first current discharging path triggers the conduction of the second current discharging path, so that the first current discharging path is triggered to conduct discharging. In this way, the trigger voltage required for triggering the conduction of the second current leakage path by the conduction of the first current leakage path in the SCR electrostatic protection structure is reduced. In conclusion, the performance of the SCR electrostatic protection structure is improved.
Drawings
Fig. 1 to 4 are schematic structural views illustrating a process of forming an SCR electrostatic protection structure according to an embodiment of the invention.
Detailed Description
As described in the background, the prior art forms semiconductor devices with poor performance.
There are two important parameters in the SCR electrostatic protection structure, namely the holding voltage and the trigger voltage. The higher holding voltage and lower trigger voltage are the process directions that SCR electrostatic protection structures are continually pursuing.
The existing SCR electrostatic protection structure includes: a P-type semiconductor substrate; an SCR unit located in the semiconductor substrate; the SCR unit includes: a first N-type well in the semiconductor substrate; the first P-type well is positioned in the first N-type well, is positioned on the side part of the first N-type well and is adjacent to the first N-type well; a second N-type well surrounding the first P-type well and the first N-type well; the P-type doped region is positioned at the top of the first N-type well; an N-type doped region located at the top of the first P-type well.
In order to increase the holding voltage of the SCR electrostatic protection structure, the SCR electrostatic protection structure generally has a plurality of SCR units, the plurality of SCR units are connected in series, specifically, the plurality of SCR units are a first-stage SCR unit to a W-stage SCR unit, W is an integer greater than or equal to 2, an N-type doped region in a j-stage SCR unit is electrically connected with a P-type doped region in a j+1st-stage SCR unit, j is an integer greater than or equal to 1 and less than or equal to W-1, the P-type doped region in the first-stage SCR unit is connected with an anode potential, and the N-type doped region in the W-stage SCR unit is connected with a cathode potential.
However, the above structure increases the trigger voltage of the SCR electrostatic protection structure while increasing the holding voltage.
On the basis, the invention provides an SCR electrostatic protection structure, which comprises the following components: a first cell and a second cell located in the semiconductor substrate; the first unit includes: a first N-type well and a first P-type well in the semiconductor substrate, the first P-type well being located at a side of the first N-type well along a first direction and being adjacent to the first N-type well; the first P-type doped region is positioned at the top of the first N-type well; the first N-type doped region is positioned at the top of the first P-type well; the second unit includes: the second P-type well is positioned at the side part of the second N-type well along the first direction and is adjacent to the second N-type well; the second P type doped region and the third N type doped region are positioned at the top of the second N type well and are separated from each other; the second N-type doped region and the third P-type doped region are positioned at the top of the second P-type well and are separated from each other; bridging the doping group; for the adjacent first unit and second unit, the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected; the set of crossover doping includes: a plurality of discrete fourth P-type doped regions arranged along the second direction, each fourth P-type doped region being located at the top of a portion of the second N-type well and extending to the top of a portion of the second P-type well, the second direction being perpendicular to the first direction; the fourth N-type doped region is positioned between the adjacent fourth P-type doped regions and is adjacent to the fourth P-type doped region; and the conductive structure is electrically connected with the fourth N-type doped region and the fourth P-type doped region. The performance of the SCR electrostatic protection structure is improved.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 to 4 are schematic structural views illustrating a process of forming an SCR electrostatic protection structure according to an embodiment of the invention.
Referring to fig. 1, a semiconductor substrate 200 is provided.
The semiconductor substrate 200 has therein substrate well ions, and the conductivity type of the substrate well ions is P-type.
The material of the semiconductor substrate 200 is monocrystalline silicon, monocrystalline germanium or monocrystalline silicon germanium.
The semiconductor substrate 200 includes a first cell region a and a second cell region B, which are separated from each other.
The number of the second unit areas B is one or more, and in this embodiment, the number of the second unit areas B is taken as a plurality as an example, and when the number of the second unit areas B is a plurality, the plurality of the second unit areas B are separated from each other.
The first cell areas a and the second cell areas B are arranged in the first direction X, and the plurality of second cell areas B are arranged in the first direction X.
Next, discrete first and second cells are formed in the semiconductor substrate 200. Specifically, a first cell is formed in the first cell region a, and a second cell is formed in the second cell region B.
In this embodiment, the number of the second unit areas B is plural, and correspondingly, the number of the second units is plural. In other embodiments, the number of second units is one.
The method of forming the first unit includes: forming a first N-type well in a semiconductor substrate; forming a first P-type well adjacent to the first N-type well at the side part of the first N-type well along the first direction; forming a first P-type doped region on top of the first N-type well; forming a first N-type doped region on top of the first P-type well;
the method of forming the second unit includes: forming a second N-type well in the semiconductor substrate; forming a second P-type well adjacent to the second N-type well at the side part of the second N-type well along the first direction; forming a second P-type doped region and a third N-type doped region which are mutually separated on the top in the second N-type well; forming a second N-type doped region and a third P-type doped region which are mutually separated on the top in the second P-type well; forming a bridging doping group; for adjacent first and second cells, the first N-doped region, the second P-doped region, and the third N-doped region are electrically connected.
Referring to fig. 2, a first N-type well 201 is formed in a semiconductor substrate 200; forming a first P-type well 202 adjacent to the first N-type well 201 at a side portion of the first N-type well 201 in the first direction X; forming a second N-type well 301 in the semiconductor substrate 200; a second P-type well 302 adjoining the second N-type well 301 is formed at a side portion of the second N-type well 301 in the first direction X.
The surface of the semiconductor substrate 200 exposes the first N-type well 201, the first P-type well 202, the second N-type well 301 and the second P-type well 302, that is, the top surface of the first N-type well 201 is flush with the surface of the semiconductor substrate 200, the top surface of the first P-type well 202 is flush with the surface of the semiconductor substrate 200, the top surface of the second N-type well 301 is flush with the surface of the semiconductor substrate 200, and the top surface of the second P-type well 302 is flush with the surface of the semiconductor substrate 200.
In this embodiment, referring to fig. 2, the method of forming the first unit further includes: a first side isolation well 203 and a first bottom isolation well 204 are formed in the semiconductor substrate 200, the first side isolation well 203 being located at a side of the first P-type well 202 along the first direction X and being adjacent to the first P-type well 202, the first P-type well 202 being located between the first side isolation well 203 and the first N-type well 201, the first bottom isolation well 204 being located at a bottom of the first P-type well 202 and being adjacent to the first P-type well 202, the first bottom isolation well 204 being further connected to a bottom of the first N-type well 201 and a bottom of the first side isolation well 203, respectively.
The first side isolation well 203 has an N-type conductivity, and the first bottom isolation well 204 has an N-type conductivity.
The first bottom isolation well 204 is located at the bottom of the first P-type well 202 and is adjacent to the first P-type well 202, and the first bottom isolation well 204 is also connected to the bottom of the first N-type well 201 and the bottom of the first side isolation well 203, respectively, such that the first bottom isolation well 204, the first N-type well 201, and the first side isolation well 203 enclose the first P-type well 202 such that the first P-type well 202 is isolated from the semiconductor substrate 200 at the bottom of the first bottom isolation well 204, such that the first P-type well 202 is isolated from the semiconductor substrate 200 at the side of the first side isolation well 203.
In this embodiment, referring to fig. 2, the method for forming the second unit further includes: a second side isolation well 303 and a second bottom isolation well 304 are formed in the semiconductor substrate 200, the second side isolation well 303 is located at a side of the second P-type well 302 along the first direction and is adjacent to the second P-type well 302, the second P-type well 302 is located between the second side isolation well 303 and the second N-type well 301, the second bottom isolation well 304 is located at a bottom of the second P-type well 302 and is adjacent to the second P-type well 302, and the second bottom isolation well 304 is also connected to a bottom of the second N-type well 301 and a bottom of the second side isolation well 303, respectively.
The second side isolation well 303 has an N-type conductivity, and the second bottom isolation well 304 has an N-type conductivity.
The second bottom isolation well 304 is located at the bottom of the second P-type well 302 and is adjacent to the second P-type well 302, and the second bottom isolation well 304 is also connected to the bottom of the second N-type well 301 and the bottom of the second side isolation well 303, respectively, such that the second bottom isolation well 304, the second N-type well 301, and the second side isolation well 303 enclose the second P-type well 302 such that the second P-type well 302 is isolated from the semiconductor substrate 200 at the bottom of the second bottom isolation well 304, such that the second P-type well 302 is isolated from the semiconductor substrate 200 at the side of the second side isolation well 303.
In this embodiment, the method of forming the first unit further includes: a first isolation insulating layer 510 and a second isolation insulating layer 520 are formed in the first cell region of the semiconductor substrate 200. In this embodiment, the first isolation insulating layer 510 is used to form a part of the subsequent first isolation group layer.
A portion of the second isolation insulating layer 520 is located in the first N-type well 201, a portion of the second isolation insulating layer 520 is located in the first P-type well 202, and a portion of the second isolation insulating layer 520 is located on top of the first side isolation well 203 and extends into a portion of the first P-type well 202.
In this embodiment, the method of forming the second unit further includes: a third isolation insulating layer 530 is formed in the second cell region of the semiconductor substrate 200.
A portion of the third isolation insulating layer 530 is located in the second N-type well 301, a portion of the third isolation insulating layer 530 is located in the second P-type well 302, and a portion of the third isolation insulating layer 530 is located on top of the second side isolation well 303 and extends into a portion of the second P-type well 302.
The material of the first isolation insulating layer 510 includes silicon oxide. The material of the second isolation insulating layer 520 includes silicon oxide. The material of the third isolation insulating layer 530 includes silicon oxide.
Referring to fig. 3, a first P-type doped region 210 is formed on top in the first N-type well 201; forming a first N-type doped region 220 on top of the first P-type well 202; forming a second P-type doped region 310 and a third N-type doped region 330 separated from each other on top in the second N-type well 301; forming a second N-type doped region 320 and a third P-type doped region 340 separated from each other on top in the second P-type well 302; forming a bridging doping group.
For adjacent first and second cells, the first N-type doped region 220, the second P-type doped region 310, and the third N-type doped region 330 are electrically connected.
The method for forming the bridging doping group comprises the following steps: forming a plurality of discrete fourth P-type doped regions 350 arranged along a second direction Y, each fourth P-type doped region 350 being located on top of a portion of the second N-type well 301 and extending to top of a portion of the second P-type well 302, the second direction Y being perpendicular to the first direction X; a fourth N-type doped region 360 is formed between adjacent fourth P-type doped regions 350 adjacent to the fourth P-type doped region 350, the fourth N-type doped region 360 being located on top of a portion of the second N-type well 301 and extending to top of a portion of the second P-type well 302.
The method of forming the first cell further comprises: a fifth N-type doped region 230 is formed on top of the first N-type well 201, the fifth N-type doped region 230 is separated from the first P-type doped region 210, and the fifth N-type doped region 230 is electrically connected to the first P-type doped region 210.
In this embodiment, the first P-type doped region 210 and the fifth N-type doped region 230 are both connected to the anode potential.
The method of forming the first cell further comprises: a fifth P-type doped region 240 is formed on top of the first P-type well 202, the fifth P-type doped region 240 is separated from the first N-type doped region 220, and the fifth P-type doped region 240 is electrically connected to the first N-type doped region 220.
In this embodiment, the method of forming the first unit further includes: a sixth P-type doped region 250 is formed in the semiconductor substrate 200, the sixth P-type doped region 250 being located on top of a portion of the first N-type well 201 and extending to top of a portion of the first P-type well 202.
In this embodiment, the first isolation insulating layers are respectively located at two sides of the sixth P-type doped region 250 in the first direction X, the first isolation insulating layer at one side of the sixth P-type doped region 250 is located in the first N-type well 201, and the first isolation insulating layer at the other side of the sixth P-type doped region 250 is located in the first P-type well 202.
In this embodiment, the first isolation insulating layer and the sixth P-type doped region 250 form a first isolation group layer, which is located in the semiconductor substrate 200 between the first P-type doped region 210 and the first N-type doped region 220, and which is located at the top of a portion of the first N-type well 201 and extends to the top of a portion of the first P-type well 202.
The concentration of P-type ions in the sixth P-type doped region 250 is much greater than the concentration of P-type ions in the first P-type well 202.
In other embodiments, the first isolation group layer is a single layer structure, the material of the first isolation group layer includes silicon oxide, the first isolation group layer is located in the semiconductor substrate between the first P-type doped region and the first N-type doped region, and the first isolation group layer is located at the top of a portion of the first N-type well and extends to the top of a portion of the first P-type well.
In this embodiment, the first P-type doped region 210, the first N-type doped region 220, the fifth N-type doped region 230, the fifth P-type doped region 240 and the sixth P-type doped region 250 are separated from each other, and the fifth P-type doped region 240, the first P-type doped region 210, the sixth P-type doped region 250, the first N-type doped region 220 and the fifth N-type doped region 230 are arranged along the first direction X.
In one embodiment, the first P-type doped region 210 is located between the fifth N-type doped region 230 and the first isolation group layer, and the first N-type doped region 220 is located between the fifth P-type doped region 240 and the first isolation group layer.
A second isolation insulating layer 520 is provided between the first P-type doped region 210 and the fifth N-type doped region 230, and between the first N-type doped region 220 and the fifth P-type doped region 240.
The second P-type doped region 310, the second N-type doped region 320, the third N-type doped region 330, the third P-type doped region 340 and the bridging doped group are discrete from one another.
In one specific embodiment, a second P-type doped region 310 is located between the set of crossover dopants and the third N-type doped region 330, and a second N-type doped region 320 is located between the set of crossover dopants and the third P-type doped region 340.
A third isolation insulating layer 530 is provided between the second P-type doped region 310 and the third N-type doped region 330, between the second P-type doped region 310 and the set of crossover doping, between the second N-type doped region 320 and the third P-type doped region 340, and between the second N-type doped region 320 and the set of crossover doping.
The concentration of P-type ions in the fourth P-type doped region 350 is greater than the concentration of P-type ions in the second P-type well 302. The concentration of N-type ions in the fourth N-type doped region 360 is greater than the concentration of N-type ions in the second N-type well 301.
For adjacent first and second cells, the first N-type doped region 220, the second P-type doped region 310, and the third N-type doped region 330 are electrically connected.
In this embodiment, taking the number of the second units as a plurality of examples, the plurality of second units are respectively a first-stage second unit to a Q-th-stage second unit, and Q is an integer greater than or equal to 2; the second N-type doped region 320 and the third P-type doped region 340 in the i-th level second cell are electrically connected with the second P-type doped region 310 and the third N-type doped region 330 in the i+1th level second cell, i is an integer greater than or equal to 1 and less than or equal to Q-1, the second N-type doped region 320 and the third P-type doped region 340 in the Q-th level second cell are connected with cathode potential, and the first N-type doped region is electrically connected with the second P-type doped region 310 and the third N-type doped region 330 in the first level second cell.
In this embodiment, Q is equal to 2, and the number of second units is two, and the plurality of second units are the first-stage second units to the second-stage second units, respectively.
In other embodiments, Q may be 3, 4, 5, 6, or an integer greater than or equal to 7.
In other embodiments, the number of the second units is one, and the second N-type doped region and the third P-type doped region are both connected to the cathode potential.
The formation method of the SCR electrostatic protection structure further comprises the following steps: a seventh P-type doped region 400 is formed on top of the portion of the semiconductor substrate 200, and the seventh P-type doped region 400 is respectively located between the adjacent first cell and second cell, and on both sides of the second cell along the first direction X, and each seventh P-type doped region 400 is grounded.
Each of the seventh P-type doped regions 400 is grounded to ground the semiconductor substrate 200, thereby avoiding latch-up.
In this embodiment, a second isolation insulating layer 520 is disposed between the seventh P-type doped region 400 and the fifth P-type doped region 240, and in particular, a second isolation insulating layer 520 is disposed between the seventh P-type doped region 400 and the fifth P-type doped region 240 in the first cell.
In this embodiment, a third isolation insulating layer 530 is disposed between the seventh P-type doped region 400 and the third N-type doped region 330. Specifically, a third isolation insulating layer 530 is provided between the seventh P-type doped region 400 between the first cell and the first-stage second cell and the third N-type doped region 330 in the first-stage second cell; a third isolation insulating layer 530 is provided between the seventh P-type doped region 400 between the i-th level second cell and the i+1-th level second cell and the third N-type doped region 330 in the i+1-th level second cell.
In this embodiment, a third isolation insulating layer 530 is disposed between the seventh P-type doped region 400 and the third P-type doped region 340, and in particular, a third isolation insulating layer 530 is disposed between the seventh P-type doped region 400 between the i-th level second cell and the i+1-th level second cell and the third P-type doped region 340 in the i-th level second cell.
Referring to fig. 4, a conductive structure 500 is formed on the semiconductor substrate 200, and the conductive structure 500 electrically connects the fourth N-type doped region and the fourth P-type doped region.
In this embodiment, the conductive structure 500 is located on the surface of the fourth N-type doped region and extends to the surface of the fourth P-type doped region; the material of the conductive structure 500 is metal silicide.
In other embodiments, the conductive structure comprises: the first metal silicide layer is positioned on the surface of the fourth N-type doped region; the second metal silicide layer is positioned on the surface of the fourth P-type doped region, and the first metal silicide layer and the second metal silicide layer are mutually separated; and the metal connecting layers are positioned on the first metal silicide layer and the second metal silicide layer and are respectively connected with the first metal silicide layer and the second metal silicide layer.
When the conductive structure 500 is located on the surface of the fourth N-type doped region and extends to the surface of the fourth P-type doped region, the conductive structure 500 is made of metal silicide, so that the structure of the conductive structure 500 is simpler and the manufacturing cost is reduced.
In this embodiment, the method further includes: the first connection layer is located on the semiconductor substrate, and the first connection layer is connected to the first P-type doped region 210 and the fifth N-type doped region 230, and the first connection layer is connected to the anode potential. The material of the first connection layer comprises a metal, such as copper or aluminum.
In this embodiment, the method further includes: and a second connection layer on the semiconductor substrate, the second connection layer being respectively connected to the fifth P-type doped region 240, the first N-type doped region 220, the second P-type doped region 310 and the third N-type doped region 330 in the first-level second cell, the material of the second connection layer being referred to the material of the first connection layer.
In this embodiment, the method further includes: and an i-th level connection layer on the semiconductor substrate, the i-th level connection layer connecting the second and third N-type doped regions 320 and 340 in the i-th level second cell and the second and third P-type doped regions 310 and 330 in the i+1-th level second cell, i being an integer of 1 or more and 1 or less. The material of the i-th level connection layer refers to the material of the first connection layer.
In this embodiment, the method further includes: and a third connection layer on the semiconductor substrate, the third connection layer connecting the second N-type doped region 320 and the third P-type doped region 340 in the Q-th level second cell, the third connection layer connecting the cathode potential. The material of the third connection layer refers to the material of the first connection layer.
In this embodiment, the method further includes: a fourth connection layer on the semiconductor substrate 200, the fourth connection layer connecting each of the seventh P-type doped regions 400, the material of the fourth connection layer being referenced to the material of the first connection layer.
The SCR electrostatic protection structure of the present embodiment includes a first current drain structure and a second current drain structure.
The first current discharging structure is a PNPN structure, the first current discharging structure comprises a first PNP tube and a first NPN tube, the first P-type doped region 210 is used as an emitter of the first PNP tube, the first N-type well 201 at the bottom of the first P-type doped region 210 is used as a base of the first PNP tube, the first P-type well 202 at the bottom of the first N-type doped region 220 is used as a collector of the first PNP tube, the first N-type well 201 at the bottom of the first P-type doped region 210 is used as a collector of the first NPN tube, the first P-type well 202 at the bottom of the first N-type doped region 220 is used as a base of the first NPN tube, and the first N-type doped region 220 is used as an emitter of the first NPN tube.
The second current discharging structure is a PNPN structure, the second current discharging structure comprises a second PNP tube and a second NPN tube, the second P-type doped region 310 is used as an emitter of the second PNP tube, the second N-type well 301 at the bottom of the second P-type doped region 310 is used as a base of the second PNP tube, the second P-type well 302 at the bottom of the second N-type doped region 320 is used as a collector of the second PNP tube, the second N-type well 301 at the bottom of the second P-type doped region 310 is used as a collector of the second NPN tube, the second P-type well 302 at the bottom of the second N-type doped region 320 is used as a base of the second NPN tube, and the second N-type doped region 320 is used as an emitter of the second NPN tube. The second current drain structures in the second units of each stage are connected in series.
The SCR electrostatic protection structure of this embodiment further includes a resistance flow guiding structure, the resistance flow guiding structure includes: a third N-type doped region 330, a second N-type well 301, a set of cross-over dopings, a second P-type well 302, and a third P-type doped region 340.
In the SCR electrostatic protection structure of this embodiment, a first current leakage path L1 and a second current leakage path L2 are provided, where the first current leakage path L1 corresponds to the first current leakage structure, and the second current leakage path L2 corresponds to the second current leakage structure. The resistance water conservancy diversion structure has resistance water conservancy diversion route L3, and resistance water conservancy diversion route L3 includes: from the third N-doped region 330 to the second N-well, from the second N-well to the fourth N-doped region 360 in the cross-over doping set, from the fourth N-doped region 360 through the conductive structure 500 to the fourth P-doped region 350, from the fourth P-doped region 350 to the second P-well 302, and from the second P-well 302 to the third P-doped region 340. The resistive diversion paths in the second units of each stage are connected in series.
In this embodiment, since the first current drain path L1 and the second current drain path L2 are superimposed in series, the holding voltage of the SCR electrostatic protection structure is increased, and the holding voltage of the SCR electrostatic protection structure is the sum of the holding voltage of the first current drain structure and the holding voltage of the second current drain structure, so that the holding voltage of the SCR electrostatic protection structure is increased. Since the holding voltage of the SCR electrostatic protection structure is increased, the range of the normal operating voltage of the semiconductor device is expanded for the semiconductor device protected by the SCR electrostatic protection structure.
In this embodiment, a trigger voltage is applied to the cathode and the anode, in an initial stage, the second current discharge path in the second unit is not conductive, the resistor diversion structure in the second unit is conductive, the voltage drop across the second unit is small, at this time, most of the trigger voltage is applied to the first unit, and most of the trigger voltage is applied to the first unit to make the first current discharge path in the first unit conductive, so as to trigger the first current discharge path to perform leakage. In this way, the trigger voltage required for triggering the conduction of the second current leakage path by the conduction of the first current leakage path in the SCR electrostatic protection structure is reduced.
Further, the concentration of P-type ions in the sixth P-type doped region 250 is much greater than that in the first P-type well 202, so that the breakdown voltage between the sixth P-type doped region 250 and the first N-type well 201 is lower, and the trigger voltage required for conducting the first current drain path L1 in the first cell is further reduced.
Correspondingly, the present embodiment further provides an SCR electrostatic protection structure, please refer to fig. 3 and fig. 4 in combination, including:
A semiconductor substrate 200;
a first cell and a second cell separated in the semiconductor substrate 200;
the first unit includes: a first N-type well 201 and a first P-type well 202 located in the semiconductor substrate 200, the first P-type well 202 being located at a side of the first N-type well 201 along the first direction X and being adjacent to the first N-type well 201; a first P-type doped region 210 located at the top of the first N-type well 201; a first N-type doped region 220 located at the top of the first P-type well 202;
the second unit includes: a second N-type well 301 and a second P-type well 302 located in the semiconductor substrate 200, the second P-type well 302 being located at a side of the second N-type well 301 along the first direction X and being adjacent to the second N-type well 301; a second P-type doped region 310 and a third N-type doped region 330 located on top of the second N-type well 301 and separated from each other; second N-type doped region 320 and third P-type doped region 340 are located on top of second P-type well 302 and are separated from each other; bridging the doping group; for adjacent first and second cells, the first N-type doped region 220, the second P-type doped region 310, and the third N-type doped region 330 are electrically connected;
the set of crossover doping includes: a plurality of discrete fourth P-type doped regions 350 arranged along a second direction Y, each fourth P-type doped region 350 being located on top of a portion of the second N-type well 301 and extending to top of a portion of the second P-type well 302, the second direction Y being perpendicular to the first direction X; a fourth N-type doped region 360 located between adjacent fourth P-type doped regions 350 and adjacent to the fourth P-type doped region 350, the fourth N-type doped region 360 being located on top of a portion of the second N-type well 301 and extending to top of a portion of the second P-type well 302;
The conductive structure 500 is located on the semiconductor substrate 200, and the conductive structure 500 electrically connects the fourth N-type doped region 360 and the fourth P-type doped region 350.
The semiconductor substrate 200 has therein substrate well ions, and the conductivity type of the substrate well ions is P-type.
In this embodiment, taking the number of the second units as a plurality of examples, the plurality of second units are respectively a first-stage second unit to a Q-th-stage second unit, and Q is an integer greater than or equal to 2; the second N-type doped region 320 and the third P-type doped region 340 in the i-th level second cell are electrically connected with the second P-type doped region 310 and the third N-type doped region 330 in the i+1th level second cell, i is an integer greater than or equal to 1 and less than or equal to Q-1, the second N-type doped region 320 and the third P-type doped region 340 in the Q-th level second cell are connected with cathode potential, and the first N-type doped region is electrically connected with the second P-type doped region 310 and the third N-type doped region 330 in the first level second cell.
In other embodiments, the number of the second units is one, and the second N-type doped region and the third P-type doped region are both connected to the cathode potential.
The first P-type doped region 210 and the fifth N-type doped region 230 are both connected to the anode potential.
The first unit further includes: the fifth N-doped region 230 is located on top of the first N-well 201, the fifth N-doped region 230 is separated from the first P-doped region 210, and the fifth N-doped region 230 is electrically connected to the first P-doped region 210.
The first unit further includes: the fifth P-type doped region 240 is located on top of the first P-type well 202, the fifth P-type doped region 240 is separated from the first N-type doped region 220, and the fifth P-type doped region 240 is electrically connected to the first N-type doped region 220.
The first unit further includes: a first isolation group layer in the semiconductor substrate 200 between the first P-type doped region 210 and the first N-type doped region 220, the first isolation group layer being located on top of a portion of the first N-type well 201 and extending to top of a portion of the first P-type well 202.
In this embodiment, the first isolation group layer includes a sixth P-type doped region 250 and first isolation insulating layers 510 respectively located at two sides of the sixth P-type doped region 250 along the first direction X, the sixth P-type doped region 250 is located at the top of a part of the first N-type well 201 and extends to the top of a part of the first P-type well 202, the first isolation insulating layers 510 at one side of the sixth P-type doped region 250 is located in the first N-type well 201, and the first isolation insulating layers 510 at the other side of the sixth P-type doped region are located in the first P-type well 202.
In other embodiments, the first isolation group layer is a single layer structure, and the material of the first isolation group layer includes silicon oxide.
The first unit further includes: a first side isolation well 203 located in the semiconductor substrate 200, the first side isolation well 203 being located at a side of the first P-type well 202 along the first direction X and being adjacent to the first P-type well 202, the first P-type well 202 being located between the first side isolation well 203 and the first N-type well 201, the first side isolation well being of an N-type conductivity; the first bottom isolation well 204, the first bottom isolation well 204 is located at the bottom of the first P-type well 202 and is adjacent to the first P-type well 202, the first bottom isolation well 204 is also connected to the bottom of the first N-type well 201 and the bottom of the first side isolation well 203, respectively, and the conductivity type of the first bottom isolation well is N-type.
The second unit further includes: a second side isolation well 303 in the semiconductor substrate 200, the second side isolation well 303 being located at a side of the second P-type well 302 along the first direction X and being adjacent to the second P-type well 302, the second P-type well 302 being located between the second side isolation well 303 and the second N-type well 301, the second side isolation well 303 being of an N-type conductivity; the second bottom isolation well 304, the second bottom isolation well 304 is located at the bottom of the second P-type well 302 and is adjacent to the second P-type well 302, the second bottom isolation well 304 is also connected to the bottom of the second N-type well 301 and the bottom of the second side isolation well 303, respectively, and the conductivity type of the second bottom isolation well 304 is N-type.
The SCR electrostatic protection structure further comprises: the seventh P-type doped region 400 is located at the top of the semiconductor substrate 200, and the seventh P-type doped region 400 is located between the adjacent first cell and second cell, and at two sides of the second cell along the first direction, and each seventh P-type doped region 400 is grounded.
In this embodiment, the conductive structure 500 is located on the surface of the fourth N-type doped region and extends to the surface of the fourth P-type doped region; the material of the conductive structure 500 is metal silicide.
In other embodiments, the conductive structure comprises: the first metal silicide layer is positioned on the surface of the fourth N-type doped region; the second metal silicide layer is positioned on the surface of the fourth P-type doped region, and the first metal silicide layer and the second metal silicide layer are mutually separated; and the metal connecting layers are positioned on the first metal silicide layer and the second metal silicide layer and are respectively connected with the first metal silicide layer and the second metal silicide layer.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. An SCR electrostatic protection structure, comprising:
a semiconductor substrate;
a first unit and a second unit which are separated and positioned in the semiconductor substrate;
the first unit includes: a first N-type well and a first P-type well in the semiconductor substrate, the first P-type well being located at a side of the first N-type well along a first direction and being adjacent to the first N-type well; the first P-type doped region is positioned at the top of the first N-type well; the first N-type doped region is positioned at the top of the first P-type well;
the second unit includes: the second P-type well is positioned at the side part of the second N-type well along the first direction and is adjacent to the second N-type well; the second P type doped region and the third N type doped region are positioned at the top of the second N type well and are separated from each other; the second N-type doped region and the third P-type doped region are positioned at the top of the second P-type well and are separated from each other; bridging the doping group; for the adjacent first unit and second unit, the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected;
The set of crossover doping includes: a plurality of discrete fourth P-type doped regions arranged along the second direction, each fourth P-type doped region being located at the top of a portion of the second N-type well and extending to the top of a portion of the second P-type well, the second direction being perpendicular to the first direction; the fourth N-type doped region is positioned between the adjacent fourth P-type doped regions and is adjacent to the fourth P-type doped region, and the fourth N-type doped region is positioned at the top of part of the second N-type well and extends to the top of part of the second P-type well;
and the conductive structure is positioned on the semiconductor substrate and electrically connected with the fourth N-type doped region and the fourth P-type doped region.
2. The SCR electrostatic protection structure according to claim 1, wherein the number of the second units is one; the second N-type doped region and the third P-type doped region are connected with cathode potential.
3. The SCR electrostatic protection structure according to claim 1, wherein the number of the second units is plural; the plurality of second units are respectively a first-stage second unit to a Q-th-stage second unit, and Q is an integer greater than or equal to 2; the second N-type doped region and the third P-type doped region in the ith second unit are electrically connected with the second P-type doped region and the third N-type doped region in the (i+1) th second unit, i is an integer greater than or equal to 1 and less than or equal to Q-1, the second N-type doped region and the third P-type doped region in the (Q) -th second unit are connected with cathode potentials, and the first N-type doped region is electrically connected with the second P-type doped region and the third N-type doped region in the first second unit.
4. The SCR electrostatic protection structure of claim 1, wherein the first P-doped region is connected to an anode potential.
5. The SCR electrostatic protection structure of claim 1, wherein the first unit further comprises: the fifth N-type doped region is positioned at the top of the first N-type well, the fifth N-type doped region and the first P-type doped region are mutually separated, and the fifth N-type doped region is electrically connected with the first P-type doped region.
6. The SCR electrostatic protection structure of claim 1, wherein the first unit further comprises: the fifth P-type doped region is positioned at the top of the first P-type well, the fifth P-type doped region and the first N-type doped region are mutually separated, and the fifth P-type doped region is electrically connected with the first N-type doped region.
7. The SCR electrostatic protection structure of claim 1, wherein the first unit further comprises: and a first isolation group layer in the semiconductor substrate between the first P-type doped region and the first N-type doped region, the first isolation group layer being located on top of a portion of the first N-type well and extending to top of a portion of the first P-type well.
8. The SCR electrostatic protection structure of claim 7, wherein the first isolation group layer comprises a sixth P-type doped region and first isolation insulating layers respectively located at two sides of the sixth P-type doped region along the first direction, the sixth P-type doped region is located at the top of a part of the first N-type well and extends to the top of a part of the first P-type well, the first isolation insulating layer at one side of the sixth P-type doped region is located in the first N-type well, and the first isolation insulating layer at the other side of the sixth P-type doped region is located in the first P-type well.
9. The SCR electrostatic protection structure of claim 7, wherein the first spacer layer is a single layer structure, and the material of the first spacer layer comprises silicon oxide.
10. The SCR electrostatic protection structure of claim 1, wherein the first unit further comprises: a first side isolation well in the semiconductor substrate, the first side isolation well being located at a side of the first P-type well along a first direction and being adjacent to the first P-type well, the first P-type well being located between the first side isolation well and the first N-type well, the first side isolation well being of an N-type conductivity type; the first bottom isolation well is positioned at the bottom of the first P-type well and is adjacent to the first P-type well, the first bottom isolation well is also respectively connected with the bottom of the first N-type well and the bottom of the first side isolation well, and the conductivity type of the first bottom isolation well is N-type.
11. The SCR electrostatic protection structure of claim 1, wherein the second unit further comprises: the second side isolation well is positioned in the semiconductor substrate, is positioned at the side part of the second P-type well along the first direction and is adjacent to the second P-type well, the second P-type well is positioned between the second side isolation well and the second N-type well, and the conductivity type of the second side isolation well is N-type; the second bottom isolation well is positioned at the bottom of the second P-type well and is adjacent to the second P-type well, the second bottom isolation well is also connected with the bottom of the second N-type well and the bottom of the second side isolation well respectively, and the conductivity type of the second bottom isolation well is N-type.
12. The SCR static electricity protection structure of claim 1, further comprising: and the seventh P-type doped regions are positioned at the top part of the semiconductor substrate, are respectively positioned between the adjacent first unit and the second unit and are respectively grounded at two sides of the second unit along the first direction.
13. The SCR electrostatic protection structure of claim 1, wherein the conductive structure is located on a surface of the fourth N-type doped region and extends to a surface of the fourth P-type doped region; the conductive structure is made of metal silicide.
14. The SCR electrostatic protection structure of claim 1, wherein the semiconductor substrate has substrate well ions therein, the substrate well ions having a P-type conductivity.
15. A method of forming the SCR electrostatic protection structure of any one of claims 1 to 14, comprising:
providing a semiconductor substrate;
forming discrete first and second cells in a semiconductor substrate;
the method of forming the first unit includes: forming a first N-type well in a semiconductor substrate; forming a first P-type well adjacent to the first N-type well at the side part of the first N-type well along the first direction; forming a first P-type doped region on top of the first N-type well; forming a first N-type doped region on top of the first P-type well;
The method of forming the second unit includes: forming a second N-type well in the semiconductor substrate; forming a second P-type well adjacent to the second N-type well at the side part of the second N-type well along the first direction; forming a second P-type doped region and a third N-type doped region which are mutually separated on the top in the second N-type well; forming a second N-type doped region and a third P-type doped region which are mutually separated on the top in the second P-type well; forming a bridging doping group; for the adjacent first unit and second unit, the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected;
the method for forming the bridging doping group comprises the following steps: forming a plurality of discrete fourth P-type doped regions arranged along a second direction, wherein each fourth P-type doped region is positioned at the top of part of the second N-type well and extends to the top of part of the second P-type well, and the second direction is perpendicular to the first direction; forming a fourth N-type doped region adjacent to the fourth P-type doped region between the adjacent fourth P-type doped regions, wherein the fourth N-type doped region is positioned at the top of part of the second N-type well and extends to the top of part of the second P-type well;
and forming a conductive structure on the semiconductor substrate, wherein the conductive structure is electrically connected with the fourth N-type doped region and the fourth P-type doped region.
16. The method of forming an SCR electrostatic protection structure of claim 15, wherein the method of forming the first cell further comprises: forming a fifth N-type doped region positioned at the top of the first N-type well, wherein the fifth N-type doped region and the first P-type doped region are separated from each other, and the fifth N-type doped region is electrically connected with the first P-type doped region; and forming a fifth P-type doped region positioned at the top of the first P-type well, wherein the fifth P-type doped region and the first N-type doped region are mutually separated, and the fifth P-type doped region is electrically connected with the first N-type doped region.
17. The method of forming an SCR electrostatic protection structure of claim 15, wherein the method of forming the first cell further comprises: a first isolation group layer is formed in the semiconductor substrate between the first P-type doped region and the first N-type doped region, the first isolation group layer being located on top of a portion of the first N-type well and extending to top of a portion of the first P-type well.
18. The method of forming an SCR electrostatic protection structure of claim 15, wherein the method of forming the first cell further comprises: before forming the first P-type doped region and the first N-type doped region, forming a first side isolation well and a first bottom isolation well in the semiconductor substrate, wherein the first side isolation well is positioned on the side of the first P-type well along a first direction and is adjacent to the first P-type well, the first P-type well is positioned between the first side isolation well and the first N-type well, the first bottom isolation well is positioned at the bottom of the first P-type well and is adjacent to the first P-type well, the first bottom isolation well is also connected with the bottom of the first N-type well and the bottom of the first side isolation well respectively, and the conductivity types of the first side isolation well and the first bottom isolation well are N-type.
19. The method of forming an SCR electrostatic protection structure according to claim 15, wherein the method of forming the second unit further comprises: before forming the second P-type doped region, the second N-type doped region, the third N-type doped region and the third P-type doped region, a second side isolation well and a second bottom isolation well are formed in the semiconductor substrate, the second side isolation well is located at the side part of the second P-type well along the first direction and is adjacent to the second P-type well, the second P-type well is located between the second side isolation well and the second N-type well, the second bottom isolation well is located at the bottom of the second P-type well and is adjacent to the second P-type well, the second bottom isolation well is also connected with the bottom of the second N-type well and the bottom of the second side isolation well respectively, and the conductivity types of the second side isolation well and the second bottom isolation well are N-type.
20. The method of forming an SCR electrostatic protection structure according to claim 15, further comprising: and forming a seventh P-type doped region on the top of part of the semiconductor substrate, wherein the seventh P-type doped region is respectively positioned between the adjacent first unit and the second unit and at two sides of the second unit along the first direction, and each seventh P-type doped region is grounded.
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