CN107346791A - The preparation method and transient voltage suppressor of transient voltage suppressor - Google Patents
The preparation method and transient voltage suppressor of transient voltage suppressor Download PDFInfo
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- CN107346791A CN107346791A CN201610299229.9A CN201610299229A CN107346791A CN 107346791 A CN107346791 A CN 107346791A CN 201610299229 A CN201610299229 A CN 201610299229A CN 107346791 A CN107346791 A CN 107346791A
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- 230000001052 transient effect Effects 0.000 title claims abstract description 36
- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 238000002347 injection Methods 0.000 claims abstract description 46
- 239000007924 injection Substances 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 238000002955 isolation Methods 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 150000002500 ions Chemical class 0.000 claims description 52
- 230000003647 oxidation Effects 0.000 claims description 33
- 238000007254 oxidation reaction Methods 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 238000009792 diffusion process Methods 0.000 claims description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 11
- -1 aluminium-silicon-copper Chemical compound 0.000 claims description 8
- 238000000407 epitaxy Methods 0.000 claims description 7
- 230000000873 masking effect Effects 0.000 claims description 7
- 239000002131 composite material Substances 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 5
- 230000005622 photoelectricity Effects 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 15
- 239000003990 capacitor Substances 0.000 abstract description 11
- 230000002441 reversible effect Effects 0.000 abstract description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000009776 industrial production Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000686 essence Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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Abstract
The invention provides a kind of preparation method of transient voltage suppressor and transient voltage suppressor, above-mentioned preparation method includes：P-type epitaxial layer is formed in N-type substrate, to complete the preparation of photodiode；Isolation channel is formed on the p-type epitaxial layer, the photodiode is divided as two photodiode units using each isolation channel；In the p-type epitaxial layer of the photodiode unit, p-type injection zone and N-type injection zone are sequentially formed, to form the Zener diode being connected in series with each photodiode；On the N-type substrate of the Zener diode is formed, front metal electrode and back metal electrode are formed.By technical scheme, the reverse characteristic of semiconductor devices is improved, influence degree of the voltage surge to integrated circuit is reduced, reduces additional capacitor, while improves the integrated and reliability of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, suppresses two poles in particular to a kind of transient voltage
The preparation method of pipe and a kind of transient voltage suppressor.
Background technology
Transient Voltage Suppressor (TVS, Transient Voltage Suppressors) is to be used to alleviate
Influence and damage of the voltage surge to integrated circuit, it has low clamp voltage, small volume, response
Hurry up, leakage current is small and high reliability, can be fast after TVS device on-load voltage surge
Quick access, which is received, absorbs surge current, by current reduction to normal level.
In correlation technique, in order to further improve the reverse characteristic of TVS device, generally in TVS
The predeterminable area setting protection structure such as partial pressure protection ring and Metal field plate structure of device, but above-mentioned guarantor
Protection structure introduces larger additional capacitor, and adds the area of TVS device, is unfavorable for device collection
Cheng Hua.
Therefore, how to design a kind of new transient voltage suppressor and its prepare scheme, with effective
Improve TVS device reverse characteristic and integrated turn into technical problem urgently to be resolved hurrily.
The content of the invention
The present invention is based at least one above-mentioned technical problem, it is proposed that a kind of new transient electrical is constrained
The preparation scheme of diode processed, by be upwardly formed in the Vertical Square of substrate series connection photodiode and
Zener diode, the reverse characteristic of semiconductor devices is improved, reduce voltage surge to integrated circuit
Influence degree, reduce additional capacitor, while improve the integrated and reliable of semiconductor devices
Property.
In view of this, the present invention proposes a kind of preparation method of transient voltage suppressor, wraps
Include：P-type epitaxial layer is formed in N-type substrate, to complete the preparation of photodiode；In the P
Isolation channel is formed on type epitaxial layer, the photodiode is divided as two light using each isolation channel
Electric diode unit；In the p-type epitaxial layer of the photodiode unit, p-type note is sequentially formed
Enter region and N-type injection zone, to form the Zener two being connected in series with each photodiode
Pole pipe；On the N-type substrate of the Zener diode is formed, front metal electrode and back-side gold are formed
Belong to electrode.
In the technical scheme, by be upwardly formed in the Vertical Square of substrate series connection photodiode and
Zener diode, the reverse characteristic of semiconductor devices is improved, reduce voltage surge to integrated circuit
Influence degree, reduce additional capacitor, while improve the integrated and reliable of semiconductor devices
Property.
Wherein, Zener diode has avalanche breakdown characteristic, is based on avalanche breakdown feature to eliminate
Voltage surge, on the one hand, the electric capacity of photodiode is much smaller than Zener diode, therefore, series connection
The total capacitance of photodiode and Zener diode is smaller, and this reduces additional capacitor, the opposing party
Face, Zener diode and photodiode are distributed in the vertical direction of substrate, improves the integrated of device
Change and reliability.
It is worth it is emphasized that by the formation of isolation channel, beneficial in the above-mentioned transient electrical of industrial production
Scribing processing is carried out during constraining diode processed, to form the TVS unit devices of high reliability
Part.
In the above-mentioned technical solutions, it is preferable that isolation channel is formed on the p-type epitaxial layer, with every
It is two photodiode units that the individual isolation channel, which divides the photodiode, is specifically included following
Step：Silicon oxide layer is formed on the p-type epitaxial layer；Outside to the silicon oxide layer and the p-type
Prolong untill layer is patterned and is etched to and cuts through, and continue to etch the N-type epitaxy layer to specified thickness
Degree, to form clearance hole；In the inwall of the clearance hole and bottom by ion diffusion technique, with shape
Into N-type diffusion region；Thermal oxidation is carried out to the N-type diffusion region, at the thermal oxide
The thermal oxide layer that reason is formed fills the clearance hole, to form the isolation channel.
In the technical scheme, clearance hole is filled by thermal oxidation technology, on the one hand, pass through to be formed
N-type epitaxy layer and p-type epitaxial layer carry out partial pressure, on the other hand, realized based on isolation channel more preferable
Scribing processing exactly, to improve the efficiency of volume production.
In any of the above-described technical scheme, it is preferable that form silica on the p-type epitaxial layer
Layer, specifically includes following steps：The p-type epitaxial layer is handled using thermal oxidation technology, with
Form silicon oxide masking film layer.
In any of the above-described technical scheme, it is preferable that form silica on the p-type epitaxial layer
Layer, specifically includes following steps：Using chemical vapor deposition method to the p-type epitaxial layer at
Reason, to form the silicon oxide masking film layer.
In the above-mentioned technical solutions, it is preferable that thermal oxidation is carried out to the N-type diffusion region, led to
Cross the thermal oxide layer that the thermal oxidation is formed and fill the clearance hole, to form the isolation channel,
Specifically include following steps：It is 900~1000 DEG C of thermal oxidation technology to the N to use temperature range
Type diffusion region carries out thermal oxidation, described in the thermal oxide layer filling formed by the thermal oxidation
Clearance hole, to form the isolation channel.
In any of the above-described technical scheme, it is preferable that outside the p-type of the photodiode unit
Prolong in layer, sequentially form p-type injection zone and N-type injection zone, to be formed and each light
The Zener diode that electric diode is connected in series, specifically includes following steps：To the p-type epitaxial layer
P-type ion implanting is carried out, the energy range of the p-type ion implanting is 40~100KeV, the P
The dosage range of type ion implanting is 10E15~10E20/cm2, to form the p-type doped region；It is right
The p-type doped region is made annealing treatment, to form the p-type injection zone；The p-type is noted
Enter region and carry out N-type ion implanting, the energy range of the N-type ion implanting is
40~100KeV, the dosage range of the N-type ion implanting is 10E15~10E20/cm2, to be formed
The n-type doping area；The n-type doping area is made annealing treatment, noted with forming the N-type
Enter region, and then form the Zener diode.
In any of the above-described technical scheme, it is preferable that outside the p-type of the photodiode unit
Prolong in layer, sequentially form p-type injection zone and N-type injection zone, to be formed and each light
The Zener diode that electric diode is connected in series, specifically includes following steps：To the p-type epitaxial layer
P-type ion implanting is carried out, the energy range of the p-type ion implanting is 40~100KeV, the P
The dosage range of type ion implanting is 10E15~10E20/cm2, to form the p-type doped region；It is right
The p-type doped region carries out N-type ion implanting, and the energy range of the N-type ion implanting is
40~100KeV, the dosage range of the N-type ion implanting is 10E15~10E20/cm2, to be formed
The n-type doping area；The p-type doped region and the n-type doping area are made annealing treatment,
To form the p-type injection zone and the N-type injection zone simultaneously, and then form the Zener
Diode.
In any of the above-described technical scheme, it is preferable that forming the N-type lining of the Zener diode
On bottom, front metal electrode and back metal electrode are formed, specifically includes following steps：Forming institute
In the N-type substrate for stating N-type injection zone, it is compound that front side aluminum-silicon-copper is formed using double-faced sputter technique
Metal level and back aluminium-silicon-copper composite metal layer, using as the front metal electrode and described
Back metal electrode.
In any of the above-described technical scheme, it is preferable that also include：Forming the front metal electricity
Behind pole and the back metal electrode, scribing processing is carried out in position corresponding to the isolation channel.
According to another aspect of the present invention, it is also proposed that a kind of transient voltage suppressor, using such as
The preparation method of transient voltage suppressor described in any of the above-described technical scheme is prepared.
By above technical scheme, by the photodiode that series connection is upwardly formed in the Vertical Square of substrate
And Zener diode, the reverse characteristic of semiconductor devices is improved, reduces voltage surge to integrated electricity
The influence degree on road, additional capacitor is reduced, while improve the integrated and reliable of semiconductor devices
Property.
Brief description of the drawings
Fig. 1 shows the preparation method of transient voltage suppressor according to an embodiment of the invention
Schematic flow diagram；
Fig. 2 to Fig. 7 shows the preparation of transient voltage suppressor according to an embodiment of the invention
The diagrammatic cross-section of scheme.
Embodiment
In order to be more clearly understood that the above objects, features and advantages of the present invention, with reference to attached
The present invention is further described in detail for figure and embodiment.It should be noted that not
In the case of conflict, the feature in embodiments herein and embodiment can be mutually combined.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still,
The present invention can also be different from other modes described here to implement using other, therefore, the present invention
Protection domain do not limited by following public specific embodiment.
Fig. 1 shows the preparation method of transient voltage suppressor according to an embodiment of the invention
Schematic flow diagram.
As shown in figure 1, the preparation side of transient voltage suppressor according to an embodiment of the invention
Method, including：Step 12, p-type epitaxial layer is formed in N-type substrate, to complete photodiode
Preparation；Step 14, isolation channel is formed on the p-type epitaxial layer, with each isolation channel
It is two photodiode units to divide the photodiode；Step 16, in the pole of photoelectricity two
In the p-type epitaxial layer of pipe unit, p-type injection zone and N-type injection zone are sequentially formed, with shape
Into the Zener diode being connected in series with each photodiode；Step 18, described in formation
In the N-type substrate of Zener diode, front metal electrode and back metal electrode are formed.
In the technical scheme, by be upwardly formed in the Vertical Square of substrate series connection photodiode and
Zener diode, the reverse characteristic of semiconductor devices is improved, reduce voltage surge to integrated circuit
Influence degree, reduce additional capacitor, while improve the integrated and reliable of semiconductor devices
Property.
Wherein, Zener diode has avalanche breakdown characteristic, is based on avalanche breakdown feature to eliminate
Voltage surge, on the one hand, the electric capacity of photodiode is much smaller than Zener diode, therefore, series connection
The total capacitance of photodiode and Zener diode is smaller, and this reduces additional capacitor, the opposing party
Face, Zener diode and photodiode are distributed in the vertical direction of substrate, improves the integrated of device
Change and reliability.
It is worth it is emphasized that by the formation of isolation channel, beneficial in the above-mentioned transient electrical of industrial production
Scribing processing is carried out during constraining diode processed, to form the TVS unit devices of high reliability
Part.
In the above-mentioned technical solutions, it is preferable that isolation channel is formed on the p-type epitaxial layer, with every
It is two photodiode units that the individual isolation channel, which divides the photodiode, is specifically included following
Step：Silicon oxide layer is formed on the p-type epitaxial layer；Outside to the silicon oxide layer and the p-type
Prolong untill layer is patterned and is etched to and cuts through, and continue to etch the N-type epitaxy layer to specified thickness
Degree, to form clearance hole；In the inwall of the clearance hole and bottom by ion diffusion technique, with shape
Into N-type diffusion region；Thermal oxidation is carried out to the N-type diffusion region, at the thermal oxide
The thermal oxide layer that reason is formed fills the clearance hole, to form the isolation channel.
In the technical scheme, clearance hole is filled by thermal oxidation technology, on the one hand, pass through to be formed
N-type epitaxy layer and p-type epitaxial layer carry out partial pressure, on the other hand, realized based on isolation channel more preferable
Scribing processing exactly, to improve the efficiency of volume production.
In any of the above-described technical scheme, it is preferable that form silica on the p-type epitaxial layer
Layer, specifically includes following steps：The p-type epitaxial layer is handled using thermal oxidation technology, with
Form silicon oxide masking film layer.
In any of the above-described technical scheme, it is preferable that form silica on the p-type epitaxial layer
Layer, specifically includes following steps：Using chemical vapor deposition method to the p-type epitaxial layer at
Reason, to form the silicon oxide masking film layer.
In the above-mentioned technical solutions, it is preferable that thermal oxidation is carried out to the N-type diffusion region, led to
Cross the thermal oxide layer that the thermal oxidation is formed and fill the clearance hole, to form the isolation channel,
Specifically include following steps：It is 900~1000 DEG C of thermal oxidation technology to the N to use temperature range
Type diffusion region carries out thermal oxidation, described in the thermal oxide layer filling formed by the thermal oxidation
Clearance hole, to form the isolation channel.
In any of the above-described technical scheme, it is preferable that outside the p-type of the photodiode unit
Prolong in layer, sequentially form p-type injection zone and N-type injection zone, to be formed and each light
The Zener diode that electric diode is connected in series, specifically includes following steps：To the p-type epitaxial layer
P-type ion implanting is carried out, the energy range of the p-type ion implanting is 40~100KeV, the P
The dosage range of type ion implanting is 10E15~10E20/cm2, to form the p-type doped region；It is right
The p-type doped region is made annealing treatment, to form the p-type injection zone；The p-type is noted
Enter region and carry out N-type ion implanting, the energy range of the N-type ion implanting is
40~100KeV, the dosage range of the N-type ion implanting is 10E15~10E20/cm2, to be formed
The n-type doping area；The n-type doping area is made annealing treatment, noted with forming the N-type
Enter region, and then form the Zener diode.
In any of the above-described technical scheme, it is preferable that outside the p-type of the photodiode unit
Prolong in layer, sequentially form p-type injection zone and N-type injection zone, to be formed and each light
The Zener diode that electric diode is connected in series, specifically includes following steps：To the p-type epitaxial layer
P-type ion implanting is carried out, the energy range of the p-type ion implanting is 40~100KeV, the P
The dosage range of type ion implanting is 10E15~10E20/cm2, to form the p-type doped region；It is right
The p-type doped region carries out N-type ion implanting, and the energy range of the N-type ion implanting is
40~100KeV, the dosage range of the N-type ion implanting is 10E15~10E20/cm2, to be formed
The n-type doping area；The p-type doped region and the n-type doping area are made annealing treatment,
To form the p-type injection zone and the N-type injection zone simultaneously, and then form the Zener
Diode.
In any of the above-described technical scheme, it is preferable that forming the N-type lining of the Zener diode
On bottom, front metal electrode and back metal electrode are formed, specifically includes following steps：Forming institute
In the N-type substrate for stating N-type injection zone, it is compound that front side aluminum-silicon-copper is formed using double-faced sputter technique
Metal level and back aluminium-silicon-copper composite metal layer, using as the front metal electrode and described
Back metal electrode.
In any of the above-described technical scheme, it is preferable that also include：Forming the front metal electricity
Behind pole and the back metal electrode, scribing processing is carried out in position corresponding to the isolation channel.
Fig. 2 to Fig. 7 shows the preparation of transient voltage suppressor according to an embodiment of the invention
The diagrammatic cross-section of scheme.
As shown in Figures 2 to 7, the system of transient voltage suppressor according to an embodiment of the invention
Preparation Method, including：As shown in Fig. 2 p-type epitaxial layer 102 is formed in N-type substrate 101, with
Complete photodiode 1A preparation；As shown in Figure 3 and Figure 4, in the p-type epitaxial layer 102
Upper formation isolation channel 108, the photodiode 1A is divided as two using each isolation channel 108
Individual photodiode unit；As shown in Fig. 5, Fig. 6 and Fig. 7, in the photodiode unit
In p-type epitaxial layer 102, p-type injection zone 103 and N-type injection zone 104 are sequentially formed, with
Form the Zener diode 1B being connected in series with each photodiode 1A；As shown in fig. 7,
On the N-type substrate 101 of the Zener diode 1B is formed, front metal electrode 105A is formed
With back metal electrode 105B.
In the technical scheme, by the photodiode that series connection is upwardly formed in the Vertical Square of substrate
1A and Zener diode 1B, improves the reverse characteristic of semiconductor devices, reduces voltage surge pair
The influence degree of integrated circuit, additional capacitor is reduced, while improve the integrated of semiconductor devices
And reliability.
Wherein, Zener diode 1B has avalanche breakdown characteristic, is based on avalanche breakdown feature
Eliminating voltage surge, on the one hand, photodiode 1A electric capacity is much smaller than Zener diode 1B, because
This, the photodiode 1A and Zener diode 1B of series connection total capacitance are smaller, this reduces
Additional capacitor, on the other hand, it is distributed Zener diode 1B and the pole of photoelectricity two in the vertical direction of substrate
Pipe 1A, improve the integrated and reliability of device.
It is worth it is emphasized that by the formation of isolation channel 108, beneficial in industrial production above-mentioned wink
Time variant voltage suppresses to carry out scribing processing during diode, to form the TVS units of high reliability
Device.
As shown in Figure 3 and Figure 4, isolation channel 108 is formed on the p-type epitaxial layer 102, with every
It is two photodiode 1A units that the individual isolation channel 108, which divides the photodiode 1A,
Specifically include following steps：As shown in figure 3, form silica on the p-type epitaxial layer 102
Layer；As shown in figure 3, etching is patterned to the silicon oxide layer and the p-type epitaxial layer 102
Untill cutting through, and continue to etch the N-type epitaxy layer to appointed thickness, to form clearance hole；Such as
Shown in Fig. 3, in the inwall of the clearance hole and bottom by ion diffusion technique, to form N-type expansion
Dissipate area 107；As shown in figure 4, carrying out thermal oxidation to the N-type diffusion region 107, pass through institute
The thermal oxide layer 106 for stating thermal oxidation formation fills the clearance hole, to form the isolation channel
108。
In the technical scheme, clearance hole is filled by thermal oxidation technology, on the one hand, pass through to be formed
N-type epitaxy layer and p-type epitaxial layer 102 carry out partial pressure, on the other hand, based on isolation channel 108
More preferable scribing processing exactly is realized, to improve the efficiency of volume production.
Silicon oxide layer is formed on the p-type epitaxial layer 102, specifically includes following steps：Using heat
Oxidation technology is handled the p-type epitaxial layer 102, to form the silicon oxide masking film layer.
Silicon oxide layer is formed on the p-type epitaxial layer 102, specifically includes following steps：Using change
Learn vapor deposition process to handle the p-type epitaxial layer 102, to form the silicon oxide masking film
Layer.
As shown in figure 4, carrying out thermal oxidation to the N-type diffusion region 107, pass through the hot oxygen
Change the thermal oxide layer 106 that processing is formed and fill the clearance hole, to form the isolation channel 108, tool
Body comprises the following steps：It is 900~1000 DEG C of thermal oxidation technology to the N-type to use temperature range
Diffusion region 107 carries out thermal oxidation, and the thermal oxide layer 106 formed by the thermal oxidation is filled out
The clearance hole is filled, to form the isolation channel 108.
As shown in Figure 5 and Figure 6, in the p-type epitaxial layer 102 of the photodiode 1A units
In, p-type injection zone 103 and N-type injection zone 104 are sequentially formed, it is with formation and each described
The Zener diode 1B that photodiode 1A is connected in series, specifically includes following steps：To the P
Type epitaxial layer 102 carries out p-type ion implanting, and the energy range of the p-type ion implanting is
40~100KeV, the dosage range of the p-type ion implanting is 10E15~10E20/cm2, to be formed
The p-type doped region；The p-type doped region is made annealing treatment, injected with forming the p-type
Region 103；N-type ion implanting, the N-type ion are carried out to the p-type injection zone 103
The energy range of injection is 40~100KeV, and the dosage range of the N-type ion implanting is
10E15~10E20/cm2, to form the n-type doping area；The n-type doping area is annealed
Processing, to form the N-type injection zone 104, and then form the Zener diode 1B.
As shown in Fig. 5, Fig. 6 and Fig. 7, in the p-type epitaxial layer of the photodiode 1A units
In 102, p-type injection zone 103 and N-type injection zone 104 are sequentially formed, with formation and each
The Zener diode 1B that the photodiode 1A is connected in series, specifically includes following steps：To institute
State p-type epitaxial layer 102 and carry out p-type ion implanting, the energy range of the p-type ion implanting is
40~100KeV, the dosage range of the p-type ion implanting is 10E15~10E20/cm2, to be formed
The p-type doped region；N-type ion implanting, the N-type ion are carried out to the p-type doped region
The energy range of injection is 40~100KeV, and the dosage range of the N-type ion implanting is
10E~1510E20/cm2, to form the n-type doping area；To the p-type doped region and the N
Type doped region is made annealing treatment, to form the p-type injection zone 103 and the N-type simultaneously
Injection zone 104, and then form the Zener diode 1B.
As shown in fig. 7, on the N-type substrate 101 of the Zener diode 1B is formed, formed just
Face metal electrode 105A and back metal electrode 105B, specifically includes following steps：Described in formation
In the N-type substrate 101 of N-type injection zone 104, using double-faced sputter technique formed front side aluminum-silicon-
Copper composite metal layer and back aluminium-silicon-copper composite metal layer, using as the front metal electrode
The 105A and back metal electrode 105B.
After the front metal electrode 105A and back metal electrode 105B is formed, in institute
State position corresponding to isolation channel 108 and carry out scribing processing.
Technical scheme is described in detail above in association with accompanying drawing, it is contemplated that proposed in correlation technique
How to design a kind of new transient voltage suppressor and its prepare scheme, to effectively improve TVS
Device reverse characteristic and integrated technical problem.Therefore, the present invention proposes a kind of new transient electrical
The preparation scheme of diode processed is constrained, by the pole of photoelectricity two that series connection is upwardly formed in the Vertical Square of substrate
Pipe and Zener diode, the reverse characteristic of semiconductor devices is improved, reduce voltage surge to integrated
The influence degree of circuit, additional capacitor is reduced, while improve the integrated of semiconductor devices and can
By property.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for
For those skilled in the art, the present invention can have various modifications and variations.All essences in the present invention
God any modification, equivalent substitution and improvements made etc., should be included in the present invention with principle
Protection domain within.
Claims (10)
- A kind of 1. preparation method of transient voltage suppressor, it is characterised in that including：P-type epitaxial layer is formed in N-type substrate, to complete the preparation of photodiode；Isolation channel is formed on the p-type epitaxial layer, the photoelectricity two is divided with each isolation channel Pole pipe is two photodiode units；In the p-type epitaxial layer of the photodiode unit, p-type injection zone and N are sequentially formed Type injection zone, to form the Zener diode being connected in series with each photodiode；On the N-type substrate of the Zener diode is formed, front metal electrode and back metal are formed Electrode.
- 2. the preparation method of transient voltage suppressor according to claim 1, its feature It is, isolation channel is formed on the p-type epitaxial layer, the photoelectricity is divided with each isolation channel Diode is two photodiode units, specifically includes following steps：Silicon oxide layer is formed on the p-type epitaxial layer；The silicon oxide layer and the p-type epitaxial layer are patterned untill being etched to and cutting through, and after The continuous etching N-type epitaxy layer is to appointed thickness, to form clearance hole；In the inwall of the clearance hole and bottom by ion diffusion technique, to form N-type diffusion region；Thermal oxidation, the hot oxygen formed by the thermal oxidation are carried out to the N-type diffusion region Change layer and fill the clearance hole, to form the isolation channel.
- 3. the preparation method of transient voltage suppressor according to claim 2, its feature It is, forms silicon oxide layer on the p-type epitaxial layer, specifically include following steps：The p-type epitaxial layer is handled using thermal oxidation technology, to form the silicon oxide masking film Layer.
- 4. the preparation method of transient voltage suppressor according to claim 2, its feature It is, forms silicon oxide layer on the p-type epitaxial layer, specifically include following steps：The p-type epitaxial layer is handled using chemical vapor deposition method, to form the oxidation Silicon mask layer.
- 5. the preparation method of transient voltage suppressor according to claim 4, its feature It is, thermal oxidation, the heat formed by the thermal oxidation is carried out to the N-type diffusion region Oxide layer fills the clearance hole, to form the isolation channel, specifically includes following steps：Temperature range is used to carry out heat to the N-type diffusion region for 900~1000 DEG C of thermal oxidation technology Oxidation processes, the thermal oxide layer formed by the thermal oxidation fill the clearance hole, to be formed The isolation channel.
- 6. the preparation method of transient voltage suppressor according to claim 5, its feature Be, in the p-type epitaxial layer of the photodiode unit, sequentially form p-type injection zone and N-type injection zone, to form the Zener diode being connected in series with each photodiode, tool Body comprises the following steps：P-type ion implanting, the energy range of the p-type ion implanting are carried out to the p-type epitaxial layer For 40~100KeV, the dosage range of the p-type ion implanting is 10E15~10E20/cm2, with shape Into the p-type doped region；The p-type doped region is made annealing treatment, to form the p-type injection zone；N-type ion implanting, the energy of the N-type ion implanting are carried out to the p-type injection zone Scope is 40~100KeV, and the dosage range of the N-type ion implanting is 10E15~10E20/cm2, To form the n-type doping area；The n-type doping area is made annealing treatment, to form the N-type injection zone, and then Form the Zener diode.
- 7. the preparation method of transient voltage suppressor according to claim 5, its feature Be, in the p-type epitaxial layer of the photodiode unit, sequentially form p-type injection zone and N-type injection zone, to form the Zener diode being connected in series with each photodiode, tool Body comprises the following steps：P-type ion implanting, the energy range of the p-type ion implanting are carried out to the p-type epitaxial layer For 40~100KeV, the dosage range of the p-type ion implanting is 10E15~10E20/cm2, with shape Into the p-type doped region；N-type ion implanting, the energy model of the N-type ion implanting are carried out to the p-type doped region Enclose for 40~100KeV, the dosage range of the N-type ion implanting is 10E15~10E20/cm2, with Form the n-type doping area；The p-type doped region and the n-type doping area are made annealing treatment, to form institute simultaneously P-type injection zone and the N-type injection zone are stated, and then forms the Zener diode.
- 8. the preparation of transient voltage suppressor according to any one of claim 1 to 7 Method, it is characterised in that on the N-type substrate of the Zener diode is formed, form front metal Electrode and back metal electrode, specifically include following steps：On the N-type substrate of the N-type injection zone is formed, formed just using double-faced sputter technique Face aluminium-silicon-copper composite metal layer and back aluminium-silicon-copper composite metal layer, using as the front Metal electrode and the back metal electrode.
- 9. the preparation method of transient voltage suppressor according to claim 8, its feature It is, in addition to：It is corresponding in the isolation channel after the front metal electrode and the back metal electrode is formed Position carry out scribing processing.
- 10. a kind of transient voltage suppressor, it is characterised in that using such as claim 1 to 9 Any one of the preparation method of transient voltage suppressor be prepared.
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| CN112119507A (en) * | 2018-05-17 | 2020-12-22 | 日本电信电话株式会社 | Light detector |
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|---|---|---|---|---|
| US20110127577A1 (en) * | 2006-11-30 | 2011-06-02 | Madhur Bobde | Latch-up free vertical TVS diode array structure using trench isolation |
| CN102306649A (en) * | 2011-08-24 | 2012-01-04 | 浙江大学 | Bidirectional dual-channel transient voltage suppressor (TVS) |
| CN103377916A (en) * | 2012-04-19 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110127577A1 (en) * | 2006-11-30 | 2011-06-02 | Madhur Bobde | Latch-up free vertical TVS diode array structure using trench isolation |
| CN102306649A (en) * | 2011-08-24 | 2012-01-04 | 浙江大学 | Bidirectional dual-channel transient voltage suppressor (TVS) |
| CN103377916A (en) * | 2012-04-19 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112119507A (en) * | 2018-05-17 | 2020-12-22 | 日本电信电话株式会社 | Light detector |
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