CN107768250B - Method for producing a power semiconductor component and power semiconductor component - Google Patents
Method for producing a power semiconductor component and power semiconductor component Download PDFInfo
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- CN107768250B CN107768250B CN201610677403.9A CN201610677403A CN107768250B CN 107768250 B CN107768250 B CN 107768250B CN 201610677403 A CN201610677403 A CN 201610677403A CN 107768250 B CN107768250 B CN 107768250B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Abstract
The present disclosure relates to a method of manufacturing a power semiconductor device and a power semiconductor device, the method comprising: forming a front metal layer (11) on the interlayer dielectric layer of the power semiconductor device semi-finished product (100) with the interlayer dielectric layer formed; etching the front metal layer (11); performing alloy treatment on the etched front metal layer (11); forming a front-side titanium-nickel-silver layer (12) on the front-side metal layer (11) after the alloying treatment; and etching the front titanium-nickel-silver layer (12). According to the method, the power semiconductor device with the front surface covered with the titanium-nickel-silver layer is prepared, the welding process can be used for the front surface of the power semiconductor device during packaging, the heat dissipation capacity of the front surface of the power semiconductor device can be improved, and further the overall heat dissipation capacity of the power semiconductor device is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a power semiconductor device and a power semiconductor device.
Background
The front metal of the conventional power devices such as the IGBT, the FRD, the VDMOS and the like is only a single-layer aluminum silicon layer, when the power device provided with the front single-layer aluminum silicon layer is packaged, a routing process is adopted on the front side, and the front routing process is not beneficial to heat dissipation of the front side of the device.
Disclosure of Invention
An object of the present disclosure is to provide a method of manufacturing a power semiconductor device and a power semiconductor device having good overall heat dissipation capability.
In order to achieve the above object, the present disclosure provides a method of manufacturing a power semiconductor device, the method including: forming a front metal layer on the interlayer dielectric layer of the power semiconductor device semi-finished product with the interlayer dielectric layer; etching the front metal layer; performing alloying treatment on the etched front metal layer; forming a front titanium-nickel-silver layer on the front metal layer after the alloying treatment; and etching the front titanium-nickel-silver layer.
Optionally, after the etching treatment is performed on the front-side metal layer and before the front-side titanium-nickel-silver layer is formed on the alloy-treated front-side metal layer, the method further includes: and forming a protective layer on the etched front metal layer, wherein the front titanium-nickel-silver layer covers the boundary of the protective layer.
Optionally, the method further includes: after the front metal layer is subjected to etching treatment and before the front metal layer subjected to etching treatment is subjected to alloying treatment, forming a silicon nitride protective layer on the front metal layer subjected to etching treatment; and after the front metal layer after the etching treatment is subjected to the alloying treatment, forming a polyimide film protective layer on the silicon nitride protective layer before a front titanium-nickel-silver layer is formed on the front metal layer after the alloying treatment.
Optionally, the manufacturing step of the power semiconductor device semi-finished product includes: forming a gate oxide layer on a substrate; forming a polysilicon gate on the gate oxide layer; carrying out first etching treatment on the polysilicon gate and the gate oxide layer to form a first etching area, wherein the first etching area penetrates through the polysilicon gate and deeply penetrates into the gate oxide layer; forming a lower ion implantation area, a middle ion implantation area and an upper ion implantation area in the substrate, and forming a thermal oxidation layer on the gate oxide layer and the polysilicon gate, wherein the middle ion implantation area and the upper ion implantation area are positioned in the lower ion implantation area, and the middle ion implantation area is positioned below the upper ion implantation area; forming an interlayer dielectric layer on the thermal oxidation layer; forming a contact hole, wherein the contact hole penetrates through the interlayer dielectric layer, the thermal oxidation layer and the upper ion implantation area from top to bottom to the middle ion implantation area; and the front metal layer is filled in the contact hole and formed on the interlayer dielectric layer.
Optionally, the forming a lower ion implantation region, a middle ion implantation region, and an upper ion implantation region in the substrate, and the forming a thermal oxide layer on the gate oxide layer and the polysilicon gate includes: forming a first ion implantation region on an upper portion of the substrate, wherein a conductivity type of the first ion implantation region is opposite to a conductivity type of the substrate, and the first ion implantation region is located below the first etching region, and the first ion implantation region is the lower layer ion implantation region; forming a second ion implantation region in the first ion implantation region; forming a thermal oxide layer on the gate oxide layer and the polysilicon gate; forming a third ion implantation region in the first ion implantation region; the upper ion implantation area is one of the second ion implantation area and the third ion implantation area, the middle ion implantation area is the other of the second ion implantation area and the third ion implantation area, the conductivity type of the upper ion implantation area is the same as that of the substrate, and the conductivity type of the middle ion implantation area is the same as that of the first ion implantation area.
Optionally, the manufacturing step of the power semiconductor device semi-finished product further includes: forming an aluminum layer under the substrate; and forming a back titanium-nickel-silver layer below the aluminum layer.
Optionally, the manufacturing step of the power semiconductor device semi-finished product further includes: forming a P region below the substrate; forming an aluminum layer below the P region; and forming a back titanium-nickel-silver layer below the aluminum layer.
The present disclosure also provides a power semiconductor device, comprising: the gate oxide layer is formed on the substrate; the polycrystalline silicon gate is formed on the gate oxide layer; the first etching area penetrates through the polysilicon gate from top to bottom and penetrates into the gate oxide layer; the ion implantation device comprises a lower layer ion implantation area, an upper layer ion implantation area and a middle layer ion implantation area, wherein the lower layer ion implantation area is formed in a substrate, the conductivity type of the lower layer ion implantation area is opposite to that of the substrate, the upper layer ion implantation area and the middle layer ion implantation area are respectively formed in the lower layer ion implantation area, the upper layer ion implantation area is positioned above the middle layer ion implantation area, the conductivity type of the upper layer ion implantation area is the same as that of the substrate, and the conductivity type of the middle layer ion implantation area is the same as that of the lower layer ion implantation area; the thermal oxidation layer covers the polysilicon gate and the gate oxidation layer; an interlayer dielectric layer formed on the thermal oxide layer; the contact hole penetrates through the interlayer dielectric layer, the thermal oxidation layer and the upper ion implantation area from top to bottom to reach the middle ion implantation area; the front metal layer is filled in the contact hole and formed on the interlayer dielectric layer; and the front-side titanium-nickel-silver layer is formed on the front-side metal layer.
Optionally, the power semiconductor device further includes: and the protective layer is positioned on the front metal layer, and the front titanium-nickel-silver layer covers the boundary of the protective layer.
Optionally, the power semiconductor device further includes: the silicon nitride protective layer is positioned on the front metal layer; the polyimide film protective layer is positioned on the silicon nitride protective layer; and the front titanium-nickel-silver layer is positioned above the polyimide film protective layer and covers the boundary of the polyimide film protective layer.
Optionally, the power semiconductor device further includes: an aluminum layer located below the substrate; and the back titanium-nickel-silver layer is positioned below the aluminum layer.
Optionally, the power semiconductor device further includes: a P region located below the substrate; an aluminum layer located below the P region; and the back titanium-nickel-silver layer is positioned below the aluminum layer.
According to the method, the power semiconductor device with the front surface covered with the titanium-nickel-silver layer is prepared, the welding process can be used for the front surface of the power semiconductor device during packaging, the heat dissipation capacity of the front surface of the power semiconductor device can be improved, and further the overall heat dissipation capacity of the power semiconductor device is improved.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
FIGS. 1A-1B are flow diagrams illustrating a process for fabricating a power semiconductor device according to an exemplary embodiment;
FIGS. 2A-2B are flow diagrams illustrating the preparation of a passivation layer according to an exemplary embodiment;
FIGS. 3A-3G are flow diagrams illustrating a process for fabricating a semi-finished power semiconductor device according to an exemplary embodiment;
FIGS. 4A-4D 2 are flow charts illustrating the fabrication of a lower ion implantation region, a middle ion implantation region, an upper ion implantation region, and a thermal oxide layer according to one exemplary embodiment;
FIGS. 5A-5B are flow diagrams illustrating the preparation of an aluminum layer and a back titanium-nickel-silver layer according to an exemplary embodiment;
FIG. 5C is a flow chart of the preparation of the P-region, the aluminum layer and the back titanium-nickel-silver layer provided by an exemplary embodiment;
FIG. 6 is a schematic diagram of a power semiconductor device provided in an exemplary embodiment;
FIG. 7 is a schematic diagram of a power semiconductor device provided in an exemplary embodiment;
FIG. 8 is a schematic diagram of a power semiconductor device provided in an exemplary embodiment;
fig. 9 is a schematic structural diagram of a power semiconductor device according to an exemplary embodiment.
Description of the reference numerals
100 power semiconductor device semi-finished product
I first ion implantation region II second ion implantation region III third ion implantation region
1 substrate, 2 gate oxide layers and 3 polysilicon layers
4 first etching region 5 lower ion implantation region 6 upper ion implantation region
7 thermal oxidation layer 8 middle layer ion implantation region 9 interlayer medium layer
10 contact hole 11 front metal layer 12 front titanium nickel silver layer
13 silicon nitride protective layer 14 polyimide film protective layer 15 aluminum layer
16 back titanium nickel silver layer 17P area
Detailed Description
The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.
The present disclosure provides a method of manufacturing a power semiconductor device, which may be an IGBT, FRD, or VDMOS. Fig. 1A-1B are flow charts illustrating a method for manufacturing a power semiconductor device according to an exemplary embodiment.
As shown in fig. 1A, a front metal layer 11 is formed on an interlayer dielectric layer of a power semiconductor device semi-finished product 100 on which the interlayer dielectric layer is formed, the front metal layer 11 is etched, and the front metal layer 11 after the etching is alloyed, where the thickness of the front metal layer 11 after the alloying is 0.05 to 5 micrometers.
As shown in fig. 1B, a front-side titanium-nickel-silver layer 12 is formed on the front-side metal layer 11 after the alloying treatment; and etching the front titanium-nickel-silver layer 12. The specific steps may include: front side evaporation or sputtering of titanium nickel silver and front side titanium nickel silver lithography and etching. The front titanium nickel silver layer 12 includes a titanium layer, a nickel layer, and a silver layer, the titanium layer may be 0.05 to 0.5 microns thick, the nickel layer may be 0.1 to 2 microns thick, and the silver layer may be 0.1 to 2 microns thick.
This disclose on the one hand covers positive titanium nickel silver layer on positive metal level 11, the welding process can be used to power semiconductor device openly during the encapsulation, can improve the positive heat-sinking capability of power semiconductor device, and then improve power semiconductor device's whole heat-sinking capability, on the other hand this disclosure forms positive metal level 11 earlier, then carry out etching treatment and alloying treatment to positive metal level 11, with formation terminal field plate ring structure, prepare positive titanium nickel silver layer 12 again, positive titanium nickel silver layer 12 does not have the ring structure at power semiconductor device terminal, can avoid the influence of the side direction etching volume of positive titanium nickel silver to the terminal design, effectively reduce terminal area, avoid the influence of positive titanium nickel silver layer 12 to positive metal alloying step simultaneously, and then can effectively reduce power semiconductor device area.
In another exemplary embodiment, after the etching process is performed on the front-side metal layer 11 and before the front-side titanium-nickel-silver layer 12 is formed on the front-side metal layer 11 after the alloying process, the method further includes: and forming a protective layer on the front-side metal layer 11 after the etching treatment, wherein the front-side titanium-nickel-silver layer 12 covers the boundary of the protective layer. The passivation layer is preferably located on the boundary of the front metal layer 11. Fig. 2A-2B are flow charts illustrating the preparation of the passivation layer according to an exemplary embodiment, which may specifically include the following steps.
As shown in fig. 2A, after the etching process is performed on the front-side metal layer 11 and before the alloying process is performed on the front-side metal layer 11 after the etching process, a silicon nitride protective layer 13 is formed on the front-side metal layer 11 after the etching process, and the specific steps may include: silicon nitride is sputtered or deposited and then is lithographically and etched.
As shown in fig. 2B, after the alloying treatment is performed on the front-side metal layer 11 after the etching treatment, and before the front-side titanium-nickel-silver layer 12 is formed on the front-side metal layer 11 after the alloying treatment, a polyimide film protective layer 14 is formed on the silicon nitride protective layer 13, for example, by a wet etching method without performing photolithography and etching. Wherein the front-side titanium-nickel-silver layer 12 covers the boundary of the polyimide film protective layer 14. The design is that the titanium-nickel-silver covers the boundary of the polyimide film sheath 14, so that the polyimide film sheath 14 is not exposed, the influence of subsequent process acid liquid (such as titanium-nickel-silver etching liquid) on the boundary of the polyimide film sheath 14 can be avoided, the polyimide film sheath 14 is prevented from warping and peeling, and the thickness of the polyimide film sheath 14 can be 0.1 to 20 micrometers.
The existing IGBT and VDMOS manufacturing process generally includes: p-implantation, P + photoetching, P + implantation, P + photoresist removal, P-/P + well annealing, gate oxide etching, N + photoetching, N + implantation, N + photoresist removal, interlayer dielectric layer manufacturing, contact hole photoetching, etching, front metal sputtering and the like, wherein photoetching selective implantation is generally used for the P + implantation process and the N + implantation process. During such fabrication, the misalignment problem of P + lithography and N + lithography can cause fluctuations and deviations in device parameters (e.g., Vth). Especially, when the design margin is low, the parameter fluctuation is large, which can increase the process control difficulty and cause high photoetching rework rate, and reduce the product yield.
Fig. 3A-3G are flow charts illustrating the fabrication of a semi-finished power semiconductor device according to an exemplary embodiment. The manufacturing steps of the power semiconductor device semi-finished product 100 include the following steps.
As shown in fig. 3A, a gate oxide layer 2 is formed on a substrate 1.
As shown in fig. 3B, a polysilicon gate 3 is formed on the gate oxide layer 2. The substrate 1 may be a doped silicon substrate, and the doping type is not particularly limited, and may be P-type doping or N-type doping. The formation of the gate oxide layer 2 and the polysilicon gate 3 is not particularly limited and may be performed by any method known in the art.
As shown in fig. 3C, the polysilicon gate 3 and the gate oxide layer 2 are subjected to a first etching process to form a first etching region 4, wherein the first etching region 4 penetrates through the polysilicon gate 3 and penetrates deep into the gate oxide layer 2. The first etching process is not particularly limited and may be flexibly selected by those skilled in the art as desired, for example, including but not limited to wet etching, dry etching, laser etching, and the like.
As shown in fig. 3D, a lower ion implantation region 5, a middle ion implantation region 8 and an upper ion implantation region 6 are formed in the substrate 1, a thermal oxide layer 7 is formed on the gate oxide layer 2 and the polysilicon gate 3, and the thickness of the thermal oxide layer 7 may be 0.05 micrometers to 0.2 micrometers, wherein the middle ion implantation region 8 and the upper ion implantation region 6 are located in the lower ion implantation region 5, and the middle ion implantation region 8 is located below the upper ion implantation region 6.
As shown in fig. 3E, an interlayer dielectric layer 9 is formed on the thermal oxide layer 7, and the interlayer dielectric layer 9 may completely cover the upper surface of the thermal oxide layer 7. After the formation of the interlayer dielectric layer 9, before the subsequent steps, the interlayer dielectric layer 9 may be subjected to a reflow process to densify and planarize the interlayer dielectric layer 9. In some embodiments of the present invention, the reflow process of the interlayer dielectric layer 9 and the annealing process of the interlayer ion implantation region 8 can be performed simultaneously, which can simplify the manufacturing steps and save energy consumption.
As shown in fig. 3F, a contact hole 10 is formed, the contact hole 10 penetrates through the interlayer dielectric layer 9, the thermal oxidation layer 7 and the upper ion implantation region 6 from top to bottom to the middle ion implantation region 8, pins respectively connected with the upper ion implantation region 6 and the middle ion implantation region 8 can be conveniently led out from the surface of the contact hole 10, and further, the upper ion implantation region 6 and the middle ion implantation region 8 can be conveniently connected with other circuits. The height of the bottom of the contact hole 10 from the upper surface of the substrate 1 may be 0.5 to 1 micrometer.
As shown in fig. 3G, the front metal layer 11 is filled in the contact hole 10 and formed on the interlayer dielectric layer 9.
The power semiconductor device of the exemplary embodiment has the advantages of simple preparation process, low process control difficulty, almost no parameter fluctuation and deviation caused by alignment deviation, high device parameter stability and high product yield.
Fig. 4A-4D 2 are flow charts illustrating the fabrication of the lower ion implantation region, the middle ion implantation region, the upper ion implantation region, and the thermal oxide layer according to an exemplary embodiment. The step of forming a lower ion implantation region 5, a middle ion implantation region 8 and an upper ion implantation region 6 in the substrate 1 and forming a thermal oxide layer 7 on the gate oxide layer 2 and the polysilicon gate 3 includes the following steps.
As shown in fig. 4A, a first ion implantation region I is formed in an upper portion of the substrate 1, wherein a conductivity type of the first ion implantation region I is opposite to a conductivity type of the substrate, and the first ion implantation region I is located below the first etching region 4, and the first ion implantation region I is the lower layer ion implantation region 5.
It should be noted that the description "the conductivity type of the first ion injection region I is opposite to the conductivity type of the substrate 1" used in the present disclosure means that when the conductivity type of the substrate 1 is electron conduction, the conductivity type of the first ion injection region I is hole conduction, and when the conductivity type of the substrate 1 is hole conduction, the conductivity type of the first ion injection region I is electron conduction, and the expressions of "conductivity types are opposite" in the foregoing and the following text mean that both are hole conduction or electron conduction, and the same conductivity type means that both are hole conduction or electron conduction.
The ions injected to form the first ion implantation region I may be selected according to the conductivity type of the substrate 1, and specifically, when the conductivity type of the substrate 1 is hole conduction, the ions injected may be arsenic, phosphorus, or the like, so that the conductivity type of the first ion implantation region I is electron conduction, whereas, if the conductivity type of the substrate 1 is electron conduction, the ions injected may be boron, or the like, so that the conductivity type of the first ion implantation region I is hole conduction. Of course, it will be understood by those skilled in the art that the specific ions are not limited to arsenic, phosphorus or boron, and any ions may be selected by those skilled in the art as long as the conductivity type of the first ion implantation region I can be made hole-conductive or electron-conductive.
After the first ion implantation region I is formed, before the subsequent steps are performed, the first ion implantation region I may be annealed to activate the dopant ions and repair the lattice damage.
As shown in fig. 4B1 and 4B2, a second ion implantation region II is formed in the first ion implantation region I.
The second ion implantation region II may be disposed at two positions, specifically, the first position may be referred to as fig. 4B2, the second ion implantation region II may be located at the top (or upper layer) of the first ion implantation region I, the second position may be referred to as fig. 4B1, and the second ion implantation region II may be located at the middle (or middle layer) of the first ion implantation region I. The specific position of the second ion implantation region II may be determined according to the type structure of the power semiconductor device and the diffusion coefficient of the implanted ions, specifically, ions with a small diffusion coefficient are preferentially implanted during the manufacturing process, so that the diffusion coefficient of the implanted ions forming the second ion implantation region II is smaller than that of the implanted ions subsequently forming the third ion implantation region III, and then the specific position of the second ion implantation region II is determined according to the specific type structure of the power semiconductor device, for example, for an N-type trench IGBT, a VDMOS, an N-type drift region, a P-well, and a P + region are below the N + region, if the diffusion coefficient of the N + implanted ions is smaller than that of the P + implanted ions, the second ion implantation region II is located at the top of the first ion implantation region I, if the diffusion coefficient of the P + implanted ions is smaller than that of the N + implanted ions, the second ion implantation area II is positioned in the middle of the first ion implantation area I; for a P-type groove VDMOS, a P-type drift region, an N trap and an N + region are arranged under a P + region, if the diffusion coefficient of N + implanted ions is smaller than that of P + implanted ions, a second ion implantation region II is arranged in the middle of a first ion implantation region I, and if the diffusion coefficient of P + implanted ions is smaller than that of N + implanted ions, the second ion implantation region II is arranged at the top of the first ion implantation region I.
When the second ion implantation area II is positioned at the top of the first ion implantation area I, the conductivity type of the second ion implantation area II is the same as that of the substrate 1, and the doping amount of the second ion implantation area II is higher than that of the substrate 1; when the second ion implantation area II is positioned in the middle of the first ion implantation area I, the conductivity type of the second ion implantation area II is the same as that of the first ion implantation area I, and the doping amount of the second ion implantation area II is higher than that of the first ion implantation area I. Therefore, the use effect of the power semiconductor device is improved.
After the second ion implantation region II is formed, before the subsequent steps are performed, annealing treatment may be performed on the second ion implantation region II to activate the dopant ions and repair the lattice damage.
As shown in fig. 4C1 and 4C2, a thermal oxide layer 7 is formed on the gate oxide layer 2 and the polysilicon gate 3. By forming the thermal oxide layer 7, self-alignment can be performed when an ion implantation area is formed subsequently, parameter fluctuation and deviation caused by problems of N + photoetching alignment and P + photoetching alignment in the prior art are effectively avoided, parameter stability of a device is improved, process steps of P + photoetching, P + photoresist removal, N + photoetching, N + photoresist removal and the like are reduced, a preparation process is simplified, process control difficulty is reduced, and the thickness of the thermal oxide layer 7 can be 0.05-0.2 micrometer.
In addition, the substance exposed on the upper surface of the gate oxide layer 2 may be oxidized to obtain the thermal oxide layer 7. Of course, the manner of forming the thermal oxide layer 7 is not limited thereto, and those skilled in the art may adopt any other method for replacement. The gate oxide layer 2 that was not completely etched away in the first etching process is used as the thermal oxide layer 7 together with the oxide layer formed in this step.
Forming a third ion implantation region III in the first ion implantation region I as shown in fig. 4D1 and 4D 2; it should be noted that the upper ion implantation region 6 is one of the second ion implantation region II and the third ion implantation region III, the middle ion implantation region 8 is the other of the second ion implantation region II and the third ion implantation region III, a conductivity type of the upper ion implantation region 6 is the same as a conductivity type of the substrate 1, and a conductivity type of the middle ion implantation region 8 is the same as a conductivity type of the first ion implantation region I.
According to the foregoing description in the preparation steps shown in fig. 4B1 and fig. 4B2, the position of the third ion implantation region III may be in two cases depending on the position where the second ion implantation region is disposed, and specifically, referring to fig. 4D2, if the second ion implantation region II is located at the top of the first ion implantation region I, the third ion implantation region III is located at the middle of the first ion implantation region I, below the second ion implantation region II; referring to fig. 4D1, if the second ion implantation region II is located at the middle of the first ion implantation region I, the third ion implantation region III is located at the top of the first ion implantation region I, above the second ion implantation region II.
When the third ion implantation area III is positioned at the top of the first ion implantation area I, the conductivity type of the third ion implantation area III is the same as that of the substrate 1, and the doping amount of the third ion implantation area III is higher than that of the substrate; when the third ion implantation area III is located in the middle of the first ion implantation area I, the conductivity type of the third ion implantation area III is the same as that of the first ion implantation area I, and the doping amount of the third ion implantation area III is higher than that of the first ion implantation area I. Therefore, the use effect of the power semiconductor device is improved.
After the third ion implantation region III is formed and before the subsequent steps are performed, the third ion implantation region III may be annealed to activate the dopant ions and repair the lattice damage.
Fig. 5A-5B are flow diagrams illustrating the preparation of an aluminum layer and a back titanium nickel silver layer according to an exemplary embodiment. The manufacturing steps of the power semiconductor device semi-finished product 100 further include the following steps.
As shown in fig. 5A, an aluminum layer 15 is formed below the substrate 1.
As shown in fig. 5B, a back titanium-nickel-silver layer 16 is formed below the aluminum layer 15.
Fig. 5C is a flow chart of the preparation of the P-region, the aluminum layer, and the back titanium nickel silver layer provided by an exemplary embodiment. The manufacturing steps of the power semiconductor device semi-finished product 100 further include the following steps.
As shown in fig. 5C, a P region 17 is formed below the substrate 1; forming an aluminum layer 15 under the P region 17; a back titanium nickel silver layer 16 is formed below the aluminum layer 15. The specific steps may include: and thinning and etching the lower part of the substrate 1, injecting boron into the lower part and annealing to form a P region, and then sputtering or evaporating an aluminum layer 15 and a back titanium-nickel-silver layer 16.
According to the method provided by the exemplary embodiment, the titanium-nickel-silver layers are formed on the front side and the back side of the power semiconductor device, the front side and the back side of the power semiconductor device can use a welding process during packaging, and the overall heat dissipation capacity of the power semiconductor device can be improved.
Fig. 6 is a schematic structural diagram of a power semiconductor device according to an exemplary embodiment. As shown in fig. 6, the power semiconductor device includes:
the substrate 1 is provided with a plurality of layers,
a gate oxide layer 2 formed on the substrate 1;
a polysilicon gate 3 formed on the gate oxide layer 2;
the first etching area penetrates through the polysilicon gate 3 from top to bottom and penetrates into the gate oxide layer 2;
a lower ion implantation region 5, an upper ion implantation region 6 and a middle ion implantation region 8, wherein the lower ion implantation region 5 is formed in the substrate 1, the conductivity type of the lower ion implantation region 5 is opposite to that of the substrate 1, the upper ion implantation region 6 and the middle ion implantation region 8 are respectively formed in the lower ion implantation region 5, the upper ion implantation region 6 is located above the middle ion implantation region 8, the conductivity type of the upper ion implantation region 6 is the same as that of the substrate 1, and the conductivity type of the middle ion implantation region 8 is the same as that of the lower ion implantation region 5;
the thermal oxidation layer 7 covers the polysilicon gate 3 and the gate oxidation layer 2;
an interlayer dielectric layer 9 formed on the thermal oxide layer 7;
a contact hole which penetrates through the interlayer dielectric layer 9, the thermal oxidation layer 7 and the upper ion implantation area 6 from top to bottom to reach the middle ion implantation area 8;
the front metal layer 11 is filled in the contact hole and formed on the interlayer dielectric layer 9;
and a front-side titanium-nickel-silver layer 12 formed on the front-side metal layer 11.
According to the power semiconductor device, the front titanium-nickel-silver layer covers the surface of the front metal layer 11, the welding process can be used on the front of the power semiconductor device during packaging, the heat dissipation capacity of the front of the power semiconductor device can be improved, the overall heat dissipation capacity of the power semiconductor device is further improved, on the other hand, parameter fluctuation and deviation caused by alignment deviation of the power semiconductor device are almost avoided, the parameter stability of the device is high, the preparation process is simple, the process control difficulty is low, and the product yield is high.
Fig. 7 is a schematic structural diagram of a power semiconductor device according to an exemplary embodiment. The power semiconductor device further includes: and the protective layer is positioned on the front metal layer 11, and the front titanium-nickel-silver layer 12 covers the boundary of the protective layer. The passivation layer is preferably located on the boundary of the front metal layer 11.
As shown in fig. 7, the sheath includes:
a silicon nitride protective layer 13 located on the front metal layer 11;
the polyimide film protective layer 14 is positioned on the silicon nitride protective layer 13;
the front titanium-nickel-silver layer 12 is located above the polyimide film sheath 14 and covers the boundary of the polyimide film sheath 14, so that the boundary of the polyimide film sheath 14 is not exposed, the influence of a subsequent process acid solution (such as a titanium-nickel-silver etching solution) on the boundary of the polyimide film sheath 14 can be avoided, the polyimide film sheath 14 is prevented from warping and peeling, and the thickness of the polyimide film sheath 14 can be 0.1 to 20 micrometers.
Fig. 8 is a schematic structural diagram of a power semiconductor device according to an exemplary embodiment. As shown in fig. 8, the power semiconductor device further includes:
an aluminum layer 15 located below the substrate 1;
and the back titanium-nickel-silver layer 16 is positioned below the aluminum layer 15, and the semiconductor power device is a VDMOS without a P region 17.
Fig. 9 is a schematic structural diagram of a power semiconductor device according to an exemplary embodiment. As shown in fig. 9, the power semiconductor device further includes:
a P region 17 located below the substrate 1; an aluminum layer 15 located below the P region 17; and the back titanium-nickel-silver layer 16 is positioned below the aluminum layer 15. The semiconductor power device is an IGBT forming a P region 17.
The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
It should be noted that, in the foregoing embodiments, various features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various combinations that are possible in the present disclosure are not described again.
In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.
Claims (9)
1. A method of fabricating a power semiconductor device, the method comprising:
forming a front metal layer (11) on the interlayer dielectric layer of the power semiconductor device semi-finished product (100) with the interlayer dielectric layer formed;
etching the front metal layer (11);
performing alloy treatment on the etched front metal layer (11);
forming a front-side titanium-nickel-silver layer (12) on the front-side metal layer (11) after the alloying treatment; and
etching the front titanium-nickel-silver layer (12),
the manufacturing method of the power semiconductor device semi-finished product (100) comprises the following steps:
forming a gate oxide layer (2) on a substrate (1);
forming a polysilicon gate (3) on the gate oxide layer (2);
subjecting the polysilicon gate (3) and the gate oxide layer (2) to a first etching process to form a first etching region (4), wherein the first etching region (4) penetrates through the polysilicon gate (3) and penetrates into the gate oxide layer (2);
forming a lower ion implantation area (5), a middle ion implantation area (8) and an upper ion implantation area (6) in the substrate (1), and forming a thermal oxidation layer (7) on the gate oxide (2) and the polysilicon gate (3), wherein the middle ion implantation area (8) and the upper ion implantation area (6) are positioned in the lower ion implantation area (5), and the middle ion implantation area (8) is positioned below the upper ion implantation area (6);
forming an interlayer dielectric layer (9) on the thermal oxidation layer (7);
forming a contact hole (10), wherein the contact hole (10) penetrates through the interlayer dielectric layer (9), the thermal oxidation layer (7) and the upper ion implantation area (6) from top to bottom to the middle ion implantation area (8);
wherein the front metal layer (11) is filled in the contact hole (10) and formed on the interlayer dielectric layer (9),
wherein, after the etching treatment of the front-side metal layer (11), and before forming a front-side titanium-nickel-silver layer (12) on the alloy-treated front-side metal layer (11), the method further comprises:
and forming a protective layer on the front-side metal layer (11) after etching treatment, wherein the front-side titanium-nickel-silver layer (12) covers the boundary of the protective layer.
2. The method of claim 1, further comprising:
forming a silicon nitride protective layer (13) on the etched front metal layer (11) after the etching treatment of the front metal layer (11) and before the alloying treatment of the etched front metal layer (11); and
and after the front metal layer (11) after the etching treatment is subjected to the alloying treatment, forming a polyimide film protective layer (14) on the silicon nitride protective layer (13) before forming a front titanium-nickel-silver layer (12) on the front metal layer (11) after the alloying treatment.
3. The method according to claim 1, wherein the step of forming a lower ion implantation region (5), a middle ion implantation region (8) and an upper ion implantation region (6) in the substrate (1), and forming a thermal oxide layer (7) on the gate oxide layer (2) and the polysilicon gate (3) comprises:
forming a first ion implantation region (I) on the upper part of the substrate (1), wherein the conductivity type of the first ion implantation region (I) is opposite to that of the substrate (1), and the first ion implantation region (I) is positioned below the first etching region (4), and the first ion implantation region (I) is the lower layer ion implantation region (5);
forming a second ion implantation region (II) in the first ion implantation region (I);
forming a thermal oxide layer (7) on the gate oxide layer (2) and the polysilicon gate (3);
forming a third ion implantation region (III) in the first ion implantation region (I);
wherein the upper ion implantation region (6) is one of the second ion implantation region (II) and the third ion implantation region (III), the middle ion implantation region (8) is the other of the second ion implantation region (II) and the third ion implantation region (III), the conductivity type of the upper ion implantation region (6) is the same as the conductivity type of the substrate (1), and the conductivity type of the middle ion implantation region (8) is the same as the conductivity type of the first ion implantation region (I).
4. The method according to claim 1, wherein the step of fabricating the power semiconductor device semi-finished product (100) further comprises:
-forming an aluminium layer (15) below the substrate (1);
and forming a back titanium-nickel-silver layer (16) below the aluminum layer (15).
5. The method according to claim 1, wherein the step of fabricating the power semiconductor device semi-finished product (100) further comprises:
forming a P region (17) below the substrate (1);
-forming an aluminium layer (15) below said P-region (17);
and forming a back titanium-nickel-silver layer (16) below the aluminum layer (15).
6. A power semiconductor device, comprising:
a substrate (1) having a first and a second substrate,
a gate oxide layer (2) formed on the substrate (1);
a polysilicon gate (3) formed on the gate oxide layer (2);
the first etching area penetrates through the polysilicon gate (3) from top to bottom and penetrates into the gate oxide layer (2);
the substrate comprises a lower layer ion implantation area (5), an upper layer ion implantation area (6) and a middle layer ion implantation area (8), wherein the lower layer ion implantation area (5) is formed in the substrate (1), the conductivity type of the lower layer ion implantation area (5) is opposite to that of the substrate (1), the upper layer ion implantation area (6) and the middle layer ion implantation area (8) are respectively formed in the lower layer ion implantation area (5), the upper layer ion implantation area (6) is positioned above the middle layer ion implantation area (8), the conductivity type of the upper layer ion implantation area (6) is the same as that of the substrate (1), and the conductivity type of the middle layer ion implantation area (8) is the same as that of the lower layer ion implantation area (5);
the thermal oxidation layer (7) covers the polysilicon gate (3) and the gate oxidation layer (2);
an interlayer dielectric layer (9) formed on the thermal oxide layer (7);
the contact hole penetrates through the interlayer dielectric layer (9), the thermal oxidation layer (7) and the upper ion implantation area (6) from top to bottom to reach the middle ion implantation area (8);
the front metal layer (11) is filled in the contact hole and formed on the interlayer dielectric layer (9);
a front-side titanium-nickel-silver layer (12) formed on the front-side metal layer (11),
wherein the power semiconductor device further comprises:
and the protective layer is positioned on the front metal layer (11), and the front titanium-nickel-silver layer (12) covers the boundary of the protective layer.
7. The power semiconductor device of claim 6, wherein the protective layer comprises:
a silicon nitride protective layer (13) positioned on the front metal layer (11);
the polyimide film protective layer (14) is positioned on the silicon nitride protective layer (13);
the front-side titanium-nickel-silver layer (12) is positioned above the polyimide film protective layer (14) and covers the boundary of the polyimide film protective layer (14).
8. The power semiconductor device of claim 6, further comprising:
an aluminium layer (15) located below the substrate (1);
and the back titanium-nickel-silver layer (16) is positioned below the aluminum layer (15).
9. The power semiconductor device of claim 6, further comprising:
a P region (17) located below the substrate (1);
an aluminum layer (15) located below the P region (17);
and the back titanium-nickel-silver layer (16) is positioned below the aluminum layer (15).
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| CN102496571A (en) * | 2011-12-19 | 2012-06-13 | 杭州士兰集成电路有限公司 | Method and structure for manufacturing low barrier Schottky diode |
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| US20050092985A1 (en) * | 2003-10-29 | 2005-05-05 | International Business Machines Corporation | Single and double-gate pseudo-fet devices for semiconductor materials evaluation |
| CN102496571A (en) * | 2011-12-19 | 2012-06-13 | 杭州士兰集成电路有限公司 | Method and structure for manufacturing low barrier Schottky diode |
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