CN110518012A - A kind of grid constraint thyristor ESD device and its implementation - Google Patents
A kind of grid constraint thyristor ESD device and its implementation Download PDFInfo
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- CN110518012A CN110518012A CN201910809608.1A CN201910809608A CN110518012A CN 110518012 A CN110518012 A CN 110518012A CN 201910809608 A CN201910809608 A CN 201910809608A CN 110518012 A CN110518012 A CN 110518012A
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 40
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 238000000605 extraction Methods 0.000 claims abstract description 24
- 238000002955 isolation Methods 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 230000008901 benefit Effects 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 238000012423 maintenance Methods 0.000 abstract description 9
- 230000007547 defect Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000001737 promoting effect Effects 0.000 abstract description 5
- 230000000694 effects Effects 0.000 description 9
- 230000008569 process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention discloses a kind of grid constraint thyristor ESD device and its implementation, high concentration p-type doping by the way that existing grid to be constrained to the jointed anode of thyristor ESD device replaces with low concentration p-type and (20) is lightly doped, and surface forms metal silicide (30) thereon, anode of the extraction electrode as grid constraint thyristor ESD device, the present invention can be while promoting maintenance voltage, simplify manufacturing process, the boundary defect because introducing schottky junction is reduced, and reduces its contact resistance.
Description
Technical field
The present invention relates to semiconductor integrated circuit technology fields, constrain thyristor more particularly to a kind of novel grid
ESD (Electro-Static Discharge, Electro-static Driven Comb) device and its implementation.
Background technique
In integrated circuit antistatic protection design field, antistatic protection design protection window is generally dependent on operating voltage
With the gate oxide thickness of internal protected circuit, the operating voltage with general Advanced CMOS Process integrated circuit is 1V or so,
Gate oxide thickness is about the antistatic protection design window of the Advanced CMOS Process integrated circuit for 14A (angstrom, 0.1nm)
Usually between 1.2V~2.8V, and typical GGNMOS (Grounded-Gate NMOS) electrostatic protection in Advanced CMOS Process
The trigger voltage (Vt1) of the echo effect of device is commonly greater than 2.8V, so industry first proposed a kind of grid as shown in Figure 1
Constraint thyristor attempts to solve this problem.
As shown in Figure 1, existing grid constraint thyristor ESD device include multiple shallow trench isolation layers (STI,
Shallow Trench Isolation) 10, high concentration n-type doping (N+) 28, the doping of high concentration p-type (P+) 20, high concentration N-type
Adulterate (N+) 24, high concentration p-type doping (P+) 26, N trap (N-Well) 60, p-well (P-Well) 70, P type substrate (P-Sub) 80,
The metal silicide (Silicide) 30 of first floating gate 40, second grid 50 and multiple connecting doped areas and electrode.
Entire ESD device is placed in P type substrate (P-Sub) 80, generates a N trap on 80 left side of P type substrate (P-Sub)
(N-Well) 60, a p-well (P-Well) 70, high concentration n-type doping (N+) 28, height are generated on 80 the right of P type substrate (P-Sub)
Concentration of P type doping (P+) 20 is placed in 60 top of N trap (N-Well), and high concentration p-type adulterates (P+) 20, N trap (N-Well) 60 and P
Trap (P-Well) 70 constitutes equivalent PNP triode structure, and high concentration n-type doping (N+) 24, high concentration p-type doping (P+) 26 are placed in
70 top of p-well (P-Well), N trap (N-Well) 60, p-well (P-Well) 70 and high concentration n-type doping (N+) 24 constitute equivalent N PN
Audion；
Shallow trench isolation layer (STI, Shallow Trench is placed in 28 left side of high concentration n-type doping (N+)
Isolation) 10, between high concentration n-type doping (N+) 28, high concentration p-type doping (P+) 20 (i.e. with the isolation of N trap (N-Well) 60
60 a part is divided between therebetween), the first floating gate 40 is placed above the N trap of the part, high concentration p-type adulterates the right side of (P+) 20
Side is a part of N trap (N-Well) 60, and the width of part N trap (N-Well) 60 is A, high concentration n-type doping (N+) 24, height
Concentration of P type is isolated between adulterating (P+) 26 with shallow trench isolation layer (STI, Shallow Trench Isolation) 10, high concentration P
Type adulterates 26 right side (P+) and places shallow trench isolation layer (STI, Shallow Trench Isolation) 10, and high concentration N-type is mixed
The left side of miscellaneous (N+) 24 is a part of p-well (P-Well) 70, and the width of the part p-well (P-Well) 70 is B；
The top of (P+) 20, high concentration n-type doping (N are adulterated in the top of high concentration n-type doping (N+) 28, high concentration p-type
+) 24 top, high concentration p-type doping (P+) 26 top generate 4 metal silicides 30, in high concentration n-type doping (N+) 24
Place second gate in the top for the N trap that width above the p-well that the width in left side is B and on the right side of high concentration p-type doping (P+) 20 is A
Pole 50, i.e. second grid 50 above N trap and p-well boundary and do not cover high concentration p-type doping (P+) 20 and high concentration N-type mix
Miscellaneous (N+) 24；
30 extraction electrode of metal silicide of 28 top of high concentration n-type doping (N+) is connected to power supply Vdd, high concentration p-type
Adulterate anode of 30 extraction electrode of metal silicide of 20 top (P+) as novel grid constraint thyristor ESD device
The metal silicide 30 and high concentration p-type of the top of Anode, second grid 50 and high concentration n-type doping (N+) 24 adulterate (P
+) metal silicide 30 of 26 top is connected and extraction electrode forms the cathode of existing grid constraint thyristor ESD device
Cathode, minus earth Vss when use.
It is surveyed as a result, it has been found that its maintenance voltage (Vh) is too low, only 1.2V or so.
Currently, industry also then proposes embedded Xiao such as Fig. 2 on the basis of grid as shown in Figure 1 constrain thyristor
The modified grid of special base junction constrain thyristor to promote its maintenance voltage (Vh), i.e., on 24 left side of high concentration n-type doping (N+)
The top of the p-well (P-Well) 70 of side directly forms metal layer 22 to form schottky junction (Schottky Junction), in gold
The top for the p-well (P-Well) 70 that the width in the left side of category layer 22 is B-S and the width on the right side of high concentration p-type doping (P+) 20 are
The top of the N trap (N-Well) 60 of A is only second grid (floating gate) 50.
As the grid of Fig. 1 constrain the echo effect characteristic of thyristor and the modified grid constraint thyristor such as Fig. 2
As shown in figure 3, left side be Fig. 1 characteristic curve, right side be Fig. 2 characteristic curve, by Fig. 3 it can be concluded that, such as embedded Xiao of Fig. 2
The maintenance voltage of its echo effect can be promoted to 2V from 1.2V by the modified grid constraint thyristor of special base junction, and be triggered
Voltage is then controlled in 2.4V, still is below 2.8V, so the grid constraint thyristor such as the embedded schottky junction of Fig. 2 is more applicable
It is designed in the antistatic protection of Advanced CMOS Process integrated circuit.But the introducing of schottky junction causes its technique more complicated, separately
Outer metal-semiconductor contact interface is readily incorporated boundary defect, and the contact resistance of schottky junction is higher.
Summary of the invention
In order to overcome the deficiencies of the above existing technologies, purpose of the present invention is to provide a kind of grid to constrain thyristor
ESD device and its implementation are reduced with simplifying manufacturing process while promoting maintenance voltage because introducing schottky junction
Boundary defect, and reduce its contact resistance.
In view of the above and other objects, the present invention proposes a kind of grid constraint thyristor ESD device, the ESD device
Include:
Semiconductor substrate (80)；
The N trap (60) and p-well (70) being created in the semiconductor substrate (80)；
High concentration n-type doping (28), low concentration p-type are lightly doped (20) and are placed in N trap (60) top, high concentration n-type doping
(24), high concentration p-type doping (26) is placed in the p-well (70) top；
The top of the high concentration n-type doping (28), low concentration p-type be lightly doped (20) top and the high concentration N
The top of type doping (24), the top of high concentration p-type doping (26) generate metal silicide (30) respectively；
Metal silicide (30) extraction electrode above the high concentration n-type doping (28) is connected to connection power supply, described
Low concentration p-type is lightly doped metal silicide (30) extraction electrode above (20) as the grid and constrains thyristor ESD device
The anode of part, the metal silicide (30) of the top of the high concentration n-type doping (24) and the high concentration p-type are adulterated on (26)
The metal silicide (30) of side is connected and extraction electrode forms the cathode that the grid constrain thyristor ESD device.
Preferably, the low concentration p-type is lightly doped (20), the N trap (60) and the p-well (70) and constitutes equivalent PNP
Audion.
Preferably, the N trap (60), p-well (70) and the high concentration n-type doping (24) constitute equivalent N PN triode knot
Structure.
Preferably, shallow trench isolation layer (10) are set on the left of the high concentration n-type doping (28), the high concentration N-type is mixed
Miscellaneous (28), low concentration p-type are isolated between (20) are lightly doped using the N trap (60), place the first floating gate above the N trap of the part
(40), a part that the right side of (20) is the N trap (60) is lightly doped in the low concentration p-type, and the width of part N trap is A.
Preferably, the high concentration n-type doping (24), high concentration p-type doping (26) between with shallow trench isolation layer (10) every
From placement shallow trench isolation layer (10) on the right side of the high concentration p-type doping (26), high concentration n-type doping (24) left side is
A part of the p-well (70), the width of the part p-well are B
Preferably, the doping of (20) is lightly doped by A, B and the low concentration p-type for the echo effect characteristic of the ESD device
Concentration codetermines, and wherein A is 0.1~0.5um, and B is 0.1~0.5um, and doping concentration dosage range is 1E12-1E15/cm2。
Preferably, it is gently mixed above the p-well that high concentration n-type doping (24) left side width is B with the low concentration p-type
Place the second floating gate (50) in the top for the N trap that width on the right side of miscellaneous (20) is A.
In order to achieve the above objectives, described the present invention also provides a kind of implementation method of grid constraint thyristor ESD device
The high concentration p-type doping of the jointed anode of existing grid constraint thyristor ESD device is replaced with low concentration p-type and gently mixed by method
Miscellaneous (20), and surface forms metal silicide (30) thereon, extraction electrode constrains thyristor ESD device as the grid
Anode.
Preferably, which comprises
Step 501, semi-conductive substrate (80) are provided；
Step 502, N trap (60) and p-well (70) are generated in the semiconductor substrate (80)；
Step 503, (20) are lightly doped in high concentration n-type doping (28), low concentration p-type and are placed in N trap (60) top, high concentration
N-type doping (24), high concentration p-type doping (26) are placed in the p-well (70) top；
Step 504, the top of (20) and described is lightly doped in the top of the high concentration n-type doping (28), low concentration p-type
The top of high concentration n-type doping (24), the top of high concentration p-type doping (26) generate metal silicide (30) respectively；
Step 505, metal silicide (30) extraction electrode above the high concentration n-type doping (28) is connected to connection
Power supply, it is whole as grid constraint silicon control that metal silicide (30) extraction electrode above (20) is lightly doped in the low concentration p-type
Flow the anode of device ESD device, the metal silicide (30) of the top of the high concentration n-type doping (24) and the high concentration p-type
Metal silicide (30) above doping (26) is connected and extraction electrode forms the yin that the grid constrain thyristor ESD device
Pole.
Preferably, minus earth when the grid constraint thyristor ESD device uses.
Compared with prior art, a kind of grid constraint thyristor ESD device of the present invention and its implementation will be by that will show
There is the high concentration p-type doping of the jointed anode of grid constraint thyristor ESD device to replace with low concentration p-type lightly doped district
(PLDD), manufacturing process can be simplified while promoting its maintenance voltage, reduces the boundary defect because introducing schottky junction, and
Its contact resistance is reduced, the antistatic protection design of Advanced CMOS Process integrated circuit is more applicable for.
Detailed description of the invention
Fig. 1 is the schematic diagram of the ESD device of a prior art；
Fig. 2 is the schematic diagram of the ESD device of another prior art；
Fig. 3 is that grid constrain thyristor echo effect characteristic and schottky junction relation schematic diagram in the prior art；
Fig. 4 is the device junction composition for the preferred embodiment that a kind of grid of the present invention constrain thyristor ESD device；
Fig. 5 is the step flow chart for the implementation method that a kind of grid of the present invention constrain thyristor ESD device；
Fig. 6 is application scenarios schematic diagram of the invention.
Specific embodiment
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand further advantage and effect of the invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from
Various modifications and change are carried out under spirit of the invention.
Fig. 4 is the device junction composition for the preferred embodiment that a kind of grid of the present invention constrain thyristor ESD device.Such as Fig. 4
Shown, a kind of grid of the present invention constrain thyristor ESD device, comprising: multiple shallow trench isolation layer (STI, Shallow
Trench Isolation) 10, high concentration n-type doping (N+) 28, low concentration p-type (PLDD) 20, high concentration n-type doping is lightly doped
(N+) 24, the doping of high concentration p-type (P+) 26, N trap (N-Well) 60, p-well (P-Well) 70, P type substrate (P-Sub) 80, first
The metal silicide (Silicide) 30 of floating gate 40, the second floating gate 50 and multiple connecting doped areas and electrode.
Entire ESD device is placed in P type substrate (P-Sub) 80, and two traps: N trap are generated in P type substrate (P-Sub) 80
(N-Well) 60 and p-well (P-Well) 70, wherein N trap (N-Well) 60 is created on the left side in P type substrate (P-Sub) 80, p-well
(P-Well) 70 it is created on the right in P type substrate (P-Sub) 80, high concentration n-type doping (N+) 28, low concentration p-type are lightly doped
(PLDD) 20 it is placed in 60 top of N trap (N-Well), (PLDD) 20, N trap (N-Well) 60 and p-well (P- is lightly doped in low concentration p-type
Well) 70 equivalent PNP triode structure is constituted, high concentration n-type doping (N+) 24, high concentration p-type doping (P+) 26 are placed in p-well
(P-Well) 70 top, N trap (N-Well) 60, p-well (P-Well) 70 and high concentration n-type doping (N+) 24 constitute equivalent N PN tri-
Pole pipe structure；
In 28 left side of high concentration n-type doping (N+), shallow trench isolation layer (STI, Shallow Trench is set
Isolation) 10, high concentration n-type doping (N+) 28, low concentration p-type are isolated between (PLDD) 20 is lightly doped with N trap (N-Well) 60
(i.e. therebetween between be divided into 60 a part), the first floating gate 40 is placed above the N trap of the part, low concentration p-type is lightly doped
(PLDD) 20 right side is a part of N trap (N-Well) 60, and the width of part N trap (N-Well) 60 is A, high concentration N-type
It adulterates and uses shallow trench isolation layer (STI, Shallow Trench Isolation) between (N+) 24, high concentration p-type doping (P+) 26
10 isolation, high concentration p-type adulterate 26 right side (P+) and place shallow trench isolation layer (STI, Shallow Trench Isolation)
10, the left side of high concentration n-type doping (N+) 24 is a part of p-well (P-Well) 70, the width of the part p-well (P-Well) 70
For B；
Top and the high concentration N-type of (PLDD) 20 is lightly doped in the top of high concentration n-type doping (N+) 28, low concentration p-type
The top of the top, high concentration p-type doping (P+) 26 of adulterating (N+) 24 generates 4 metal silicides 30, in high concentration n-type doping
(N+) top for the N trap that the width on 20 right side (PLDD) is A is lightly doped above the p-well that the width in 24 left sides is B with low concentration p-type
The second floating gate 50 is placed, i.e., the second floating gate 50 is above N trap and p-well boundary；
30 extraction electrode of metal silicide of 28 top of high concentration n-type doping (N+) is connected to power supply Vdd, low concentration p-type
Anode of 30 extraction electrode of metal silicide of 20 top (PLDD) as grid constraint thyristor ESD device is lightly doped
Anode, the gold of the top of metal silicide 30 and high concentration p-type doping (P+) 26 of the top of high concentration n-type doping (N+) 24
Belong to that silicide 30 is connected and extraction electrode forms the cathode Cathode of grid constraint thyristor ESD device, cathode when use
It is grounded Vss.
As it can be seen that the grid of the prior art as shown in Figure 1 are constrained the high concentration P of jointed anode in thyristor by the present invention
Type doping (P+) 20 replaces with the low concentration p-type lightly doped district (PLDD) 20 being lightly doped, the low concentration p-type lightly doped district (PLDD)
20 are used as the grid constraint endoparasitic PNP of thyristor, and ((PLDD) 20/N trap (N-Well) 60/P trap is lightly doped in low concentration p-type
(P-Well) efficiency of the 70) emitter of triode, transmitting hole is reduced because of the reduction of p-type doping concentration itself, this drop
((PLDD) 20/N trap (N-Well) 60/P trap (P-Well) is lightly doped in low concentration p-type to the low endoparasitic PNP of thyristor
70) current gain (β) of triode, so that the maintenance voltage (Vh) of the thyristor is improved, in addition because without introducing Xiao
Special base junction simplifies manufacturing process while promoting its maintenance voltage, and low concentration p-type lightly doped district (PLDD) 20 because
Doping compared with light and diffusivity is lower, it is possible to shortening N trap (N-Well) 60 includes low concentration p-type lightly doped district (PLDD) 20
Distance A (plays the effect of electrically isolating), further saves chip area, so grid proposed by the invention constrain thyristor
It is more suitable for the antistatic protection design of Advanced CMOS Process integrated circuit.The device ruler of the grid constraint thyristor of the present invention
Very little A, B and PLDD (20) doping concentration (dosage range 1E12-1E15/cm2) its echo effect characteristic is determined together.
Fig. 5 is the step flow chart for the implementation method that a kind of grid of the present invention constrain thyristor ESD device.Such as Fig. 5 institute
Show, a kind of implementation method of grid constraint thyristor ESD device of the present invention includes the following steps:
Step 501, semi-conductive substrate is provided, in the specific embodiment of the invention, provides a P type substrate (P-Sub) 80.
Step 502, two traps, i.e. N trap (N-Well) 60 and p-well (P-Well) 70, In are generated in the semiconductor substrate
In the specific embodiment of the invention, N trap (N-Well) 60 and p-well (P-Well) 70, N trap are generated in P type substrate (P-Sub) 80
(N-Well) 60 it is created on 80 left side of P type substrate (P-Sub), p-well (P-Well) 70 is created on 80 right side of P type substrate (P-Sub).
Step 503, equivalent PNP triode structure is formed in N trap (N-Well) 60, and equivalent N PN tri- is formed in p-well 70
Pole pipe structure.Specifically, (PLDD) 20, which is lightly doped, in high concentration n-type doping (N+) 28, low concentration p-type is placed in N trap (N-
Well) 60 top, low concentration p-type are lightly doped (PLDD) 20, N trap (N-Well) 60 and p-well (P-Well) 70 and constitute equivalent PNP
Shallow trench isolation layer (STI, Shallow Trench is arranged in 28 left side of high concentration n-type doping (N+) in audion
Isolation) 10, high concentration n-type doping (N+) 28, low concentration p-type are isolated between (PLDD) 20 is lightly doped with N trap (N-Well) 60
(i.e. therebetween between be divided into 60 a part), the first floating gate 40 is placed above the N trap of the part, low concentration p-type is lightly doped
(PLDD) 20 right side is a part of N trap (N-Well) 60, and the width of part N trap (N-Well) 60 is A；By high concentration N
Type doping (N+) 24, high concentration p-type doping (P+) 26 are placed in 70 top of p-well (P-Well), N trap (N-Well) 60, p-well (P-
Well) 70 equivalent N PN audion, high concentration n-type doping (N+) 24, high concentration P are constituted with high concentration n-type doping (N+) 24
Type is isolated between adulterating (P+) 26 with shallow trench isolation layer (STI, Shallow Trench Isolation) 10, and high concentration p-type is mixed
Place shallow trench isolation layer (STI, Shallow Trench Isolation) 10, high concentration n-type doping (N in 26 right side miscellaneous (P+)
+) a part that 24 left side is p-well (P-Well) 70, the width of the part p-well (P-Well) 70 is B.
Step 504, top and the height of (PLDD) 20 are lightly doped in the top of high concentration n-type doping (N+) 28, low concentration p-type
The top of concentration N-dopant (N+) 24, the top of high concentration p-type doping (P+) 26 generate 4 metal silicides 30, in high concentration
Above the p-well that the width in 24 left side of n-type doping (N+) is B and the N that the width on 20 right side (PLDD) is A is lightly doped in low concentration p-type
The second floating gate 50 is placed in the top of trap, i.e., the second floating gate 50 is above N trap and p-well boundary；
Step 505,30 extraction electrode of metal silicide of 28 top of high concentration n-type doping (N+) is connected to power supply Vdd,
30 extraction electrode of metal silicide that 20 top (PLDD) is lightly doped in low concentration p-type constrains thyristor ESD device as the grid
The anode A node of part, metal silicide 30 and high concentration p-type doping (P+'s) 26 of the top of high concentration n-type doping (N+) 24
The metal silicide 30 of top is connected and extraction electrode forms the cathode Cathode that the grid constrain thyristor ESD device, makes
Used time minus earth Vss
In application, the cathode Cathode of the grid constraint thyristor ESD device of the present invention is connect for protection I/O port
Ground Vss, Vdd terminal (i.e. the metal silicide 30 of 28 top of high concentration n-type doping (N+)) connect supply voltage Vdd, anode
Anode is to external IO (input/output terminal)；For protection power source, can also connect after the grid constrain thyristor ESD device
Connect certain other ESD protective device to obtain the characteristic of needs, as shown in Figure 6.
In conclusion a kind of grid of present invention constraint thyristor ESD device and its implementation by by existing grid about
The high concentration p-type doping of the jointed anode of beam thyristor ESD device replaces with low concentration p-type lightly doped district (PLDD), energy
While promoting its maintenance voltage, simplify manufacturing process, reduces the boundary defect because introducing schottky junction, and reduce its contact
Resistance is more applicable for the antistatic protection design of Advanced CMOS Process integrated circuit.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Without departing from the spirit and scope of the present invention, modifications and changes are made to the above embodiments by field technical staff.Therefore,
The scope of the present invention, should be as listed in the claims.
Claims (10)
1. a kind of grid constrain thyristor ESD device, which is characterized in that the ESD device includes:
Semiconductor substrate (80)；
The N trap (60) and p-well (70) being created in the semiconductor substrate (80)；
High concentration n-type doping (28), low concentration p-type are lightly doped (20) and are placed in N trap (60) top, high concentration n-type doping (24), height
Concentration of P type doping (26) is placed in the p-well (70) top；
The top of (20) is lightly doped in the top of the high concentration n-type doping (28), low concentration p-type and the high concentration N-type is mixed
The top of miscellaneous (24), the top of high concentration p-type doping (26) generate metal silicide (30) respectively；
Metal silicide (30) extraction electrode above the high concentration n-type doping (28) is connected to connection power supply, described low dense
Metal silicide (30) extraction electrode above (20) is lightly doped as grid constraint thyristor ESD device in degree p-type
Above anode, the metal silicide (30) of the top of the high concentration n-type doping (24) and high concentration p-type doping (26)
Metal silicide (30) is connected and extraction electrode forms the cathode that the grid constrain thyristor ESD device.
2. a kind of grid as described in claim 1 constrain thyristor ESD device, it is characterised in that: the low concentration p-type is light
It adulterates (20), the N trap (60) and the p-well (70) and constitutes equivalent PNP triode structure.
3. a kind of grid as described in claim 1 constrain thyristor ESD device, it is characterised in that: the N trap (60), p-well
(70) equivalent N PN audion is constituted with the high concentration n-type doping (24).
4. a kind of grid as described in claim 1 constrain thyristor ESD device, it is characterised in that: the high concentration N-type is mixed
Shallow trench isolation layer (10) are set on the left of miscellaneous (28), benefit between (20) is lightly doped in the high concentration n-type doping (28), low concentration p-type
It is isolated with the N trap (60), the first floating gate (40) is placed above the N trap of the part, the right side of (20) is lightly doped in the low concentration p-type
Side is a part of the N trap (60), and the width of part N trap is A.
5. a kind of grid as claimed in claim 4 constrain thyristor ESD device, it is characterised in that: the high concentration N-type is mixed
Miscellaneous (24), high concentration p-type are isolated between adulterating (26) with shallow trench isolation layer (10), are put on the right side of the high concentration p-type doping (26)
It sets shallow trench isolation layer (10), is a part of the p-well (70) on the left of the high concentration n-type doping (24), the part p-well
Width is B.
6. a kind of grid as claimed in claim 5 constrain thyristor ESD device, it is characterised in that: the ESD device is returned
Stagnant performance characteristic is codetermined by the doping concentration that (20) are lightly doped in A, B and the low concentration p-type, and wherein A is 0.1~0.5um,
B is 0.1~0.5um, and doping concentration dosage range is 1E12-1E15/cm2。
7. a kind of grid as claimed in claim 5 constrain thyristor ESD device, it is characterised in that: in the high concentration N-type
Above the p-well that doping (24) left side width is B and the top for the N trap that the width on the right side of (20) is A is lightly doped in the low concentration p-type
Place the second floating gate (50).
8. a kind of implementation method of grid constraint thyristor ESD device, it is characterised in that: existing grid are constrained thyristor
The high concentration p-type doping of the jointed anode of ESD device replaces with low concentration p-type and (20) is lightly doped, and surface forms gold thereon
Belong to silicide (30), anode of the extraction electrode as grid constraint thyristor ESD device.
9. a kind of implementation method of grid constraint thyristor ESD device as claimed in claim 8, which is characterized in that described
Method includes:
Step 501, semi-conductive substrate (80) are provided；
Step 502, N trap (60) and p-well (70) are generated in the semiconductor substrate (80)；
Step 503, (20) are lightly doped in high concentration n-type doping (28), low concentration p-type and are placed in N trap (60) top, high concentration N-type
Doping (24), high concentration p-type doping (26) are placed in the p-well (70) top；
Step 504, the top of (20) and described highly concentrated is lightly doped in the top of the high concentration n-type doping (28), low concentration p-type
The top of the top, high concentration p-type doping (26) of spending n-type doping (24) generates metal silicide (30) respectively；
Step 505, metal silicide (30) extraction electrode above the high concentration n-type doping (28) is connected to connection electricity
Metal silicide (30) extraction electrode above (20) is lightly doped as grid constraint silicon control rectification in source, the low concentration p-type
The anode of device ESD device, metal silicide (30) and the high concentration p-type of the top of the high concentration n-type doping (24) are mixed
Metal silicide (30) above miscellaneous (26) is connected and extraction electrode forms the yin that the grid constrain thyristor ESD device
Pole.
10. a kind of implementation method of grid constraint thyristor ESD device as claimed in claim 9, it is characterised in that: described
Grid constrain minus earth when thyristor ESD device uses.
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| CN112071834A (en) * | 2020-09-25 | 2020-12-11 | 上海华力微电子有限公司 | Gate-constrained silicon controlled rectifier and implementation method thereof |
| CN112071836A (en) * | 2020-09-25 | 2020-12-11 | 上海华力微电子有限公司 | Gate-constrained silicon controlled rectifier and implementation method thereof |
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