CN110504254A - A kind of novel grid constraint thyristor ESD device and its implementation - Google Patents
A kind of novel grid constraint thyristor ESD device and its implementation Download PDFInfo
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 44
- 238000002955 isolation Methods 0.000 claims description 34
- 238000000605 extraction Methods 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000000694 effects Effects 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000012423 maintenance Methods 0.000 abstract description 8
- 230000007547 defect Effects 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000001737 promoting effect Effects 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
- H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
Abstract
The invention discloses a kind of novel grid constraint thyristor ESD device and its implementation, removed by the schottky junction that existing grid are constrained thyristor ESD device, and high concentration n-type doping is replaced with into low concentration N-type, (24) are lightly doped, and (24) upper section is lightly doped in the low concentration N-type and forms metal silicide (30), it is connected to the cathode of novel grid constraint thyristor ESD device, it can be while promoting maintenance voltage, simplify manufacturing process, the boundary defect because introducing schottky junction is reduced, and reduces its contact resistance.
Description
Technical field
The present invention relates to semiconductor integrated circuit technology fields, constrain thyristor more particularly to a kind of novel grid
ESD (Electro-Static Discharge, Electro-static Driven Comb) device and its implementation.
Background technique
In integrated circuit antistatic protection design field, antistatic protection design protection window is generally dependent on operating voltage
With the gate oxide thickness of internal protected circuit, the operating voltage with general Advanced CMOS Process integrated circuit is 1V or so,
Gate oxide thickness is about the antistatic protection design window of the Advanced CMOS Process integrated circuit for 14A (angstrom, 0.1nm)
Usually between 1.2V~2.8V, and typical GGNMOS (Grounded-Gate NMOS) electrostatic protection in Advanced CMOS Process
The trigger voltage (Vt1) of the echo effect of device is commonly greater than 2.8V, so industry first proposed a kind of grid as shown in Figure 1
Constraint thyristor attempts to solve this problem.
As shown in Figure 1, existing grid constraint thyristor ESD device include multiple shallow trench isolation layers (STI,
Shallow Trench Isolation) 10, high concentration n-type doping (N+) 28, the doping of high concentration p-type (P+) 20, high concentration N-type
Adulterate (N+) 24, high concentration p-type doping (P+) 26, N trap (N-Well) 60, p-well (P-Well) 70, P type substrate (P-sub) 80,
The metal silicide (Silicide) 30 of first floating gate 40, second grid 50 and multiple connecting doped areas and electrode.
Entire ESD device is placed in P type substrate (P-sub) 80, generates a N trap on 80 left side of P type substrate (P-sub)
(N-Well) 60, a p-well (P-Well) 70, high concentration n-type doping (N+) 28, height are generated on 80 the right of P type substrate (P-sub)
Concentration of P type doping (P+) 20 is placed in 60 top of N trap (N-Well), and high concentration p-type adulterates (P+) 20, N trap (N-Well) 60 and P
Trap (P-Well) 70 constitutes equivalent PNP triode structure, and high concentration n-type doping (N+) 24, high concentration p-type doping (P+) 26 are placed in
70 top of p-well (P-Well), N trap (N-Well) 60, p-well (P-Well) 70 and high concentration n-type doping (N+) 24 constitute equivalent N PN
Audion；
Shallow trench isolation layer (STI, Shallow Trench is placed in 28 left side of high concentration n-type doping (N+)
Isolation) 10, between high concentration n-type doping (N+) 28, high concentration p-type doping (P+) 20 (i.e. with the isolation of N trap (N-Well) 60
60 a part is divided between therebetween), the first floating gate 40 is placed above the N trap of the part, high concentration p-type adulterates the right side of (P+) 20
Side is a part of N trap (N-Well) 60, and the width of part N trap (N-Well) 60 is A, high concentration n-type doping (N+) 24, height
Concentration of P type is isolated between adulterating (P+) 26 with shallow trench isolation layer (STI, Shallow Trench Isolation) 10, high concentration P
Type adulterates 26 right side (P+) and places shallow trench isolation layer (STI, Shallow Trench Isolation) 10, and high concentration N-type is mixed
The left side of miscellaneous (N+) 24 is a part of p-well (P-Well) 70, and the width of the part p-well (P-Well) 70 is B；
The top of (P+) 20, high concentration n-type doping (N are adulterated in the top of high concentration n-type doping (N+) 28, high concentration p-type
+) 24 top, high concentration p-type doping (P+) 26 top generate 4 metal silicides 30, in high concentration n-type doping (N+) 24
Place second gate in the top for the N trap that width above the p-well that the width in left side is B and on the right side of high concentration p-type doping (P+) 20 is A
Pole 50, i.e. second grid 50 above N trap and p-well boundary and do not cover high concentration p-type doping (P+) 20 and high concentration N-type mix
Miscellaneous (N+) 24；
30 extraction electrode of metal silicide of 28 top of high concentration n-type doping (N+) is connected to power supply Vdd, high concentration p-type
Adulterate anode of 30 extraction electrode of metal silicide of 20 top (P+) as novel grid constraint thyristor ESD device
The metal silicide 30 and high concentration p-type of the top of Anode, second grid 50 and high concentration n-type doping (N+) 24 adulterate (P
+) metal silicide 30 of 26 top is connected and extraction electrode forms the cathode of existing grid constraint thyristor ESD device
Cathode, minus earth Vss when use.
It is surveyed as a result, it has been found that its maintenance voltage (Vh) is too low, only 1.2V or so.
Currently, industry also then proposes embedded Xiao such as Fig. 2 on the basis of grid as shown in Figure 1 constrain thyristor
The modified grid of special base junction constrain thyristor to promote its maintenance voltage (Vh), i.e., on 24 left side of high concentration n-type doping (N+)
The top of the p-well (P-Well) 70 of side directly forms metal layer 22 to form schottky junction (Schottky Junction), in gold
The top for the p-well (P-Well) 70 that the width in the left side of category layer 22 is B-S and the width on the right side of high concentration p-type doping (P+) 20 are
The top of the N trap (N-Well) 60 of A is only second grid (floating gate) 50.
As the grid of Fig. 1 constrain the echo effect characteristic of thyristor and the modified grid constraint thyristor such as Fig. 2
As shown in figure 3, left side be Fig. 1 characteristic curve, right side be Fig. 2 characteristic curve, by Fig. 3 it can be concluded that, such as embedded Xiao of Fig. 2
The maintenance voltage of its echo effect can be promoted to 2V from 1.2V by the modified grid constraint thyristor of special base junction, and be triggered
Voltage is then controlled in 2.4V, still is below 2.8V, so the grid constraint thyristor such as the embedded schottky junction of Fig. 2 is more applicable
It is designed in the antistatic protection of Advanced CMOS Process integrated circuit.But the introducing of schottky junction causes its technique more complicated, separately
Outer metal-semiconductor contact interface is readily incorporated boundary defect, and the contact resistance of schottky junction is higher.
Summary of the invention
In order to overcome the deficiencies of the above existing technologies, purpose of the present invention is to provide a kind of constraint silicon control of novel grid is whole
Device ESD device and its implementation are flowed, to simplify manufacturing process while promoting maintenance voltage, is reduced because introducing Schottky
The boundary defect of knot, and reduce its contact resistance.
In view of the above and other objects, the present invention proposes a kind of novel grid constraint thyristor ESD device, the ESD
Device includes:
Semiconductor substrate (80)；
The N trap (60) and p-well (70) being created in the semiconductor substrate (80)；
High concentration n-type doping (28), high concentration p-type doping (20) are placed in N trap (60) top, and low concentration N-type is lightly doped
(24), high concentration p-type doping (26) is placed in the p-well (70) top, and (24) are lightly doped in the low concentration N-type, high concentration p-type is mixed
Between miscellaneous (26) with shallow trench isolation layer (10) be isolated, the low concentration N-type be lightly doped (24) left side be the p-well (70) one
Part；
It is gently mixed in the top of the high concentration n-type doping (28), the top of high concentration p-type doping (20), low low concentration N-type
The neighbouring high concentration p-type adulterates (26) part above miscellaneous (24), the top of high concentration p-type doping (26) generates metallic silicon respectively
Compound (30), the second floating gate (50) is above the N trap and p-well boundary and (24) are lightly doped in the covering low concentration N-type
A part；
Metal silicide (30) extraction electrode above the high concentration n-type doping (28) is connected to power supply, described highly concentrated
Metal silicide (30) extraction electrode spent above p-type doping (20) constrains thyristor ESD device as the novel grid
Anode, the low concentration N-type is lightly doped the metal silicide (30) above (24) and adulterates the upper of (26) with the high concentration p-type
The metal silicide (30) of side is connected and extraction electrode forms the cathode that the novel grid constrains thyristor ESD device.
Preferably, the high concentration p-type doping (20), the N trap (60) and the p-well (70) constitute equivalent PNP tri-
Pole pipe structure.
Preferably, the N trap (60), p-well (70) and low concentration N-type are lightly doped (24) and constitute equivalent N PN audion.
Preferably, shallow trench isolation layer (10) are set on the left of the high concentration n-type doping (28), the high concentration N-type is mixed
Miscellaneous (28), high concentration p-type are isolated between adulterating (20) using the N trap (60), place the first floating gate above the N trap of the part
(40), the right side of the high concentration p-type doping (20) is a part of the N trap (60), and the width of part N trap is A.
Preferably, shallow trench isolation layer (10) are placed on the right side of the high concentration p-type doping (26), the low concentration N-type is light
The width for adulterating (24) is S, and the left side that (24) are lightly doped in the low concentration N-type is a part of p-well (70), the part p-well
Width is B, and right side is shallow trench isolation layer (10).
Preferably, the echo effect characteristic of the ESD device is codetermined by A, B and S, and wherein A is 0.1~0.5um, B
It is 0.1~1um for 0.1~0.5um, S.
Preferably, minus earth when the novel grid constraint thyristor ESD device uses.
In order to achieve the above objectives, the present invention also provides a kind of novel grid constraint thyristor ESD device implementation method,
The schottky junction of existing novel grid constraint thyristor ESD device is removed, and high concentration n-type doping is replaced with low dense
Degree N-type is lightly doped (24), and (24) upper section is lightly doped in the low concentration N-type and forms metal silicide (30), extraction electrode
It is connected to the cathode of novel grid constraint thyristor ESD device.
Preferably, which comprises
Step 501, semi-conductive substrate (80) are provided；
Step 502, N trap (60) and p-well (70) are generated in the semiconductor substrate (80)；
Step 503, high concentration n-type doping (28), high concentration p-type doping (20) are placed in N trap (60) top, low concentration N
(24) are lightly doped in type, high concentration p-type doping (26) is placed in the p-well (70) top, and (24), height is lightly doped in the low concentration N-type
Concentration of P type is isolated between adulterating (26) with shallow trench isolation layer, and the other side is a part of the p-well (70)；
Step 504, in the top of the high concentration n-type doping (28), the top of high concentration p-type doping (20), low concentration N
The upper section of (24) is lightly doped in type, the top of high concentration p-type doping (26) generates metal silicide (30) respectively, and second is floated
Grid (50) are formed in above the N trap and p-well boundary and a part of (24) is lightly doped in the covering low concentration N-type；
Step 505, metal silicide (30) extraction electrode above the high concentration n-type doping (28) is connected to electricity
Source, it is whole as novel grid constraint silicon control that the high concentration p-type adulterates metal silicide (30) extraction electrode above (20)
The anode of device ESD device is flowed, metal silicide (30) and the high concentration p-type above (24) is lightly doped in the low concentration N-type
The metal silicide (30) for adulterating the top of (26) is connected and extraction electrode forms novel grid constraint thyristor ESD device
Cathode.
Preferably, minus earth when the novel grid constraint thyristor ESD device uses.
Compared with prior art, a kind of novel grid constraint thyristor ESD device of the present invention and its implementation pass through
The schottky junction of existing grid constraint thyristor is removed, the N+ knot of heavy doping is replaced with into the NLDD being lightly doped and is tied, in this
NLDD ties surface and is formed together metal silicide, and extraction electrode is connected to the cathode of thyristor, can promote its dimension
While holding voltage, simplify manufacturing process, reduces the boundary defect because introducing schottky junction, and reduce its contact resistance, more
Antistatic protection suitable for Advanced CMOS Process integrated circuit designs.
Detailed description of the invention
Fig. 1 is the schematic diagram of the ESD device of a prior art；
Fig. 2 is the schematic diagram of the ESD device of another prior art；
Fig. 3 is that grid constrain thyristor echo effect characteristic and schottky junction relation schematic diagram in the prior art；
Fig. 4 is the device junction composition for the preferred embodiment that a kind of novel grid of the present invention constrains thyristor ESD device；
Fig. 5 is the step flow chart for the implementation method that a kind of novel grid of the present invention constrains thyristor ESD device；
Fig. 6 is application scenarios schematic diagram of the invention.
Specific embodiment
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand further advantage and effect of the invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from
Various modifications and change are carried out under spirit of the invention.
Fig. 4 is the device junction composition for the preferred embodiment that a kind of novel grid of the present invention constrains thyristor ESD device.Such as
Shown in Fig. 4, a kind of novel grid of the present invention constrains thyristor ESD device, comprising: multiple shallow trench isolation layers (STI,
Shallow Trench Isolation) 10, high concentration n-type doping (N+) 28, the doping of high concentration p-type (P+) 20, low concentration N-type
(NLDD) 24, the doping of high concentration p-type (P+) 26, N trap (N-Well) 60, p-well (P-Well) 70, P type substrate (P-sub) is lightly doped
80, the metal silicide (Silicide) 30 of the first floating gate 40, the second floating gate 50 and multiple connecting doped areas and electrode.
Entire ESD device is placed in P type substrate (P-Sub) 80, and two traps: N trap are generated in P type substrate (P-Sub) 80
(N-Well) 60 and p-well (P-Well) 70, wherein N trap (N-Well) 60 is created on the left side in P type substrate (P-Sub) 80, p-well
(P-Well) 70 it is created on the right in P type substrate (P-Sub) 80, high concentration n-type doping (N+) 28, high concentration p-type adulterate (P
+) 20 it is placed in 60 top of N trap (N-Well), high concentration p-type adulterates (P+) 20, N trap (N-Well) 60 and p-well (P-Well) 70
Equivalent PNP triode structure is constituted, (NLDD) 24 is lightly doped in low concentration N-type, high concentration p-type doping (P+) 26 is placed in p-well (P-
Well) 70 top, N trap (N-Well) 60, p-well (P-Well) 70 and low concentration N-type are lightly doped (NLDD) 24 and constitute equivalent N PN tri-
Pole pipe structure；
In 28 left side of high concentration n-type doping (N+), shallow trench isolation layer (STI, Shallow Trench is set
Isolation) 10, between high concentration n-type doping (N+) 28, high concentration p-type doping (P+) 20 (i.e. with the isolation of N trap (N-Well) 60
60 a part is divided between therebetween), the first floating gate 40 is placed above the N trap of the part, high concentration p-type adulterates the right side of (P+) 20
Side is a part of N trap (N-Well) 60, and the width of part N trap (N-Well) 60 is A, and (NLDD) is lightly doped in low concentration N-type
24, it is isolated between high concentration p-type doping (P+) 26 with shallow trench isolation layer (STI, Shallow Trench Isolation) 10, it is high
Concentration of P type adulterates 26 right side (P+) and places shallow trench isolation layer (STI, Shallow Trench Isolation) 10, low concentration N
The width that (NLDD) 24 is lightly doped in type is S, and the left side that (NLDD) 24 is lightly doped in low concentration N-type is one of p-well (P-Well) 70
Point, the width of the part p-well (P-Well) 70 is B；
It is lightly doped in the top of high concentration n-type doping (N+) 28, the top of high concentration p-type doping (P+) 20, low concentration N-type
(NLDD) 24 right side above, high concentration p-type doping (P+) 26 top generate 4 metal silicides 30, it is light in low concentration N-type
It adulterates above the left side of (NLDD) 24 and adulterates 20 right side (P+) with the width on the left of it for the p-well top of B and high concentration p-type
Width be A N trap top place the second floating gate 50, i.e. the second floating gate 50 above N trap and p-well boundary and covering it is low dense
The a part in 24 left side (NLDD) is lightly doped in degree N-type；
30 extraction electrode of metal silicide of 28 top of high concentration n-type doping (N+) is connected to power supply Vdd, high concentration p-type
Adulterate anode of 30 extraction electrode of metal silicide of 20 top (P+) as novel grid constraint thyristor ESD device
The upper of metal silicide 30 and high concentration p-type doping (P+) 26 of the 24 right side top (NLDD) is lightly doped in Anode, low concentration N-type
The metal silicide 30 of side is connected and extraction electrode forms the cathode Cathode that the novel grid constrains thyristor ESD device,
Minus earth Vss when use.
As it can be seen that the present invention incites somebody to action on the basis of the grid of existing embedded schottky junction constrain thyristor (as shown in Figure 2)
The schottky junction of existing grid constraint thyristor (as shown in Figure 2) removes, and the N+ knot 24 of heavy doping is replaced with and is gently mixed
Miscellaneous NLDD knot 24 is formed together metal silicide in 24 upper surface of NLDD knot, and extraction electrode is connected to silicon control rectification
The cathode of device, as the endoparasitic NPN of thyristor, ((NLDD) 24/P trap is lightly doped in low concentration N-type to the NLDD knot 24
(P-Well) 70/N trap (N-Well) 60) triode emitter, the quantity of launching electronics can be because of itself dopant dose
Decline and reduce, it reduce the current gain of the endoparasitic NPN triode of thyristor (β), this equally can be improved
The maintenance voltage (Vh) of thyristor；In addition low concentration N-type is lightly doped (NLDD) knot 24 and causes because its doping concentration is lower
The heat diffusivity of foreign atom is smaller, so p-well (P-Well) 70 includes the crucial ruler that (NLDD) knot 24 is lightly doped in low concentration N-type
Very little B can be designed smaller, this advantageously reduces the trigger voltage (Vt1) of the thyristor to a certain extent, and there are also this
Itd is proposed novel grid constraint (Gate Bounded) thyristor is invented to remove the schottky junction of unconventional CMOS technology,
So its manufacturing process can be simplified while promoting its maintenance voltage, the boundary defect because introducing schottky junction is reduced, and drop
Its low contact resistance, so novel grid constraint thyristor proposed by the invention is more suitable for the integrated electricity of Advanced CMOS Process
The antistatic protection on road designs.Device size A, B and S of the novel grid constraint thyristor of the present invention determine its time together
Stagnant performance characteristic.
Fig. 5 is the step flow chart for the implementation method that a kind of novel grid of the present invention constrains thyristor ESD device.Such as figure
Shown in 5, a kind of implementation method of novel grid constraint thyristor ESD device of the present invention includes the following steps:
Step 501, semi-conductive substrate is provided, in the specific embodiment of the invention, provides a P type substrate (P-Sub) 80.
Step 502, two traps, i.e. N trap (N-Well) 60 and p-well (P-Well) 70, In are generated in the semiconductor substrate
In the specific embodiment of the invention, N trap (N-Well) 60 and p-well (P-Well) 70, N trap are generated in P type substrate (P-Sub) 80
(N-Well) 60 it is created on 80 left side of P type substrate (P-Sub), p-well (P-Well) 70 is created on 80 right side of P type substrate (P-Sub).
Step 503, equivalent PNP triode structure is formed in N trap (N-Well) 60, and equivalent N PN tri- is formed in p-well 70
Pole pipe structure.Specifically, high concentration n-type doping (N+) 28, high concentration p-type doping (P+) 20 are placed in N trap (N-Well) 60
Top, high concentration p-type adulterate (P+) 20, N trap (N-Well) 60 and p-well (P-Well) 70 and constitute equivalent PNP triode structure,
In 28 left side of high concentration n-type doping (N+), shallow trench isolation layer (STI, Shallow Trench Isolation) 10 is set, it is high
Concentration N-dopant (N+) 28, high concentration p-type doping (P+) 20 between with N trap (N-Well) 60 be isolated (i.e. therebetween between be divided into 60
A part), the first floating gate 40 is placed above the N trap of the part, the right side that high concentration p-type adulterates (P+) 20 is N trap (N-Well)
60 a part, the width of part N trap (N-Well) 60 are A；(NLDD) 24 is lightly doped in low concentration N-type, high concentration p-type is mixed
Miscellaneous (P+) 26 is placed in 70 top of p-well (P-Well), and N trap (N-Well) 60, p-well (P-Well) 70 are lightly doped with low concentration N-type
(NLDD) 24 equivalent N PN audion is constituted, low concentration N-type is lightly doped between (NLDD) 24, high concentration p-type doping (P+) 26 and uses
Shallow trench isolation layer (STI, Shallow Trench Isolation) 10 is isolated, and high concentration p-type is adulterated 26 right side (P+) and placed
Shallow trench isolation layer (STI, Shallow Trench Isolation) 10, the width that (NLDD) 24 is lightly doped in low concentration N-type are
A part that the left side of (NLDD) 24 is p-well (P-Well) 70 is lightly doped in S, low concentration N-type, the part p-well (P-Well) 70
Width is B；
Step 504, in the top of high concentration n-type doping (N+) 28, the top of high concentration p-type doping (P+) 20, low concentration N
Type is lightly doped above the right side of (NLDD) 24, the top of high concentration p-type doping (P+) 26 generates 4 metal silicides 30, low
Concentration N-type is lightly doped above the left side of (NLDD) 24 and adulterates above p-well of B with high concentration p-type with the width on the left of it
(P+) the second floating gate 50 is placed in the top for the N trap that the width on 20 right sides is A, i.e., the second floating gate 50 is above N trap and p-well boundary
And cover a part that 24 left side (NLDD) is lightly doped in low concentration N-type；
Step 505,30 extraction electrode of metal silicide of 28 top of high concentration n-type doping (N+) is connected to power supply Vdd,
30 extraction electrode of metal silicide that high concentration p-type adulterates 20 top (P+) constrains thyristor ESD device as the novel grid
The anode A node of part, the metal silicide 30 of the 24 right side top (NLDD) is lightly doped in low concentration N-type and high concentration p-type adulterates (P
+) metal silicide 30 of 26 top is connected and extraction electrode forms the cathode of novel grid constraint thyristor ESD device
Cathode, minus earth Vss when use.
In application, for protection I/O port, by the cathode of the novel grid constraint thyristor ESD device of the present invention
Cathode is grounded Vss, and Vdd terminal (i.e. the metal silicide 30 of 28 top of high concentration n-type doping (N+)) meets supply voltage Vdd,
Its anode A node is to external IO (input/output terminal)；For protection power source, novel grid constraint thyristor ESD device it
Certain other ESD protective device can also be connected afterwards to obtain the characteristic of needs, as shown in Figure 6.
In conclusion a kind of novel grid of present invention constraint thyristor ESD device and its implementation are by will be existing
The schottky junction of grid constraint thyristor removes, and the N+ knot of heavy doping is replaced with the NLDD being lightly doped and is tied, is tied in the NLDD
Upper surface is formed together metal silicide, and extraction electrode is connected to the cathode of thyristor, can promote its maintenance voltage
While, simplify manufacturing process, reduces the boundary defect because introducing schottky junction, and reduce its contact resistance, in addition low concentration N
(NLDD) knot 24 is lightly doped in type causes the heat diffusivity of foreign atom smaller because its doping concentration is lower, so p-well (P-
Well) the 70 critical size B that (NLDD) knot 24 is lightly doped comprising low concentration N-type can design smaller, this is to a certain extent
The trigger voltage (Vt1) for advantageously reducing the thyristor, is more applicable for the antistatic of Advanced CMOS Process integrated circuit
Design protection.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Without departing from the spirit and scope of the present invention, modifications and changes are made to the above embodiments by field technical staff.Therefore,
The scope of the present invention, should be as listed in the claims.
Claims (10)
1. a kind of novel grid constrains thyristor ESD device, which is characterized in that the ESD device includes:
Semiconductor substrate (80)；
The N trap (60) and p-well (70) being created in the semiconductor substrate (80)；
High concentration n-type doping (28), high concentration p-type doping (20) are placed in N trap (60) top, and (24), height is lightly doped in low concentration N-type
Concentration of P type doping (26) is placed in the p-well (70) top, and (24), high concentration p-type doping (26) is lightly doped in the low concentration N-type
Between with shallow trench isolation layer (10) be isolated, the low concentration N-type be lightly doped (24) left side be the p-well (70) a part；
It is lightly doped in the top of the high concentration n-type doping (28), the top of high concentration p-type doping (20), low low concentration N-type
(24) the neighbouring high concentration p-type in top adulterates (26) part, the top of high concentration p-type doping (26) generates metal silication respectively
Object (30), the second floating gate (50) is above the N trap and p-well boundary and the one of (24) is lightly doped in the covering low concentration N-type
Part；
Metal silicide (30) extraction electrode above the high concentration n-type doping (28) is connected to power supply, the high concentration p-type
Adulterate sun of metal silicide (30) extraction electrode as novel grid constraint thyristor ESD device above (20)
Metal silicide (30) and the top of high concentration p-type doping (26) above (24) is lightly doped in pole, the low concentration N-type
Metal silicide (30) is connected and extraction electrode forms the cathode that the novel grid constrains thyristor ESD device.
2. a kind of novel grid as described in claim 1 constrains thyristor ESD device, it is characterised in that: the high concentration P
Type adulterates (20), the N trap (60) and the p-well (70) and constitutes equivalent PNP triode structure.
3. a kind of novel grid as described in claim 1 constrains thyristor ESD device, it is characterised in that: the N trap
(60), p-well (70) and low concentration N-type are lightly doped (24) and constitute equivalent N PN audion.
4. a kind of novel grid as described in claim 1 constrains thyristor ESD device, it is characterised in that: the high concentration N
Type, which adulterates, is arranged shallow trench isolation layer (10) on the left of (28), between the high concentration n-type doping (28), high concentration p-type doping (20)
It is isolated using the N trap (60), is placed above the N trap of the part the first floating gate (40), the right side of the high concentration p-type doping (20)
Side is a part of the N trap (60), and the width of part N trap is A.
5. a kind of novel grid as claimed in claim 4 constrains thyristor ESD device, it is characterised in that: the high concentration P
Type adulterates and places shallow trench isolation layer (10) on the right side of (26), and the width that (24) are lightly doped in the low concentration N-type is S, described low dense
The left side that (24) are lightly doped in degree N-type is a part of p-well (70), and the width of the part p-well is B, and right side is shallow trench isolation layer
(10)。
6. a kind of novel grid as claimed in claim 5 constrains thyristor ESD device, it is characterised in that: the ESD device
Echo effect characteristic by A, B and S codetermine, wherein A be 0.1~0.5um, B be 0.1~0.5um, S be 0.1~1um.
7. a kind of novel grid as claimed in claim 6 constrains thyristor ESD device, it is characterised in that: the novel grid
Constrain minus earth when thyristor ESD device uses.
8. a kind of implementation method of novel grid constraint thyristor ESD device, it is characterised in that: constrain existing novel grid
The schottky junction and high concentration n-type doping of thyristor ESD device replace with low concentration N-type and (24) are lightly doped, and low in this
Concentration N-type is lightly doped (24) upper section and forms metal silicide (30), and extraction electrode is as novel grid constraint silicon control rectification
The cathode of device ESD device.
9. a kind of implementation method of novel grid constraint thyristor ESD device as claimed in claim 8, which is characterized in that
The described method includes:
Step 501, semi-conductive substrate (80) are provided；
Step 502, N trap (60) and p-well (70) are generated in the semiconductor substrate (80)；
Step 503, high concentration n-type doping (28), high concentration p-type doping (20) are placed in N trap (60) top, low concentration N-type is light
Doping (24), high concentration p-type doping (26) are placed in the p-well (70) top, and (24), high concentration P is lightly doped in the low concentration N-type
Type is isolated between adulterating (26) with shallow trench isolation layer, and the other side is a part of the p-well (70)；
Step 504, light in the top of the high concentration n-type doping (28), the top of high concentration p-type doping (20), low concentration N-type
The top of the upper section, high concentration p-type doping (26) that adulterate (24) generates metal silicide (30) respectively, by the second floating gate
(50) it is formed in above the N trap and p-well boundary and a part of (24) is lightly doped in the covering low concentration N-type；
Step 505, metal silicide (30) extraction electrode above the high concentration n-type doping (28) is connected to power supply, institute
It states metal silicide (30) extraction electrode above high concentration p-type doping (20) and constrains thyristor as the novel grid
Metal silicide (30) and high concentration p-type doping above (24) is lightly doped in the anode of ESD device, the low concentration N-type
(26) metal silicide (30) of top is connected and extraction electrode forms the yin that the novel grid constrains thyristor ESD device
Pole.
10. a kind of implementation method of novel grid constraint thyristor ESD device as claimed in claim 9, it is characterised in that:
Minus earth when the novel grid constraint thyristor ESD device uses.
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