US20120153347A1 - ESD clamp with auto biasing under high injection conditions - Google Patents
ESD clamp with auto biasing under high injection conditions Download PDFInfo
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- US20120153347A1 US20120153347A1 US12/928,715 US92871510A US2012153347A1 US 20120153347 A1 US20120153347 A1 US 20120153347A1 US 92871510 A US92871510 A US 92871510A US 2012153347 A1 US2012153347 A1 US 2012153347A1
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- 238000002347 injection Methods 0.000 title description 5
- 239000007924 injection Substances 0.000 title description 5
- 230000009977 dual effect Effects 0.000 claims abstract description 23
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
Definitions
- the invention relates to Electrostatic Discharge (ESD) devices.
- ESD Electrostatic Discharge
- the invention relates to dual direction ESD solutions.
- ESD Electrostatic Discharge
- FIG. 1 shows a section through a DIAC formed in a P-substrate 100 .
- An N-well 102 is formed in the substrate 100
- an R-well 104 is in turn formed in the N-well 102 .
- a P+ region 110 and an N+ region 112 are formed in the R-well 104 , and a connected together to define an anode.
- a second P+ region 120 and N+ region 122 are formed in a P-well in the substrate 100 and are connected together to define a cathode.
- Another N+ region 130 is formed in the N-well 102 and a contact region to the P-substrate is provided by another P+ region 132 .
- FIG. 2 A multi-finger NPN is shown in FIG. 2 , with the NPN structures connected back to back as shown in the corresponding schematic circuit diagram of FIG. 3 .
- the NPN structures comprise N-emitters 200 formed on P-type bases 202 , which are in turn formed on top of an epitaxial region 204 .
- An N-buried layer (NBL) 210 is formed in the epi 204 .
- NBL N-buried layer
- NPN bipolar junction transistors provide a high holding voltage but saturates at high current levels.
- the NPN BJT-based dual direction clamps be integrated in a relatively large footprint.
- SCR devices are capable of providing higher currents than NPN BJTs due to double injection, however they have lower holding voltages.
- the present invention provides for a hybrid BJT-BSCR dual direction clamp that allows the current-voltage characteristics to be controlled.
- the clamp is implemented using a selective base epitaxial region in which an element other than silicon is selectively added to the epitaxial region to define a base epitaxial region, e.g. silicon germanium (SiGe) base epitaxial region (SiGe base epi).
- SiGe base epi or other base epi having an element other than silicon added to the epitaxial region will be referred to as a selective base epi.
- a dual direction ESD protection circuit comprising multiple base-emitter regions with a shared sub-collector defining a multi-finger NPN, and multiple P+ diffusion regions, at least one of the P+ diffusion regions being connected to one or more base-emitter regions and to a pad, and at least one other of the P+ diffusion regions being connected to one or more other base-emitter regions and to ground, the bases of the base-emitter regions comprising selective base epi regions.
- the P+ diffusion regions may comprise P+ diffusion fingers or P+ diffusion rings.
- the multi-finger NPN may comprise SiGe base epi regions.
- the base-emitter regions connected to the pad may comprise an emitter connected directly to the pad and a base connected to the pad via a resistor.
- the base-emitter regions connected to ground may comprise an emitter connected directly to ground and a base connected to ground via a resistor.
- a dual direction ESD protection circuit comprising at least one first NPN BJT and at least one second NPN BJT, the NPN BJTs sharing a common collector region and having a base and an emitter, wherein the base comprises a selective base epitaxial region, the circuit further comprising at least one first P+ diffusion region connected to the base and emitter of the at least one first NPN BJT, and at least on second P+ diffusion region connected to the base and emitter region of the at least one to second NPN BJT.
- the P+ diffusion regions may comprise P+ diffusion fingers or P+ diffusion rings.
- the NPN BJTs may comprise a multi-finger SiGe BJT.
- the emitter and base of the at least one first NPN BJT may be connected to a high voltage rail and the emitter and base of the at least one second NPN BJT may be connected to ground.
- the base of the at least one first NPN BJT may be connected to the high voltage rail via a first resistor, and the base of the at least one second NPN BJT may be connected to ground via a second resistor.
- the at least one first P+ diffusion region may be formed in an N-type region to define a first diode, and the at least one second P+ diffusion region may be formed in an N-type region to define a second diode.
- the N-type regions may comprise a shared N-epitaxial region.
- a method of controlling the current-voltage curve of a dual direction protection circuit that includes multiple base-emitter regions with a shared collector defining a multi-finger NPN, and multiple P+ diffusion regions, at least one of the P+ diffusion regions being connected to one or more base-emitter regions and to a pad, and at least one other of the P+ diffusion regions being connected to one or more other base-emitter regions and to ground, wherein the base-emitter region includes a selective base epi region, the method comprising adjusting at least one of, the number of P+ diffusion regions connected to the one or more base-emitter regions and to the pad, the number of P+ diffusion regions connected to the one or more base-emitter regions and to ground, the number of base-emitter regions connected to the pad, the number of base-emitter regions connected to ground, and the distance between one or more of the P+ regions and one or more of the base-emitter regions.
- the base-emitter regions connected to the pad may comprise an emitter connected directly to the pad and a base connected to the pad via at least one first resistor
- the base-emitter regions connected to ground may comprise an emitter connected directly to ground and a base connected to ground via at least one second resistor, the method comprising adjusting at least one of, at least one first resistor value, and at least one second resistor value.
- the selective base epi region may comprise a SiGe base epi region.
- FIG. 1 is a cross-section through a prior art DIAC
- FIG. 2 is a cross-section through a prior art back to back NPN clamp with shared sub-collector
- FIG. 3 a circuit diagram of the clamp of FIG. 2 ;
- FIG. 4 shows a cross-section through one embodiment of an ESD protection circuit of the invention
- FIG. 5 shows a schematic circuit diagram of an ESD protection circuit of the invention
- FIG. 6 shows a top view of one embodiment of an ESD protection circuit of the invention.
- FIG. 7 shows a cross-section through another embodiment of an ESD protection circuit of the invention.
- the present invention defines a dual direction ESD protection circuit that can readily be adjusted to achieve different current-voltage (I-V) characteristics.
- I-V current-voltage
- the holding voltage and on-state resistance can be adjusted.
- FIG. 4 shows a cross-section through one embodiment of an ESD protection circuit of the invention, which includes an NPN BJT that has two base-emitter fingers and a common sub-collector.
- the base-emitter fingers comprise a first emitter 400 and a first base 402 connected to a high voltage rail or pad 404 , and a second emitter 410 and second base 412 connected to ground 406 .
- the common sub-collector is defined by an N-epitaxial region 420 , which in this embodiment includes selective SiGe epitaxial regions to define SiGe base epitaxial regions below bases 402 , 412 .
- the SiGe base epi regions provide a bandgap that is different from pure silicon and allows for a very high speed NPN with Ft over 300 GHz.
- the remaining epitaxial region 420 is N-doped to define an N-epi sub-collector for the BJT.
- an n-buried layer (NBL) 422 is formed in the epi, leaving epitaxial region 424 below the NBL.
- the epi region 424 is p-doped.
- a first P+ region 430 is connected to the pad 404 .
- a second P+ region 432 is connected to ground 406 .
- FIG. 5 A schematic circuit diagram of the circuit of FIG. 4 is shown in FIG. 5 .
- the first emitter 400 and base 402 are connected to the pad 404 , while the second emitter 410 and base 412 are connected to ground 406 .
- the first base 402 is connected to the pad 404 via a resistor 440
- the second base 412 is connected to ground via a resistor 442 .
- the shared sub-collector region (N-epi 420 ) is depicted in FIG. 5 by the connected collectors.
- the P+ region 430 formed in the N-epi defines a first diode 500
- the P+ region 432 formed in the N-epi defines a second diode 502
- the P+ region 432 forming the anode of the second diode 502 The diodes 500 , 502 share a common cathode as defined by the N-epi and as depicted by the connection between the diodes 500 , 502 in FIG. 5 .
- the upper diode 500 When a positive ESD pulse is applied to the pad 404 , the upper diode 500 is forward biased, thus providing a lower voltage on the collector of the upper NPN BJT 510 than the emitter 400 of NPN 510 .
- the base-collector junction of the lower transistor 512 is in turn reverse biased. At a certain voltage the base-collector junction of transistor 512 breaks down causing minority carriers in the base-collector junction, which allows current to flow through the upper diode 500 and the lower resistor 442 . The voltage drop across the resistor 442 opens the transistor 512 .
- the forward biased diode 500 provides additional injection of holes, which leads to the increase of the current and compensates for the space charge of carriers generated during avalanche multiplication in the base-collector junction, thus decreasing the holding voltage.
- the current-voltage (I-V) curve of the clamp can be controlled.
- the level of injection in each direction can be varied in different ways, including by varying the number of P+ fingers per NPN BJT finger, by varying the distribution of P+ fingers among the BJT fingers, by varying the distance between the P+ region (finger or ring) and the BJT finger, and by varying the value of the base resistor 442 (for a positive ESD pulse) or resistor 440 (for a negative ESD pulse). By varying one or more of these parameters, the SCR effect can be enhanced or suppressed.
- FIG. 6 shows a top view of one embodiment of an ESD protection circuit of the invention, which shows two different P+ region configurations.
- the ring-shaped P+ region 600 forms the anode of the upper diode 500 while the anode of the lower diode 502 is formed by a two P+ diffusion regions in the form of fingers 602 .
- the base-emitter fingers 604 are formed between the P+ fingers 602 in this embodiment.
- FIG. 7 Another embodiment of a dual direction ESD protection circuit of the invention is shown in FIG. 7 . Structurally it is similar to the circuit of FIG. 4 but the various regions are connected together differently to achieve different circuit performance.
- the circuit of FIG. 7 again includes an NPN BJT that has two base-emitter fingers and a common sub-collector.
- the base-emitter fingers comprise a first emitter 700 and a first base 702 connected to a high voltage rail or pad 704 , and a second emitter 710 and second base 712 connected to ground 706 .
- the common sub-collector is again defined by an N-epitaxial region 720 .
- an n-buried layer (NBL) 722 is formed in the N-epi 720 .
- a first P+ region 730 is connected to the pad 704 .
- a second P+ region 432 is connected to ground 706 .
- the BJTs are again capable of adopting bipolar SCR (BSCR) characteristics however, in contrast to the embodiment of FIG. 4 the P+ region (P+ SCR emitter region) is not adjacent to the base-emitter finger with which it forms a discharge circuit from pad to ground during a positive ESD pulse or from ground to pad during a negative ESD pulse.
- the current path is defined by the P+ region 732 and the resistor 740 opening up the NPN BJT defined by the emitter 700 and base 702 with sub-collector 720 .
- the emitter 700 and base 702 which are connected to the pad 704 are separated by a gap from the P+ region 732 , which is connected to the ground 706 .
- the SCR effect is partly suppressed due to the larger gap between the P+ BSCR emitter 732 and the corresponding BJT finger of emitter 700 and base 702 .
- the P+ region 730 is separated from the NPN 710 , 712 in this embodiment.
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Abstract
In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V characteristics are adjusted by including P+ regions to define SCR structures that are operable to sink positive and negative ESD pulses, and adjusting the layout and distances between regions and the number of regions.
Description
- The invention relates to Electrostatic Discharge (ESD) devices. In particular it relates to dual direction ESD solutions.
- One of the most challenging Electrostatic Discharge (ESD) problems involves dual direction protection.
- One approach that has been adopted in the past is the use of DIAC and ADIAC architectures, which have a compact, small footprint. However these devices are based on non-self-aligned BJT junctions and therefore don't always have good turn-on voltage. One such device is shown in
FIG. 1 , which shows a section through a DIAC formed in a P-substrate 100. An N-well 102 is formed in thesubstrate 100, and an R-well 104 is in turn formed in the N-well 102. AP+ region 110 and anN+ region 112 are formed in the R-well 104, and a connected together to define an anode. Asecond P+ region 120 andN+ region 122 are formed in a P-well in thesubstrate 100 and are connected together to define a cathode. AnotherN+ region 130 is formed in the N-well 102 and a contact region to the P-substrate is provided by anotherP+ region 132. - Another approach has been to make use of a standard multi-finger NPN or BSCR without a collector (cathode) region. A multi-finger NPN is shown in
FIG. 2 , with the NPN structures connected back to back as shown in the corresponding schematic circuit diagram ofFIG. 3 . Referring again toFIG. 2 , the NPN structures comprise N-emitters 200 formed on P-type bases 202, which are in turn formed on top of anepitaxial region 204. An N-buried layer (NBL) 210 is formed in theepi 204. As is shown inFIGS. 2 and 3 , two of the NPN structures have theiremitters 200 connected to apad 240, while two of the NPN structures are connected with theiremitters 200 toground 242. All of the NPN structures have their collectors connected together as defined by a common N-doped region ofepi 204. The NPN bipolar junction transistors (BJTs) provide a high holding voltage but saturates at high current levels. In order to increase the ESD protection window and allow the NPN configuration to handle higher current levels, requires that the NPN BJT-based dual direction clamps be integrated in a relatively large footprint. - In contrast, SCR devices are capable of providing higher currents than NPN BJTs due to double injection, however they have lower holding voltages.
- The present invention provides for a hybrid BJT-BSCR dual direction clamp that allows the current-voltage characteristics to be controlled. Preferably the clamp is implemented using a selective base epitaxial region in which an element other than silicon is selectively added to the epitaxial region to define a base epitaxial region, e.g. silicon germanium (SiGe) base epitaxial region (SiGe base epi). For purposes of this application the SiGe base epi or other base epi having an element other than silicon added to the epitaxial region, will be referred to as a selective base epi.
- According to the invention there is provided a dual direction ESD protection circuit, comprising multiple base-emitter regions with a shared sub-collector defining a multi-finger NPN, and multiple P+ diffusion regions, at least one of the P+ diffusion regions being connected to one or more base-emitter regions and to a pad, and at least one other of the P+ diffusion regions being connected to one or more other base-emitter regions and to ground, the bases of the base-emitter regions comprising selective base epi regions. The P+ diffusion regions may comprise P+ diffusion fingers or P+ diffusion rings. The multi-finger NPN may comprise SiGe base epi regions. The base-emitter regions connected to the pad may comprise an emitter connected directly to the pad and a base connected to the pad via a resistor. The base-emitter regions connected to ground may comprise an emitter connected directly to ground and a base connected to ground via a resistor.
- Further, according to the invention, there is provided a dual direction ESD protection circuit, comprising at least one first NPN BJT and at least one second NPN BJT, the NPN BJTs sharing a common collector region and having a base and an emitter, wherein the base comprises a selective base epitaxial region, the circuit further comprising at least one first P+ diffusion region connected to the base and emitter of the at least one first NPN BJT, and at least on second P+ diffusion region connected to the base and emitter region of the at least one to second NPN BJT. The P+ diffusion regions may comprise P+ diffusion fingers or P+ diffusion rings. The NPN BJTs may comprise a multi-finger SiGe BJT. The emitter and base of the at least one first NPN BJT may be connected to a high voltage rail and the emitter and base of the at least one second NPN BJT may be connected to ground. The base of the at least one first NPN BJT may be connected to the high voltage rail via a first resistor, and the base of the at least one second NPN BJT may be connected to ground via a second resistor. The at least one first P+ diffusion region may be formed in an N-type region to define a first diode, and the at least one second P+ diffusion region may be formed in an N-type region to define a second diode. The N-type regions may comprise a shared N-epitaxial region.
- A method of controlling the current-voltage curve of a dual direction protection circuit that includes multiple base-emitter regions with a shared collector defining a multi-finger NPN, and multiple P+ diffusion regions, at least one of the P+ diffusion regions being connected to one or more base-emitter regions and to a pad, and at least one other of the P+ diffusion regions being connected to one or more other base-emitter regions and to ground, wherein the base-emitter region includes a selective base epi region, the method comprising adjusting at least one of, the number of P+ diffusion regions connected to the one or more base-emitter regions and to the pad, the number of P+ diffusion regions connected to the one or more base-emitter regions and to ground, the number of base-emitter regions connected to the pad, the number of base-emitter regions connected to ground, and the distance between one or more of the P+ regions and one or more of the base-emitter regions. The base-emitter regions connected to the pad may comprise an emitter connected directly to the pad and a base connected to the pad via at least one first resistor, and the base-emitter regions connected to ground may comprise an emitter connected directly to ground and a base connected to ground via at least one second resistor, the method comprising adjusting at least one of, at least one first resistor value, and at least one second resistor value. The selective base epi region may comprise a SiGe base epi region.
-
FIG. 1 is a cross-section through a prior art DIAC; -
FIG. 2 is a cross-section through a prior art back to back NPN clamp with shared sub-collector; -
FIG. 3 a circuit diagram of the clamp ofFIG. 2 ; -
FIG. 4 shows a cross-section through one embodiment of an ESD protection circuit of the invention; -
FIG. 5 shows a schematic circuit diagram of an ESD protection circuit of the invention; -
FIG. 6 shows a top view of one embodiment of an ESD protection circuit of the invention, and -
FIG. 7 shows a cross-section through another embodiment of an ESD protection circuit of the invention. - The present invention defines a dual direction ESD protection circuit that can readily be adjusted to achieve different current-voltage (I-V) characteristics. In particular, the holding voltage and on-state resistance can be adjusted.
-
FIG. 4 shows a cross-section through one embodiment of an ESD protection circuit of the invention, which includes an NPN BJT that has two base-emitter fingers and a common sub-collector. The base-emitter fingers comprise afirst emitter 400 and afirst base 402 connected to a high voltage rail orpad 404, and asecond emitter 410 andsecond base 412 connected toground 406. The common sub-collector is defined by an N-epitaxial region 420, which in this embodiment includes selective SiGe epitaxial regions to define SiGe base epitaxial regions belowbases epitaxial region 420 is N-doped to define an N-epi sub-collector for the BJT. As shown inFIG. 4 , an n-buried layer (NBL) 422 is formed in the epi, leaving epitaxial region 424 below the NBL. The epi region 424 is p-doped. In this embodiment afirst P+ region 430 is connected to thepad 404. Asecond P+ region 432 is connected toground 406. By providingP+ regions - A schematic circuit diagram of the circuit of
FIG. 4 is shown inFIG. 5 . Thefirst emitter 400 andbase 402 are connected to thepad 404, while thesecond emitter 410 andbase 412 are connected toground 406. As is shown in bothFIG. 4 and the schematic ofFIG. 5 , thefirst base 402 is connected to thepad 404 via aresistor 440, and thesecond base 412 is connected to ground via aresistor 442. The shared sub-collector region (N-epi 420) is depicted inFIG. 5 by the connected collectors. TheP+ region 430 formed in the N-epi defines afirst diode 500, while theP+ region 432 formed in the N-epi defines asecond diode 502, theP+ region 430 forming the anode of thefirst diode 500, and theP+ region 432 forming the anode of thesecond diode 502. Thediodes diodes FIG. 5 . - When a positive ESD pulse is applied to the
pad 404, theupper diode 500 is forward biased, thus providing a lower voltage on the collector of theupper NPN BJT 510 than theemitter 400 ofNPN 510. The base-collector junction of thelower transistor 512 is in turn reverse biased. At a certain voltage the base-collector junction oftransistor 512 breaks down causing minority carriers in the base-collector junction, which allows current to flow through theupper diode 500 and thelower resistor 442. The voltage drop across theresistor 442 opens thetransistor 512. The forwardbiased diode 500 provides additional injection of holes, which leads to the increase of the current and compensates for the space charge of carriers generated during avalanche multiplication in the base-collector junction, thus decreasing the holding voltage. By varying the level of additional injection of holes by thediode 500, the current-voltage (I-V) curve of the clamp can be controlled. The level of injection in each direction can be varied in different ways, including by varying the number of P+ fingers per NPN BJT finger, by varying the distribution of P+ fingers among the BJT fingers, by varying the distance between the P+ region (finger or ring) and the BJT finger, and by varying the value of the base resistor 442 (for a positive ESD pulse) or resistor 440 (for a negative ESD pulse). By varying one or more of these parameters, the SCR effect can be enhanced or suppressed. - It will be appreciated that during a negative ESD pulse, the operation is similar to that discussed above except that current flow will be from the
ground 406 through thediode 502 and theBJT 510, using current flow through theresistor 440 to open upBJT 510. -
FIG. 6 shows a top view of one embodiment of an ESD protection circuit of the invention, which shows two different P+ region configurations. In this embodiment the ring-shaped P+ region 600 forms the anode of theupper diode 500 while the anode of thelower diode 502 is formed by a two P+ diffusion regions in the form of fingers 602. The base-emitter fingers 604 are formed between the P+ fingers 602 in this embodiment. - Another embodiment of a dual direction ESD protection circuit of the invention is shown in
FIG. 7 . Structurally it is similar to the circuit ofFIG. 4 but the various regions are connected together differently to achieve different circuit performance. - The circuit of
FIG. 7 again includes an NPN BJT that has two base-emitter fingers and a common sub-collector. The base-emitter fingers comprise afirst emitter 700 and afirst base 702 connected to a high voltage rail orpad 704, and asecond emitter 710 andsecond base 712 connected toground 706. The common sub-collector is again defined by an N-epitaxial region 720. As in the embodiment ofFIG. 4 , an n-buried layer (NBL) 722 is formed in the N-epi 720. Afirst P+ region 730 is connected to thepad 704. Asecond P+ region 432 is connected toground 706. By providingP+ regions FIG. 4 the P+ region (P+ SCR emitter region) is not adjacent to the base-emitter finger with which it forms a discharge circuit from pad to ground during a positive ESD pulse or from ground to pad during a negative ESD pulse. For example during a negative ESD pulse, the current path is defined by theP+ region 732 and theresistor 740 opening up the NPN BJT defined by theemitter 700 andbase 702 withsub-collector 720. Theemitter 700 andbase 702, which are connected to thepad 704 are separated by a gap from theP+ region 732, which is connected to theground 706. Thus the SCR effect is partly suppressed due to the larger gap between theP+ BSCR emitter 732 and the corresponding BJT finger ofemitter 700 andbase 702. Similarly during a positive ESD pulse with current path throughP+ region 730 andresistor 742 opening up the NPN defined byemitter 710,base 712 and sub-collector 720, theP+ region 730 is separated from theNPN - While the present invention has been described with respect to a few specific embodiments with a limited number of base-emitter fingers and P+ regions and with specific P+ region configurations, it will be appreciated that the dual direction ESD protection circuit of the present invention can be implemented in different ways without departing from the scope of the invention as defined by the claims.
Claims (15)
1. A dual direction ESD protection circuit, comprising
multiple base-emitter regions with a shared sub-collector defining a multi-finger NPN, and
multiple P+ diffusion regions, at least one of the P+ diffusion regions being connected to one or more base-emitter regions and to a pad, and at least one other of the P+ diffusion regions being connected to one or more other base-emitter regions and to ground, the bases of the base-emitter regions including selective base epitaxial regions.
2. A dual direction ESD protection circuit of claim 1 , wherein the P+ diffusion regions comprise P+ diffusion fingers or P+ diffusion rings.
3. A dual direction ESD protection circuit of claim 1 , wherein the selective base epitaxial regions comprise SiGe base epi regions.
4. A dual direction ESD protection circuit of claim 1 , wherein the base-emitter regions connected to the pad each comprise an emitter connected directly to the pad and a base connected to the pad via a resistor.
5. A dual direction ESD protection circuit of claim 1 , wherein the base-emitter regions connected to ground each comprise an emitter connected directly to ground and a base connected to ground via a resistor.
6. A direction ESD protection circuit, comprising
at least one first NPN BJT,
at least one second NPN BJT, wherein the NPN BJTs share a common collector region and each have a base and an emitter, wherein each base includes a selective base epitaxial region, the circuit further comprising
at least one first P+ diffusion region connected to the base and emitter of the at least one first NPN BJT, and
at least on second P+ diffusion region connected to the base and emitter region of the at least one second NPN BJT.
7. A dual direction ESD protection circuit of claim 6 , wherein the P+ diffusion regions comprise P+ diffusion fingers or P+ diffusion rings.
8. A dual direction ESD protection circuit of claim 6 , wherein the selective base epitaxial region comprises a SiGe base epi.
9. A dual direction ESD protection circuit of claim 6 , wherein the emitter and base of the at least one first NPN BJT are connected to a high voltage rail, and the emitter and base of the at least one second NPN BJT are connected to ground.
10. A dual direction ESD protection circuit of claim 9 , wherein the base of the at least one first NPN BJT is connected to the high voltage rail via a first resistor, and the base of the at least one second NPN BJT is connected to ground via a second resistor.
11. A dual direction ESD protection circuit of claim 6 , wherein the at least one first P+ diffusion region is formed in an N-type region to define a first diode, and the at least one second P+ diffusion region is formed in an N-type region to define a second diode.
12. A dual direction ESD protection circuit of claim 11 , wherein the N-type regions comprise a shared N-epitaxial region.
13. A method of controlling the current-voltage curve of a dual direction protection circuit that includes multiple bases with selective base epitaxial regions, multiple emitters, and a shared collector defining a multi-finger NPN, and further including multiple P+ diffusion regions, at least one of the P+ diffusion regions being connected to one or more bases and emitters and to a pad, and at least one other of the P+ diffusion regions being connected to one or more other bases and emitters and to ground, the method comprising
adjusting at least one of, the number of P+ diffusion regions connected to the one or more bases and emitters and to the pad, the number of P+ diffusion regions connected to the one or more bases and emitters and to ground, the number of bases and emitters connected to the pad, the number of bases and emitters connected to ground, and the distance between one or more of the P+ regions and one or more of the emitters.
14. A method of claim 13 , wherein the bases and emitters connected to the pad comprise an emitter connected directly to the pad and a base connected to the pad via at least one first resistor, and the bases and emitters connected to ground comprise an emitter connected directly to ground and a base connected to ground via at least one second resistor, the method comprising adjusting at least one of, at least one first resistor value, and at least one second resistor value.
15. A method of claim 14 , wherein the selective base epitaxial region comprises a SiGe base epitaxial region.
Priority Applications (2)
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US12/928,715 US20120153347A1 (en) | 2010-12-17 | 2010-12-17 | ESD clamp with auto biasing under high injection conditions |
US14/049,888 US9543296B2 (en) | 2010-12-17 | 2013-10-09 | ESD clamp with auto biasing under high injection conditions |
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US12/928,715 US20120153347A1 (en) | 2010-12-17 | 2010-12-17 | ESD clamp with auto biasing under high injection conditions |
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US14/049,888 Division US9543296B2 (en) | 2010-12-17 | 2013-10-09 | ESD clamp with auto biasing under high injection conditions |
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US12/928,715 Abandoned US20120153347A1 (en) | 2010-12-17 | 2010-12-17 | ESD clamp with auto biasing under high injection conditions |
US14/049,888 Active 2032-08-19 US9543296B2 (en) | 2010-12-17 | 2013-10-09 | ESD clamp with auto biasing under high injection conditions |
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Cited By (2)
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CN105374816A (en) * | 2015-12-23 | 2016-03-02 | 电子科技大学 | Bidirectional ESD protection device based on germanium-silicon heterojunction proces |
CN105374817A (en) * | 2015-12-23 | 2016-03-02 | 电子科技大学 | SCR device based on germanium-silicon heterojunction process |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US10804887B1 (en) * | 2019-09-26 | 2020-10-13 | Texas Instruments Incorporated | Slow clamp circuit for bipolar junction transistor (BJT) buffers |
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JP2002141476A (en) * | 2000-11-07 | 2002-05-17 | Hitachi Ltd | BiCMOS SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREFOR |
DE102004035745A1 (en) * | 2004-07-23 | 2006-02-16 | Infineon Technologies Ag | Integrated circuit |
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US5212618A (en) * | 1990-05-03 | 1993-05-18 | Linear Technology Corporation | Electrostatic discharge clamp using vertical NPN transistor |
US20010043449A1 (en) * | 2000-05-15 | 2001-11-22 | Nec Corporation | ESD protection apparatus and method for fabricating the same |
US20020096742A1 (en) * | 2001-01-25 | 2002-07-25 | International Business Machines Corporation | ESD robust silicon germanium transistor with emitter NP-block mask extrinsic base ballasting resistor with doped facet region |
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US20140034996A1 (en) | 2014-02-06 |
US9543296B2 (en) | 2017-01-10 |
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