CN104600104A - Controllable silicon structure with high sustaining voltage - Google Patents

Controllable silicon structure with high sustaining voltage Download PDF

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Publication number
CN104600104A
CN104600104A CN201410768622.9A CN201410768622A CN104600104A CN 104600104 A CN104600104 A CN 104600104A CN 201410768622 A CN201410768622 A CN 201410768622A CN 104600104 A CN104600104 A CN 104600104A
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district
voltage
trap
region
scr structure
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CN201410768622.9A
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CN104600104B (en
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陶园林
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Shanghai Beiling Co Ltd
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Shanghai Beiling Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7436—Lateral thyristors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a controllable silicon structure with sustaining voltage, which is suitable for power supply ESD (electro spark detector) protection. The controllable silicon structure comprises a P-type substrate, wherein an N-type buried layer is arranged in the P-type substrate; a high-voltage N well is injected on the N-type buried layer; a first N<+> region, a first P<+> region, a third N<+> region and a low-voltage P well are injected in the high-voltage N well; a second N<+> region and a second P<+> region are injected in the low-voltage P well. Oxidized isolating layers cover on P-type substrates at the two sides of an apparatus, and the second N<+> region and the third N<+> region are isolated by the oxidized isolating layers. The controllable silicon structure with sustaining voltage disclosed by the invention has relatively high sustaining voltage, is suitable for being applied to ESD protection of the power supply, and can be compatible with high-voltage CMOS (complementary metal-oxide-semiconductor transistor) and BCD process which are common in the field.

Description

High maintenance voltage SCR structure
Technical field
The present invention relates to a kind of high maintenance voltage SCR structure, particularly a kind of height being applicable to power supply esd protection keeps voltage SCR structure.
Background technology
Static discharge (Electrostatic Discharge, ESD) phenomenon is extensively present in occurring in nature, is also one of major reason causing integrated circuit (IC) products to lose efficacy.Integrated circuit (IC) products is manufactured at it and is easy to the impact being subject to static discharge in assembling process, causes the reliability of product to reduce, even damages.Therefore, the electrostatic discharge protection component that research reliability is high and electrostatic defending performance is strong and protection circuit have very important effect to the rate of finished products and reliability that improve integrated circuit.
According to static discharge Producing reason and the difference to integrated circuit discharge mode thereof, static discharge is divided into following four kinds of pattern: HBM (human-body model), MM (machine discharge mode), CDM (assembly charging and discharging pattern) and FIM (electric field induction pattern) usually.Wherein, HBM and MM pattern is modal is also two kinds of static discharge patterns that industrial quarters is concerned about the most.When integrated circuit generation static discharge phenomenon, a large amount of electric charge flows into the pin of chip instantaneously, and the electric current that these electric charges produce can reach several amperes of sizes usually, and the voltage produced at this pin place is up to a few volt even tens volts.Larger electric current and higher voltage can cause puncturing of the damage of chip internal circuits and device, thus cause the inefficacy of circuit function.
Therefore, in order to the damage preventing chip to be subjected to ESD, just need will carry out effective ESD protection to each pin of chip.Usually, the design of ESD protective device needs the problem of consideration two aspects: one is that ESD protective device wants to release big current; Two be ESD protective device want can when chip is subject to ESD impact by the low voltage level of chip pin terminal voltage strangulation in safety.
The device being typically used as esd protection mainly contains diode, GGNMOS (NMOS of grid ground connection), controllable silicon (SCR) etc.SCR structure due to its area little, current drain ability is strong, is widely used.But, because general SCR structure keeps voltage low (being usually less than supply voltage), easily bring out LATCH-UP phenomenon, so be seldom applied to the esd protection of chip power supply pin.
Therefore, studying a kind of SCR structure that be applicable to power supply esd protection, that have high maintenance voltage, is the problem that the applicant is devoted to solve.
Summary of the invention
For this reason, the invention provides a kind of high maintenance voltage SCR structure, comprise P type substrate (101), n type buried layer (102) is provided with in described P type substrate (101), described n type buried layer (102) is marked with high pressure N trap (103), a N+ district (104) is marked with successively side by side in described high pressure N trap (103), one P+ district (105) and low pressure P trap (109), the 2nd N+ district (107) and the 2nd P+ district (108) is marked with successively side by side in described low pressure P trap (109), wherein, the 3rd N+ district (106) is marked with between a described P+ district (105) and described 2nd N+ district (107), the part in described 3rd N+ district (106) is positioned at described high pressure N trap (103), another part is positioned at described low pressure P trap (109), and between described 3rd N+ district (106) and described 2nd N+ district (107) between be separated with the second oxidization isolation layer (110b), described P type substrate (101) extends to the surface of described SCR structure at the edge of described SCR structure, and the region overlay being positioned at described P type substrate (101) on the surface of described SCR structure has the first oxidization isolation layer (110a, 110a ').
Further, drawing the first device interface is connected to power supply jointly for a described N+ district (104) and a described P+ district (105), and the second device interface ground connection is drawn jointly by described 2nd N+ district (107) and described 2nd P+ district (108).
Height of the present invention keeps voltage SCR structure, owing to having higher maintenance voltage, therefore is applicable to being applied to the esd protection to power supply in chip, and the realization of its technique can the high-voltage CMOS conventional with industry and BCD process compatible.
Accompanying drawing explanation
Fig. 1 is the structural representation that the height of the present invention shown in the mode of profile keeps voltage SCR structure;
Fig. 2 is the parasitic element schematic diagram that height of the present invention keeps voltage SCR structure;
Fig. 3 is the TLP resolution chart that height of the present invention keeps voltage SCR structure.
Embodiment
Voltage SCR structure is kept to be described in further detail below in conjunction with the drawings and specific embodiments to height of the present invention, but not as a limitation of the invention.
As shown in Figure 1, a kind of high maintenance voltage SCR structure, it is applicable to power supply esd protection, comprises P type substrate 101, is provided with n type buried layer 102 in this P type substrate 101, n type buried layer 102 is marked with high pressure N trap 103.
Be marked with a N+ district 104, a P+ district 105 and low pressure P trap 109 in high pressure N trap 103 successively side by side, in low pressure P trap 109, be marked with the 2nd N+ district 107 and the 2nd P+ district 108 successively side by side.
In addition, the 3rd N+ district 106 is marked with between a P+ district 105 and the 2nd N+ district 107, the part in the 3rd N+ district 106 is positioned at high pressure N trap 103, and another part is positioned at low pressure P trap 109, and between the 3rd N+ district 106 and the 2nd N+ district 107 between be separated with the second oxidization isolation layer 110b.
Meanwhile, P type substrate 101 extends to the surface of this SCR structure at the edge of this SCR structure, and the region overlay being positioned at P type substrate 101 on the surface of this SCR structure has the first oxidization isolation layer 110a, 110a '.
As shown in Figure 2, above-mentioned SCR structure is parasitic positive-negative-positive bipolar transistor Q1, bipolar npn transistor npn npn Q2, high pressure N trap resistance R nWELLwith low pressure P trap resistance R pWELL.Q1, Q2, R nWELLand R pWELLtogether, the controllable silicon current drain path of a positive feedback is constituted.
In use, the power pin that a terminal connects chip is drawn in a N+ district 104 and a P+ district 105 jointly, and the ground that a terminal connects chip is drawn in the 2nd N+ district 107 and the 2nd P+ district 108 jointly.When esd pulse event occurs in power pin, the reverse PN junction that ESD electric current can cause the 3rd N+ district 106 and low pressure P trap 109 to form at the voltage that power end produces punctures, when the electric current of reverse breakdown generation is at high pressure N trap resistance R nWELLwhen the pressure drop of upper generation reaches the forward PN diode turn-on voltage (as 0.7V) that a P+ district 105 forms with high pressure N trap 103, by Q1, Q2, R nWELLand R pWELLthe SCR structure formed is opened, electric current is released to ground from power end, and power end voltage being remained on a lower value (but still higher than common supply voltage), this magnitude of voltage kept is silicon controlled and keeps voltage, the V namely shown in Fig. 3 hOLD.
Because chip power itself has very strong current output capability, if therefore the maintenance voltage of this SCR structure is lower than supply voltage, SCR structure is once be triggered, its cannot return to again and be triggered before state, and by always from the electric current that power supply pull-out is very large, cause the damage of chip the most at last.But the maintenance voltage V of SCR structure of the present invention hOLD, with reference to Fig. 3, substantially near 7 ~ 8V, higher than common supply voltage 3V or 5V.
Therefore, height of the present invention keeps voltage SCR structure, can be applied to the esd protection of power pin.Wherein, the puncture voltage V of this SCR structure t1that the puncture voltage of the reverse PN junction be made up of with low pressure P trap 109 the 3rd N+ district 106 determines, maintenance voltage V hOLDdetermined by the distance in a P+ district 105 and the 2nd N+ district 107.
Obviously, the maintenance voltage V of SCR structure can be adjusted by the distance adjusting a P+ district 105 and the 2nd N+ district 107 hOLD, to meet the demand of different application.In addition, many groups SCR structure side by side also can be adopted to strengthen the relieving capacity of ESD electric current.
Above embodiment is only illustrative embodiments of the present invention, can not be used for limiting the present invention, and protection scope of the present invention is defined by the claims.Those skilled in the art can in essence of the present invention and protection range, and make various amendment or equivalent replacement to the present invention, these are revised or be equal to replacement and also should be considered as dropping in protection scope of the present invention.

Claims (2)

1. one kind high maintenance voltage SCR structure, comprise P type substrate (101), n type buried layer (102) is provided with in described P type substrate (101), described n type buried layer (102) is marked with high pressure N trap (103), a N+ district (104), a P+ district (105) and low pressure P trap (109) is marked with successively side by side in described high pressure N trap (103), the 2nd N+ district (107) and the 2nd P+ district (108) is marked with successively side by side in described low pressure P trap (109), wherein
The 3rd N+ district (106) is marked with between a described P+ district (105) and described 2nd N+ district (107), the part in described 3rd N+ district (106) is positioned at described high pressure N trap (103), another part is positioned at described low pressure P trap (109), and between described 3rd N+ district (106) and described 2nd N+ district (107) between be separated with the second oxidization isolation layer (110b);
Described P type substrate (101) extends to the surface of described SCR structure at the edge of described SCR structure, and the region overlay being positioned at described P type substrate (101) on the surface of described SCR structure has the first oxidization isolation layer (110a, 110a ').
2. height according to claim 1 keeps voltage SCR structure, it is characterized in that, drawing the first device interface is connected to power supply jointly for a described N+ district (104) and a described P+ district (105), and the second device interface ground connection is drawn jointly by described 2nd N+ district (107) and described 2nd P+ district (108).
CN201410768622.9A 2014-12-12 2014-12-12 Height keeps voltage SCR structure Active CN104600104B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107799517A (en) * 2016-08-30 2018-03-13 格芯公司 ESD devices for semiconductor structure
CN113363253A (en) * 2021-08-11 2021-09-07 江苏应能微电子有限公司 Silicon controlled rectifier layout structure of integrated reverse conducting diode

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US907A (en) * 1838-09-07 steiger
US5808342A (en) * 1996-09-26 1998-09-15 Texas Instruments Incorporated Bipolar SCR triggering for ESD protection of high speed bipolar/BiCMOS circuits
CN1402346A (en) * 2001-08-20 2003-03-12 旺宏电子股份有限公司 Electrostatic discharge protection device
CN1183597C (en) * 1999-12-17 2005-01-05 皇家菲利浦电子有限公司 Bidirectional ESD diode structure
CN100372115C (en) * 2003-09-01 2008-02-27 上海宏力半导体制造有限公司 Method for mfg. silicon rectifier as electro static discharge protection
CN100550368C (en) * 2007-03-01 2009-10-14 和舰科技(苏州)有限公司 A kind of thyristor of protecting static discharge
CN101728428A (en) * 2008-10-10 2010-06-09 和舰科技(苏州)有限公司 Silicon controlled rectifier and manufacturing method thereof
CN103545310A (en) * 2013-11-15 2014-01-29 上海贝岭股份有限公司 PNPN type ESD protective device and ESD protective circuit

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US907A (en) * 1838-09-07 steiger
US5808342A (en) * 1996-09-26 1998-09-15 Texas Instruments Incorporated Bipolar SCR triggering for ESD protection of high speed bipolar/BiCMOS circuits
CN1183597C (en) * 1999-12-17 2005-01-05 皇家菲利浦电子有限公司 Bidirectional ESD diode structure
CN1402346A (en) * 2001-08-20 2003-03-12 旺宏电子股份有限公司 Electrostatic discharge protection device
CN100372115C (en) * 2003-09-01 2008-02-27 上海宏力半导体制造有限公司 Method for mfg. silicon rectifier as electro static discharge protection
CN100550368C (en) * 2007-03-01 2009-10-14 和舰科技(苏州)有限公司 A kind of thyristor of protecting static discharge
CN101728428A (en) * 2008-10-10 2010-06-09 和舰科技(苏州)有限公司 Silicon controlled rectifier and manufacturing method thereof
CN103545310A (en) * 2013-11-15 2014-01-29 上海贝岭股份有限公司 PNPN type ESD protective device and ESD protective circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107799517A (en) * 2016-08-30 2018-03-13 格芯公司 ESD devices for semiconductor structure
CN107799517B (en) * 2016-08-30 2021-11-26 格芯(美国)集成电路科技有限公司 ESD device for semiconductor structure
CN113363253A (en) * 2021-08-11 2021-09-07 江苏应能微电子有限公司 Silicon controlled rectifier layout structure of integrated reverse conducting diode
CN113363253B (en) * 2021-08-11 2021-11-30 江苏应能微电子有限公司 Silicon controlled rectifier layout structure of integrated reverse conducting diode

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