CN104600104B - Height keeps voltage SCR structure - Google Patents
Height keeps voltage SCR structure Download PDFInfo
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- CN104600104B CN104600104B CN201410768622.9A CN201410768622A CN104600104B CN 104600104 B CN104600104 B CN 104600104B CN 201410768622 A CN201410768622 A CN 201410768622A CN 104600104 B CN104600104 B CN 104600104B
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- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 238000000605 extraction Methods 0.000 claims 1
- 230000004224 protection Effects 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000003068 static effect Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 206010003497 Asphyxia Diseases 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 239000002775 capsule Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7436—Lateral thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of high holding voltage SCR structure; it is suitable for power supply ESD protections; the SCR structure includes P type substrate; n type buried layer is equipped with P type substrate; high pressure N traps are marked with n type buried layer; the first N+ areas, the first P+ areas, the 3rd N+ areas and low pressure p-well are marked with high pressure N traps, the 2nd N+ areas and the 2nd P+ areas are marked with low pressure p-well.Oxidization isolation layer is all covered with the both sides P type substrate of device, the 2nd N+ areas and the 3rd N+ areas are also separated by oxidization isolation layer.The high of the present invention keeps voltage SCR structure, due to higher holding voltage, therefore is suitably applied in chip and the ESD of power supply is protected, and realize can common with industry high-voltage CMOS and BCD process compatibles for its technique.
Description
Technical field
The present invention relates to a kind of high holding voltage SCR structure, more particularly to a kind of height suitable for power supply ESD protections
Keep voltage SCR structure.
Background technology
Phenomenon is widely present in nature static discharge (Electrostatic Discharge, ESD), and is caused
The one of the major reasons of IC products failure.IC products are highly susceptible in its manufacturing and assembling process
The influence of static discharge, causing the reliability of product reduces, or even damage.Therefore, reliability height and electrostatic protection performance are studied
Strong electrostatic discharge protection component and protection circuit has very important work to the yield rate and reliability that improve integrated circuit
With.
According to static discharge Producing reason and its difference to integrated circuit discharge mode, static discharge be generally divided into
Lower four kinds of patterns：HBM (human-body model), MM (machine discharge mode), CDM (component charging and discharging pattern) and FIM (electricity
Field inductive mode).Wherein, two kinds of static discharge patterns that HBM and MM patterns are most common and industrial quarters is concerned about the most.When
When static discharge phenomenon occurs for integrated circuit, a large amount of electric charge moments flow into the pin of chip, and the electric current that these electric charges produce is usual
Up to several amperes of sizes, the voltage produced at the pin is up to even tens volts of several volts.Larger electric current and higher electricity
Pressure can cause the damage of chip internal circuits and the breakdown of device, so as to cause the failure of circuit function.
Therefore, damage of the chip by ESD in order to prevent, it is necessary to will be carried out effectively to each pin of chip
ESD protection.In general, the problem of design of ESD protective device needs to consider two aspects：First, ESD protective device be able to will be let out
Amplify electric current；Second, ESD protective device will can when chip is subject to ESD impact by chip pin terminal voltage strangulation in the low of safety
Voltage level.
Being typically used as the device of ESD protections mainly has diode, GGNMOS (NMOS of grid ground connection), silicon-controlled (SCR) etc..
For SCR structure since its area is small, current drain ability is strong, is widely used.But due to general silicon-controlled
Structure keeps voltage low (usually less than supply voltage), easily induces LATCH-UP phenomenons, is powered on so being rarely applied to chip
The ESD protections of source capsule foot.
Therefore, a kind of SCR structure being protected suitable for power supply ESD, that there is height to keep voltage is studied, is the application
People is directed to solving the problems, such as.
The content of the invention
For this reason, the present invention provides a kind of high holding voltage SCR structure, including P type substrate (101), the p-type lining
N type buried layer (102) is equipped with bottom (101), high pressure N traps (103), the high pressure N traps (103) are marked with the n type buried layer (102)
Inside be marked with the first N+ areas (104), the first P+ areas (105) and low pressure p-well (109) side by side successively, in the low pressure p-well (109) according to
It is secondary to be marked with the 2nd N+ areas (107) and the 2nd P+ areas (108) side by side, wherein, in the first P+ areas (105) and the 2nd N+ areas
(107) the 3rd N+ areas (106) are marked between, a part for the 3rd N+ areas (106) is located in the high pressure N traps (103), separately
A part in the low pressure p-well (109), and between the 3rd N+ areas (106) and the 2nd N+ areas (107) between be separated with
Second oxidization isolation layer (110b)；The P type substrate (101) extends to the silicon-controlled knot at the edge of the SCR structure
The surface of structure, and the region overlay for being located at the P type substrate (101) on the surface of the SCR structure has the first oxidation isolation
Layer (110a, 110a ').
Further, the first N+ areas (104) are drawn the first device interface with the first P+ areas (105) and are connected jointly
To power supply, the 2nd N+ areas (107) draw the second device interface ground connection with the 2nd P+ areas (108) jointly.
The high of the present invention keeps voltage SCR structure, due to higher holding voltage, therefore is suitably applied chip
In the ESD of power supply is protected, and realize can common with industry high-voltage CMOS and BCD process compatibles for its technique.
Brief description of the drawings
Fig. 1 is the high structure diagram for keeping voltage SCR structure of the invention shown in a manner of profile；
Fig. 2 is the high parasitic element schematic diagram for keeping voltage SCR structure of the present invention；
Fig. 3 is the high TLP test charts for keeping voltage SCR structure of the present invention.
Embodiment
Keep voltage SCR structure work further detailed the high of the present invention with reference to the accompanying drawings and detailed description
Thin description, but it is not as a limitation of the invention.
As shown in Figure 1, a kind of high holding voltage SCR structure, it is suitable for power supply ESD protections, including P type substrate
101, the P type substrate 101 is interior to be equipped with n type buried layer 102, and high pressure N traps 103 are marked with n type buried layer 102.
The first N+ areas 104, the first P+ areas 105 and low pressure p-well 109 are marked with side by side successively in high pressure N traps 103, in low pressure p-well
It is marked with the 2nd N+ areas 107 and the 2nd P+ areas 108 in 109 side by side successively.
In addition, the 3rd N+ areas 106 are marked between the first P+ areas 105 and the 2nd N+ areas 107, the one of the 3rd N+ areas 106
In high pressure N traps 103, another part is located in low pressure p-well 109 for part, and between the 3rd N+ areas 106 and the 2nd N+ areas 107
Between be separated with the second oxidization isolation layer 110b.
Meanwhile P type substrate 101 extends to the surface of the SCR structure at the edge of the SCR structure, and can at this
The region overlay that the surface of control silicon structure is located at P type substrate 101 has the first oxidization isolation layer 110a, 110a '.
As shown in Fig. 2, above-mentioned SCR structure parasitic positive-negative-positive bipolar transistor Q1, bipolar npn transistor npn npn
Q2, high pressure N trap resistance RNWELLWith low pressure p-well resistance RPWELL。Q1、Q2、RNWELLAnd RPWELLTogether, positive feedback is constituted
Silicon-controlled current drain path.
When in use, the power pin that a terminal connects chip is drawn in the first N+ areas 104 and the first P+ areas 105 jointly, the
The ground that a terminal connects chip is drawn in two N+ areas 107 and the 2nd P+ areas 108 jointly.When esd pulse event occurs in power pin
When, ESD electric currents can cause the 3rd N+ areas 106 to puncture with the reverse PN junction that low pressure p-well 109 is formed in the voltage that power end produces,
When the electric current that reverse breakdown produces is in high pressure N trap resistance RNWELLThe pressure drop of upper generation reaches the first P+ areas 105 and high pressure N traps 103
During positive PN diode turn-on voltages (such as 0.7V) of composition, by Q1, Q2, RNWELLAnd RPWELLThe SCR structure of composition is opened,
Electric current is released to ground from power end, and power supply terminal voltage is maintained at a relatively low value and (but still is higher than common power supply
Voltage), this magnitude of voltage kept is silicon-controlled holding voltage, i.e., the V shown in Fig. 3HOLD。
Since chip power has very strong current output capability in itself, so if the holding voltage of the SCR structure
If supply voltage, SCR structure once being triggered, it will be unable to then return to be triggered before state, and will always from
Power supply pulls out very big electric current, most causes the damage of chip at last.But the holding voltage V of the SCR structure of the present inventionHOLD, ginseng
According to Fig. 3, substantially near 7~8V, higher than common supply voltage 3V or 5V.
Therefore, the high ESD protections for keeping voltage SCR structure, can be applied to power pin of the invention.Wherein, should
The breakdown voltage V of SCR structureT1It is that the breakdown voltage of the reverse PN junction being made of the 3rd N+ areas 106 with low pressure p-well 109 determines
, keep voltage VHOLDIt is to be determined by the distance in the first P+ areas 105 and the 2nd N+ areas 107.
Obviously, the holding of SCR structure can be adjusted by adjusting the distance in the first P+ areas 105 and the 2nd N+ areas 107
Voltage VHOLD, to meet the needs of different application.Alternatively, it is also possible to strengthen ESD electricity using multigroup SCR structure side by side
The relieving capacity of stream.
Above embodiment is only the illustrative embodiments of the present invention, it is impossible to be used in limits the present invention, the present invention
Protection domain be defined by the claims.Those skilled in the art can be in the essence and protection domain of the present invention, to this
Various modifications or equivalent substitution are made in invention, these modifications or equivalent substitution also should be regarded as being within the scope of the present invention.
Claims (1)
1. a kind of high holding voltage SCR structure, including P type substrate (101), the P type substrate (101) is interior to be equipped with n type buried layer
(102), high pressure N traps (103) are marked with the n type buried layer (102), the first N+ is marked with side by side successively in the high pressure N traps (103)
Area (104), the first P+ areas (105) and low pressure p-well (109), the low pressure p-well (109) is interior to be marked with the 2nd N+ areas side by side successively
(107) and the 2nd P+ areas (108), wherein,
The 3rd N+ areas (106), the 3rd N+ areas are marked between the first P+ areas (105) and the 2nd N+ areas (107)
(106) a part is located in the high pressure N traps (103), and another part is located in the low pressure p-well (109), and the described 3rd
The second oxidization isolation layer (110b) is separated between N+ areas (106) and the 2nd N+ areas (107)；
The P type substrate (101) extends to the surface of the SCR structure at the edge of the SCR structure, and described
The region overlay that the surface of SCR structure is located at the P type substrate (101) has the first oxidization isolation layer (110a, 110a ')；Institute
Stating the first N+ areas (104), the first device interface of extraction is connected to power supply, the 2nd N+ areas jointly with the first P+ areas (105)
(107) the second device interface ground connection is drawn jointly with the 2nd P+ areas (108).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410768622.9A CN104600104B (en) | 2014-12-12 | 2014-12-12 | Height keeps voltage SCR structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410768622.9A CN104600104B (en) | 2014-12-12 | 2014-12-12 | Height keeps voltage SCR structure |
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| Publication Number | Publication Date |
|---|---|
| CN104600104A CN104600104A (en) | 2015-05-06 |
| CN104600104B true CN104600104B (en) | 2018-04-27 |
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| CN201410768622.9A Active CN104600104B (en) | 2014-12-12 | 2014-12-12 | Height keeps voltage SCR structure |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9679888B1 (en) * | 2016-08-30 | 2017-06-13 | Globalfoundries Inc. | ESD device for a semiconductor structure |
| CN113363253B (en) * | 2021-08-11 | 2021-11-30 | 江苏应能微电子有限公司 | Silicon controlled rectifier layout structure of integrated reverse conducting diode |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5808342A (en) * | 1996-09-26 | 1998-09-15 | Texas Instruments Incorporated | Bipolar SCR triggering for ESD protection of high speed bipolar/BiCMOS circuits |
| CN1402346A (en) * | 2001-08-20 | 2003-03-12 | 旺宏电子股份有限公司 | Electrostatic discharge protection device |
| CN1183597C (en) * | 1999-12-17 | 2005-01-05 | 皇家菲利浦电子有限公司 | Bidirectional ESD diode structure |
| CN100372115C (en) * | 2003-09-01 | 2008-02-27 | 上海宏力半导体制造有限公司 | Method for mfg. silicon rectifier as electro static discharge protection |
| CN100550368C (en) * | 2007-03-01 | 2009-10-14 | 和舰科技(苏州)有限公司 | A kind of thyristor of protecting static discharge |
| CN101728428A (en) * | 2008-10-10 | 2010-06-09 | 和舰科技(苏州)有限公司 | Silicon controlled rectifier and manufacturing method thereof |
| CN103545310A (en) * | 2013-11-15 | 2014-01-29 | 上海贝岭股份有限公司 | PNPN type ESD protective device and ESD protective circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US907A (en) * | 1838-09-07 | steiger |
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- 2014-12-12 CN CN201410768622.9A patent/CN104600104B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5808342A (en) * | 1996-09-26 | 1998-09-15 | Texas Instruments Incorporated | Bipolar SCR triggering for ESD protection of high speed bipolar/BiCMOS circuits |
| CN1183597C (en) * | 1999-12-17 | 2005-01-05 | 皇家菲利浦电子有限公司 | Bidirectional ESD diode structure |
| CN1402346A (en) * | 2001-08-20 | 2003-03-12 | 旺宏电子股份有限公司 | Electrostatic discharge protection device |
| CN100372115C (en) * | 2003-09-01 | 2008-02-27 | 上海宏力半导体制造有限公司 | Method for mfg. silicon rectifier as electro static discharge protection |
| CN100550368C (en) * | 2007-03-01 | 2009-10-14 | 和舰科技(苏州)有限公司 | A kind of thyristor of protecting static discharge |
| CN101728428A (en) * | 2008-10-10 | 2010-06-09 | 和舰科技(苏州)有限公司 | Silicon controlled rectifier and manufacturing method thereof |
| CN103545310A (en) * | 2013-11-15 | 2014-01-29 | 上海贝岭股份有限公司 | PNPN type ESD protective device and ESD protective circuit |
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| CN104600104A (en) | 2015-05-06 |
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