CN101728428A - Silicon controlled rectifier and manufacturing method thereof - Google Patents
Silicon controlled rectifier and manufacturing method thereof Download PDFInfo
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- CN101728428A CN101728428A CN200810168280A CN200810168280A CN101728428A CN 101728428 A CN101728428 A CN 101728428A CN 200810168280 A CN200810168280 A CN 200810168280A CN 200810168280 A CN200810168280 A CN 200810168280A CN 101728428 A CN101728428 A CN 101728428A
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Abstract
The invention discloses a silicon controlled rectifier and a manufacturing method thereof. The silicon controlled rectifier comprises a semiconductor substrate, a first P+ doped region, a first N+ doped region, a second P+ doped region, a second N+ doped region, a third P+ doped region or a third N+ doped region, a fourth P+ doped region or a fourth N+ doped region, wherein an N well and a P well are positioned above the semiconductor substrate; the first P+ doped region and the first N+ doped region are formed in the N well; the second P+ doped region and the second N+ doped region are formed in the P well; the third P+ doped region or the third N+ doped region is formed at the bonding position of the N well and the P well; and the fourth P+ doped region or the fourth N+ doped region is formed below the third P+ doped region or the third N+ doped region and in the N well or the P well. The invention has the advantages that the trigger voltage value of an SCR structure can be greatly decreased, thereby improving the integral protective capacity of an ESD; the trigger voltage value of a new SCR structure can be regulated according to the different requirements of a designer, so that the ESD can exert the optimal protective capacity in different circuit designs; and under the same ESD protection requirements, the area can be saved, thereby lowering the design cost.
Description
Technical field
The present invention relates to semiconductor device, particularly a kind of thyristor and manufacture method thereof.
Background technology
Along with the advanced person day by day of semiconductor technology processing procedure, in the IC design, the protection of Electrostatic Discharge receives more and more designers' concern.The components and parts of forming the ESD protection circuit comprise resistance (Resistor), diode (Diode), triode (Bipolar), grounded-grid MOS field-effect transistor (GGMOSFET), gate coupled MOS field-effect transistor (GCMOSFET), thyristor (SCR) or the like.
In numerous ESD protective devices, thyristor (SCR) is because its lower voltage (holding voltage) of keeping makes under area identical to have best ESD protective capacities.But the SCR structure has higher trigger voltage value (Vt1) during as the ESD protective device, makes the ESD protection effect of entire circuit and not as the ideal of expection.In order to reduce the too high trigger voltage value of SCR structure (trigger voltage), the designer has developed multiple SCR structure through improving, the thyristor of low trigger voltage (LVTSCR:low voltage triggering SCR) for example, horizontal thyristor of improvement (MLSCR:modified lateral SCR) or the like.But these improved SCR structures have certain limitation for reducing its trigger voltage, and the difficult control of its trigger voltage value, thereby have increased designer's design difficulty.
Summary of the invention
In view of above-mentioned, wish to propose the manufacture method of a kind of thyristor and this thyristor, can when saving cost, reduce trigger voltage as much as possible, preferably control trigger voltage value.
Therefore, the present invention proposes a kind of thyristor, comprise
Semiconductor substrate,
The N trap and the P trap of this Semiconductor substrate top;
Be formed at a P+ doped region and a N+ doped region in the N trap;
Be formed at the 2nd P+ doped region and the 2nd N+ doped region in the P trap;
Be formed at the 3rd P+ doped region or the 3rd N+ doped region of the position that above-mentioned N trap engages with the P trap; And
N trap or the 4th N-doped region in the P trap or the 4th P-doped region of the 3rd P+ doped region or the 3rd N+ doped region below.
As preferably, above-mentioned the 4th N-doped region or the 4th P-doped region form by the mode of implanting, and the energy of its implantation and dosage are according to required trigger voltage value decision.
As preferably, have isolation structure between above-mentioned each P+ doped region and the N+ doped region, have isolation structure between the doped region that the 3rd P+ doped region or the 3rd N+ doped region are adjacent.
The invention allows for a kind of method that forms described thyristor, comprise
Semiconductor substrate is provided,
Form a plurality of well regions above above-mentioned Semiconductor substrate, these a plurality of well regions comprise N trap and P trap;
In above-mentioned a plurality of well regions, carry out shallow groove isolation structure;
Form at least one P+ doped region and at least one N+ doped region of separating by shallow groove isolation structure in above-mentioned a plurality of well regions at least one, and form at least one the 2nd P+ doped region and at least one the 2nd N+ doped region of separating by shallow groove isolation structure in above-mentioned a plurality of well regions at least one;
Form the 3rd P+ doped region or the 3rd N+ doped region in the position that above-mentioned N trap engages with the P trap, isolate by shallow groove isolation structure between the 3rd P+ doped region or the 3rd N+ doped region and the adjacent doped region; And
Form the 4th N-doped region or the 4th P-doped region in N trap below the 3rd P+ doped region or the 3rd N+ doped region or the P trap.
Beneficial effect of the present invention is that thyristor of the present invention can reduce the trigger voltage value of SCR structure greatly, and then improves the integral protection ability of its ESD; Can regulate the trigger voltage value of new SCR structure according to designer's different demands, in different circuit design, make the optimum ESD protective capacities of its performance; Under identical ESD protection requirements, can more save area, and then reduce design cost.And the method for using the present invention to propose has only increased one procedure, but has made the ESD protective capacities of resulting device improve greatly.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.For the person of ordinary skill in the field, from detailed description of the invention, above-mentioned and other purposes of the present invention, feature and advantage will be apparent.
Description of drawings
Fig. 1 is a LSCR section of structure of the prior art.
Fig. 2 is a MLSCR section of structure of the prior art.
Fig. 3 is the rapid return characteristic curve of LSCR structure and MLSCR structure under the equal area.
Fig. 4 is the SCR section of structure of a preferred embodiment of the present invention.
Fig. 5 is the rapid return characteristic curve of SCR structure of the present invention, LSCR structure and MLSCR structure under the equal area.
Fig. 6 is the SCR section of structure of another preferred embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments a kind of thyristor of the present invention is described in further detail.
Shown in Fig. 1,2 and 3; be traditional horizontal thyristor LSCR structure and improved horizontal thyristor MLSCR (Modified LSCR) in the 0.18 μ m processing procedure for example; with it is example; because traditional LSCR has higher trigger voltage value; referring to the Vt1 among Fig. 3; this trigger voltage value is relevant with the breakdown voltage value of N trap Nwell/P trap Pwell; Vt1 is about 25V; such trigger voltage makes thyristor in the esd discharge process; internal circuit can not be in time opened and then protect effectively, the effect of protection device can't be played well.Simultaneously, its second breakdown current value is for about about 7A, and this current value is higher.
In order to reduce trigger voltage, the designer improves it, in a fixing processing procedure, because the breakdown voltage value of N+/Pwell is far smaller than the breakdown voltage value of Nwell/Pwell, so MLSCR can reduce its trigger voltage effectively, trigger voltage value Vt1 reduces to about 16V.But because the change of structure, make MLSCR structure under the equal area, its second breakdown electric current but descends greatly, and second breakdown current value I t2 reduces to less than 2A, thereby makes whole ESD circuit protection poor effect.Thereby though the trigger voltage value Vt1 of MLSCR structure shown in Figure 2 LSCR structure more shown in Figure 1 has reduced a lot, its second breakdown current value I t2 is but well below LSCR structure shown in Figure 1.
In order to overcome the above defective of MLSCR structure, a kind of new SCR structure and manufacture method thereof are proposed, this new construction not only can change its trigger voltage value (Vt1) according to designer's different demands, and its second breakdown current value (It2) also can improve greatly, thereby improves the ESD protective capacities of whole SCR structure.
The SCR result of a preferred embodiment of the present invention as shown in Figure 4, this SCR structure is to increase by one P-to implant on the basis of MLSCR structure, wherein the energy implanted of P-can be made corresponding change for the different requirements of trigger voltage value according to the designer with dosage.
The structure of this new SCR is specially and comprises Semiconductor substrate, is the P substrate in this embodiment, the N trap and the P trap of this Semiconductor substrate top; Be formed at utilization for example a P+ doped region and a N+ doped region of the isolation structure that forms of fleet plough groove isolation structure or field oxide region in the N trap, as anode; Be formed at utilization isolation structure the 2nd P+ doped region spaced apart from each other and the 2nd N+ doped region that form of fleet plough groove isolation structure or field oxide region for example in the P trap, as negative electrode; Be formed at the 3rd N+ doped region of the position that above-mentioned N trap engages with the P trap, the isolation structure that utilizes fleet plough groove isolation structure for example or field oxide region to form separates the 3rd N+ doped region and a P+ doped region and the 2nd N+ doped region, and the 3rd N+ doped region for example forms by triggering the mode that spreads; And the 4th P-doped region in the P trap of the 3rd N+ doped region below, the 4th P-doped region for example forms by the mode of implanting, and the energy of its implantation and dosage are according to required trigger voltage value decision.
The rapid return characteristic curve of new SCR structure as shown in Figure 5, compare with the SCR structure of Fig. 2 with Fig. 1, the trigger voltage value of this structure is that Vt1 is 8-9V, second breakdown current value I t1 reaches about 8.65A, thereby it not only has lower trigger voltage value, and have higher second breakdown current value, its ESD protective capacities is improved greatly.
The SCR section of structure of another preferred embodiment of the present invention as shown in Figure 6, wherein P substrate, N trap, P trap, a P+ doped region, a N+ doped region, the 2nd P+ doped region and the 2nd N+ doped region are identical with SCR structure shown in Figure 4, difference is that the position that above-mentioned N trap engages with the P trap forms the 3rd P+ doped region, utilize isolation structure to separate the 3rd P+ doped region and a P+ doped region and the 2nd N+ doped region, the 3rd P+ doped region for example forms by the mode that triggers diffusion; And the 4th N-doped region in the N trap of the 3rd P+ doped region below, the 4th N-doped region for example forms by the mode of implanting, and the energy of its implantation and dosage are according to required trigger voltage value decision.
The method of the described thyristor of formation of a preferred embodiment of the present invention comprises
Semiconductor substrate is provided,
Form a plurality of well regions above above-mentioned Semiconductor substrate, these a plurality of well regions comprise N trap and P trap;
In above-mentioned a plurality of well regions, carry out shallow groove isolation structure;
In above-mentioned N trap, form at least one P+ doped region and at least one N+ doped region of separating by shallow groove isolation structure;
In above-mentioned P trap, form at least one the 2nd P+ doped region and at least one the 2nd N+ doped region of separating by shallow groove isolation structure;
Form the 3rd P+ doped region or the 3rd N+ doped region in the position that above-mentioned N trap engages with the P trap, isolate by shallow groove isolation structure between the 3rd P+ doped region or the 3rd N+ doped region and the adjacent doped region; And
Form the 4th N-doped region or the 4th P-doped region in N trap below the 3rd P+ doped region or the 3rd N+ doped region or the P trap.
Wherein, more than the formation order of a P+ doped region and a N+ doped region, the 2nd P+ doped region and the 2nd N+ doped region, the 3rd P+ doped region and the 3rd N+ doped region can be any order, perhaps above doped region forms simultaneously, is not subjected to the restriction of the order in the foregoing description.And the 4th N-doped region or the 4th P-doped region form after forming above-mentioned doped region.
Wherein Fig. 3 is the result that experiment records with the rapid return characteristic curve of different SCR structures shown in Figure 5.
The above is preferred embodiment of the present invention only, is not to be used for limiting practical range of the present invention; If do not break away from the spirit and scope of the present invention, the present invention is made amendment or is equal to replacement, all should be encompassed in the middle of the protection range of claim of the present invention.
Claims (5)
1. a thyristor is characterized in that comprising
Semiconductor substrate,
The N trap and the P trap of this Semiconductor substrate top;
Be formed at a P+ doped region and a N+ doped region in the N trap;
Be formed at the 2nd P+ doped region and the 2nd N+ doped region in the P trap;
Be formed at the 3rd P+ doped region or the 3rd N+ doped region of the position that above-mentioned N trap engages with the P trap; And
N trap or the 4th N-doped region in the P trap or the 4th P-doped region of the 3rd P+ doped region or the 3rd N+ doped region below.
2. thyristor according to claim 1 is characterized in that above-mentioned the 4th N-doped region or the 4th P-doped region form by the mode of implanting, and the energy of its implantation and dosage are according to required trigger voltage value decision.
3. thyristor according to claim 1 is characterized in that having isolation structure between each P+ doped region and the N+ doped region, has isolation structure between the doped region that the 3rd P+ doped region or the 3rd N+ doped region are adjacent.
4. a method that forms thyristor as claimed in claim 1 is characterized in that comprising
Semiconductor substrate is provided,
Form a plurality of well regions above above-mentioned Semiconductor substrate, these a plurality of well regions comprise N trap and P trap;
In above-mentioned a plurality of well regions, carry out shallow groove isolation structure;
Form at least one P+ doped region and at least one N+ doped region of separating by shallow groove isolation structure in above-mentioned a plurality of well regions at least one, and form at least one the 2nd P+ doped region and at least one the 2nd N+ doped region of separating by shallow groove isolation structure in above-mentioned a plurality of well region at least one;
Form the 3rd P+ doped region or the 3rd N+ doped region in the position that above-mentioned N trap engages with the P trap, isolate by shallow groove isolation structure between the 3rd P+ doped region or the 3rd N+ doped region and the adjacent doped region; And
Form the 4th N-doped region or the 4th P-doped region in N trap below the 3rd P+ doped region or the 3rd N+ doped region or the P trap.
5. method according to claim 4 is characterized in that above-mentioned the 4th N-doped region or the 4th P-doped region form by the mode of implanting, and the energy of its implantation and dosage are according to required trigger voltage value decision.
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Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034811A (en) * | 2010-09-21 | 2011-04-27 | 电子科技大学 | Low-voltage SCR (Silicon Controlled Rectifier) structure for ESD (Electronic Static Discharge) protection of integrated circuit chip |
| CN102157519A (en) * | 2011-01-28 | 2011-08-17 | 上海宏力半导体制造有限公司 | Silicon controlled rectifier |
| CN102208455A (en) * | 2011-03-29 | 2011-10-05 | 上海宏力半导体制造有限公司 | Silicon controlled rectifier |
| CN102290418A (en) * | 2010-06-21 | 2011-12-21 | 慧荣科技股份有限公司 | Electrostatic discharge protection device |
| CN102544115A (en) * | 2012-03-15 | 2012-07-04 | 电子科技大学 | ESD (Electro-Static discharge) protection device with low trigger voltage and high balllast resistance for SCR (Silicon Controlled Rectifier) |
| CN102545922A (en) * | 2010-12-30 | 2012-07-04 | 台湾积体电路制造股份有限公司 | Electrostatic discharge circuit for radio frequency transmitters |
| CN103354230A (en) * | 2013-07-12 | 2013-10-16 | 江苏艾伦摩尔微电子科技有限公司 | Electrostatic discharge protection TVS device of high maintenance voltage |
| CN103545310A (en) * | 2013-11-15 | 2014-01-29 | 上海贝岭股份有限公司 | PNPN type ESD protective device and ESD protective circuit |
| CN103579203A (en) * | 2013-08-06 | 2014-02-12 | 晶焱科技股份有限公司 | High-efficiency silicon controlled rectifier |
| CN104600104A (en) * | 2014-12-12 | 2015-05-06 | 上海贝岭股份有限公司 | Controllable silicon structure with high sustaining voltage |
| CN104795391A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection structure |
| CN106449635A (en) * | 2016-09-30 | 2017-02-22 | 上海华力微电子有限公司 | Novel low-trigger-voltage silicon-controlled rectifier and manufacturing method therefor |
| CN107546223A (en) * | 2017-08-22 | 2018-01-05 | 湘潭大学 | A kind of small island diode triggered thyristor electrostatic protection device of waffle-type |
| CN107731810A (en) * | 2017-09-06 | 2018-02-23 | 电子科技大学 | A kind of low trigger voltage MLSCR devices for ESD protection |
| CN108091650A (en) * | 2017-12-28 | 2018-05-29 | 上海华力微电子有限公司 | Without echo effect thyristor type esd protection structure and its implementation |
| CN108183101A (en) * | 2017-12-28 | 2018-06-19 | 上海华力微电子有限公司 | Without echo effect thyristor type esd protection structure and its implementation |
| CN109148441A (en) * | 2018-08-31 | 2019-01-04 | 上海华力微电子有限公司 | Suitable for high-tension circuit antistatic protection without echo effect thyristor |
| CN109273532A (en) * | 2018-09-12 | 2019-01-25 | 上海华力微电子有限公司 | Applied to high-tension circuit antistatic protection without echo effect thyristor |
| CN113990866A (en) * | 2021-12-28 | 2022-01-28 | 北京芯可鉴科技有限公司 | Silicon controlled rectifier, chip and circuit |
| CN117712121A (en) * | 2024-02-02 | 2024-03-15 | 芯联先锋集成电路制造(绍兴)有限公司 | Electrostatic discharge protection structure and manufacturing method thereof |
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2008
- 2008-10-10 CN CN200810168280A patent/CN101728428A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102290418A (en) * | 2010-06-21 | 2011-12-21 | 慧荣科技股份有限公司 | Electrostatic discharge protection device |
| CN102290418B (en) * | 2010-06-21 | 2015-12-16 | 慧荣科技股份有限公司 | Electrostatic discharge protective equipment |
| CN102034811B (en) * | 2010-09-21 | 2012-07-04 | 电子科技大学 | Low-voltage SCR (Silicon Controlled Rectifier) structure for ESD (Electronic Static Discharge) protection of integrated circuit chip |
| CN102034811A (en) * | 2010-09-21 | 2011-04-27 | 电子科技大学 | Low-voltage SCR (Silicon Controlled Rectifier) structure for ESD (Electronic Static Discharge) protection of integrated circuit chip |
| CN102545922B (en) * | 2010-12-30 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Electrostatic discharge circuit for radio frequency transmitters |
| CN102545922A (en) * | 2010-12-30 | 2012-07-04 | 台湾积体电路制造股份有限公司 | Electrostatic discharge circuit for radio frequency transmitters |
| CN102157519A (en) * | 2011-01-28 | 2011-08-17 | 上海宏力半导体制造有限公司 | Silicon controlled rectifier |
| CN102157519B (en) * | 2011-01-28 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Silicon controlled rectifier |
| CN102208455A (en) * | 2011-03-29 | 2011-10-05 | 上海宏力半导体制造有限公司 | Silicon controlled rectifier |
| CN102208455B (en) * | 2011-03-29 | 2016-01-06 | 上海华虹宏力半导体制造有限公司 | Thyristor |
| CN102544115B (en) * | 2012-03-15 | 2013-12-11 | 电子科技大学 | ESD (Electro-Static discharge) protection device with low trigger voltage and high balllast resistance for SCR (Silicon Controlled Rectifier) |
| CN102544115A (en) * | 2012-03-15 | 2012-07-04 | 电子科技大学 | ESD (Electro-Static discharge) protection device with low trigger voltage and high balllast resistance for SCR (Silicon Controlled Rectifier) |
| CN103354230B (en) * | 2013-07-12 | 2015-10-21 | 江苏艾伦摩尔微电子科技有限公司 | The electrostatic discharge protective TVS device of high maintenance voltage |
| CN103354230A (en) * | 2013-07-12 | 2013-10-16 | 江苏艾伦摩尔微电子科技有限公司 | Electrostatic discharge protection TVS device of high maintenance voltage |
| CN103579203B (en) * | 2013-08-06 | 2016-03-30 | 晶焱科技股份有限公司 | High-efficiency silicon control rectifying device |
| CN103579203A (en) * | 2013-08-06 | 2014-02-12 | 晶焱科技股份有限公司 | High-efficiency silicon controlled rectifier |
| CN103545310A (en) * | 2013-11-15 | 2014-01-29 | 上海贝岭股份有限公司 | PNPN type ESD protective device and ESD protective circuit |
| CN103545310B (en) * | 2013-11-15 | 2016-07-27 | 上海贝岭股份有限公司 | A kind of PNPN type ESD protective device and esd protection circuit |
| CN104795391B (en) * | 2014-01-21 | 2018-12-21 | 中芯国际集成电路制造(上海)有限公司 | ESD-protection structure |
| CN104795391A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection structure |
| CN104600104B (en) * | 2014-12-12 | 2018-04-27 | 上海贝岭股份有限公司 | Height keeps voltage SCR structure |
| CN104600104A (en) * | 2014-12-12 | 2015-05-06 | 上海贝岭股份有限公司 | Controllable silicon structure with high sustaining voltage |
| CN106449635A (en) * | 2016-09-30 | 2017-02-22 | 上海华力微电子有限公司 | Novel low-trigger-voltage silicon-controlled rectifier and manufacturing method therefor |
| CN107546223A (en) * | 2017-08-22 | 2018-01-05 | 湘潭大学 | A kind of small island diode triggered thyristor electrostatic protection device of waffle-type |
| CN107731810A (en) * | 2017-09-06 | 2018-02-23 | 电子科技大学 | A kind of low trigger voltage MLSCR devices for ESD protection |
| CN108183101A (en) * | 2017-12-28 | 2018-06-19 | 上海华力微电子有限公司 | Without echo effect thyristor type esd protection structure and its implementation |
| CN108091650A (en) * | 2017-12-28 | 2018-05-29 | 上海华力微电子有限公司 | Without echo effect thyristor type esd protection structure and its implementation |
| CN108183101B (en) * | 2017-12-28 | 2019-10-25 | 上海华力微电子有限公司 | Without echo effect thyristor type esd protection structure and its implementation |
| CN108091650B (en) * | 2017-12-28 | 2019-10-25 | 上海华力微电子有限公司 | Without echo effect thyristor type esd protection structure and its implementation |
| CN109148441A (en) * | 2018-08-31 | 2019-01-04 | 上海华力微电子有限公司 | Suitable for high-tension circuit antistatic protection without echo effect thyristor |
| CN109273532A (en) * | 2018-09-12 | 2019-01-25 | 上海华力微电子有限公司 | Applied to high-tension circuit antistatic protection without echo effect thyristor |
| CN113990866A (en) * | 2021-12-28 | 2022-01-28 | 北京芯可鉴科技有限公司 | Silicon controlled rectifier, chip and circuit |
| CN117712121A (en) * | 2024-02-02 | 2024-03-15 | 芯联先锋集成电路制造(绍兴)有限公司 | Electrostatic discharge protection structure and manufacturing method thereof |
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