CN108183101B - Without echo effect thyristor type esd protection structure and its implementation - Google Patents
Without echo effect thyristor type esd protection structure and its implementation Download PDFInfo
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- CN108183101B CN108183101B CN201711464508.7A CN201711464508A CN108183101B CN 108183101 B CN108183101 B CN 108183101B CN 201711464508 A CN201711464508 A CN 201711464508A CN 108183101 B CN108183101 B CN 108183101B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
Abstract
It includes: semiconductor substrate (80) that the present invention, which discloses a kind of no echo effect thyristor type esd protection structure and its implementation, the structure,；It is created on the N trap (60) and p-well (70) of semiconductor substrate；High concentration p-type adulterates (20), high concentration n-type doping (28) is placed in N trap (60) top, high concentration p-type adulterates (20), N trap (60) and p-well (70) constitute equivalent PNP triode structure, high concentration n-type doping (24), high concentration p-type doping (26) is placed in p-well (70) top, N trap (60), matrix (80)/p-well (70) and high concentration n-type doping (24) constitute equivalent N PN audion, high concentration n-type doping (22) is placed in above N trap (60) and p-well (70) boundary, the high concentration p-type adulterates (20), it is a part of N trap (60) between high concentration n-type doping (28) and spacing is S, it is N trap (6 between high concentration n-type doping (28) and high concentration p-type doping (22) 0) a part.
Description
Technical field
The present invention relates to semiconductor integrated circuit technology fields, rectify more particularly to a kind of novel no echo effect silicon control
Type esd protection structure and its implementation.
Background technique
The antistatic protection design of high-tension circuit is always a technical problem, this is because constituting the core of high-tension circuit
The heart: high tension apparatus (such as LDMOS) itself unlike common low-voltage device suitable for antistatic protection design, because of high tension apparatus
The characteristic that is showed of echo effect curve it is very poor.As shown in FIG. 1, FIG. 1 is the high tension apparatus that certain operating voltage is 32V
The echo effect curve graph of LDMOS, as can be drawn from Figure 1: 1) trigger voltage (Vt1) is excessively high；2) maintenance voltage (Vh) is too low, past
Toward the operating voltage well below high-tension circuit, high-tension circuit is easy to cause latch-up when working normally；3) second breakdown electricity
Stream (thermal breakdown electric current, It2) is too low, this is because because of device architecture characteristic part occurs for LDMOS when releasing ESD electric current
Caused by electric current congestion (Localized Current Crowding).
Thus industry is when solution high-tension circuit antistatic protection designs this technical problem, often using following
Two kinds of thinkings are realized: 1) being adjusted to the high-voltage device structure for antistatic protection module, optimize its echo effect song
Line is allowed to be suitable for antistatic protection design, but often practices ratio because of the reason of architectural characteristic of high tension apparatus itself
It is more difficult；2) it is together in series with a certain number of low pressure electrostatic-proof protection devices and constitutes the antistatic protection electricity that can bear high pressure
Road.Because the characteristic of low pressure electrostatic-proof protection device is relatively easily adjusted and controlled, industry especially integrated circuit is set
Meter company often prefers with a certain number of concatenated methods of low pressure electrostatic-proof protection device.
Because of the needs of high-tension circuit antistatic protection design window, this just imitates the hysteresis of low pressure electrostatic-proof protection device
It answers characteristic to have certain requirement, often requires that its echo effect window is the smaller the better, be preferably no echo effect, that is, hysteresis
The maintenance voltage and trigger voltage of effect are consistent substantially.Low pressure PMOS device is exactly a kind of common no echo effect electrostatic
Protective device, because parasitic PNP triode current gain when its generation echo effect is smaller, but low pressure PMOS device is not
Foot place is that the secondary breakdown current (It2) of its echo effect is smaller, so industry researchs and develops a kind of both do not had one after another
Echo effect and the electrostatic-proof protection device of secondary breakdown current with higher.
Industry proposed a kind of novel no echo effect thyristor (No-Snapback SCR) in 2015, such as
Shown in Fig. 2, specifically, entire esd protection structure is placed on matrix (Psub) 80, generates a N on 80 left side of matrix (Psub)
Trap (N-Well) 60 generates a p-well (P-Well) 70 on the right of matrix (Psub) 80, high concentration n-type doping (N+) 30, highly concentrated
Degree p-type adulterates (P+) 20, high concentration n-type doping (N+) 28 is placed in 60 top of N trap (N-Well), high concentration p-type doping (P+) 20,
N trap (N-Well) 60 and p-well (P-Well) 70 constitute equivalent PNP triode structure, high concentration n-type doping (N+) 24, highly concentrated
Degree p-type doping (P+) 26 is placed in 70 top of p-well (P-Well), N trap (N-Well) 60, matrix (Psub) 80/P trap (P-Well) 70
Equivalent N PN audion is constituted with high concentration n-type doping (N+) 24, high concentration p-type doping (P+) 22 is placed in N trap (N-Well)
60 with above p-well (P-Well) 70 boundary, and high concentration n-type doping (N+) 30, high concentration p-type adulterate (P+) 20, high concentration N-type
It is isolated between doping (N+) 28 with the shallow trench isolation layer (STI, ShallowTrenchIsolation) 10 that width is S, high concentration P
Type adulterates shallow trench isolation layer (STI, the Shallow Trench between (P+) 20, high concentration n-type doping (N+) 28
Isolation) 10 width is S, is N trap (N-Well) between high concentration n-type doping (N+) 28 and high concentration p-type doping (P+) 22
60 a part and spacing is D1, and high concentration n-type doping (N+) 28 and high concentration p-type doping (P+) 22 width are D2, highly concentrated
It spends 30 left side n-type doping (N+) and places shallow trench isolation layer (STI, Shallow Trench Isolation) 10, high concentration p-type
Adulterate (P+) 22, high concentration n-type doping (N+) 24, high concentration p-type doping (P+) 26 between with shallow trench isolation layer (STI,
Shallow Trench Isolation) 10 isolation, 26 right side placement shallow trench isolation layer of high concentration p-type doping (P+) (STI,
Shallow Trench Isolation)10；(P+) 20, high concentration n-type doping (N+) 30 are adulterated with metal connection high concentration p-type
The anode A for constituting the existing no echo effect thyristor type esd protection structure connects high concentration n-type doping (N with metal
+) 24, high concentration p-type doping (P+) 26 constitutes the cathode K that the existing no echo effect silicon control rectifies ESD device.
The experimental data of the existing no echo effect thyristor shows when high concentration n-type doping (N+) 28 and highly concentrated
When the size (width D 2) of degree p-type doping (P+) 22 reaches a certain level (4um), which shows no hysteresis
The characteristic of effect, as shown in figure 3, being very suitable to needs of the low-voltage device series connection for the design of high-tension circuit antistatic protection.But
The shortcomings that existing no echo effect thyristor is that device size is bigger, especially when what is needed connect,
Chip area is bigger.
Summary of the invention
In order to overcome the deficiencies of the above existing technologies, purpose of the present invention is to provide a kind of no echo effect silicon control is whole
Type esd protection structure and its implementation are flowed, to realize a kind of novel no hysteresis suitable for high-tension circuit antistatic protection
Effect thyristor, and reduce the size of device.
In view of the above and other objects, the present invention proposes a kind of no echo effect thyristor type esd protection structure, it should
Esd protection structure includes:
Semiconductor substrate (80)；
The N trap (60) and p-well (70) being created in the semiconductor substrate；
First high concentration p-type doping (20), the first high concentration n-type doping (28) are placed in N trap (60) top, the first high concentration
P-type adulterates (20), N trap (60) and p-well (70) constitute equivalent PNP triode structure, the second high concentration n-type doping (24), the
Two high concentration p-types doping (26) is placed in p-well (70) top, N trap (60), semiconductor substrate (80)/p-well (70) and the second high concentration
N-type doping (24) constitutes equivalent N PN audion, and third high concentration p-type doping (22) is placed in N trap (60) and p-well (70) point
Top at boundary, between the first high concentration p-type doping (20), the first high concentration n-type doping (28) for N trap (60) a part and
Spacing is S, is one of N trap (60) between the first high concentration n-type doping (28) and third high concentration p-type doping (22)
Point.
Further, shallow trench isolation layer (10) are placed on the left of the first high concentration p-type doping (20).
Further, the third high concentration p-type adulterates (22), the second high concentration n-type doping (24), the second high concentration P
Type is isolated between adulterating (26) with shallow trench isolation layer (10).
Further, the first high concentration p-type is connected using metal adulterate (20), the first high concentration n-type doping (28)
The anode A for constituting the esd protection structure connects the second high concentration n-type doping (24), the second high concentration p-type using metal
Doping (26) constitutes the cathode K of the esd protection structure.
The first high concentration n-type doping (28) and third high concentration p-type doping (22) spacing are D1, in the range of 0~
2um, the first high concentration n-type doping (28) width are D2, in the range of 0.2um~10um, the doping of third high concentration p-type
(22) width is D3, and in the range of 0.2um~10um, the first high concentration p-type adulterates (20), the first high concentration n-type doping (28)
Between be a part of N trap (60) and spacing is S, in the range of 0.2um~10um.
Further, the esd protection structure is by adjusting the width D 2 and the of the first high concentration n-type doping (28)
The size of the width D 3 of three high concentration p-types doping (22) and the first high concentration n-type doping (28) and the first high concentration P
Type adulterates the distance between (20) S to adjust maintenance voltage to realize no echo effect characteristic.
Further, the esd protection structure is by adjusting the first high concentration n-type doping (28) and third high concentration
The size of the space D 1 of p-type doping (22) adjusts trigger voltage when its echo effect in a certain range.
In order to achieve the above objectives, the present invention also provides a kind of realities of no echo effect thyristor type esd protection structure
Existing method, includes the following steps:
Step 1 provides semi-conductive substrate；
Step 2 generates N trap and p-well in the semiconductor substrate；
First high concentration p-type doping (20), the first high concentration n-type doping (28) are placed in N trap (60) top by step 3,
First high concentration p-type adulterates (20), N trap (60) and p-well (70) and constitutes equivalent PNP triode structure, and the second high concentration N-type is mixed
Miscellaneous (24), the second high concentration p-type doping (26) are placed in p-well (70) top, N trap (60), semiconductor substrate (80)/p-well (70) with
Second high concentration n-type doping (24) constitute equivalent N PN audion, third high concentration p-type doping (22) be placed in N trap (60) with
It is N trap (60) between the first high concentration p-type doping (20), the first high concentration n-type doping (28) above p-well (70) boundary
A part and spacing be S, be between the first high concentration n-type doping (28) and third high concentration p-type doping (22) N trap (60)
A part.
Further, the method also includes width Ds 2 and the by adjusting the first high concentration n-type doping (28)
The size of the width D 3 of three high concentration p-types doping (22) and the first high concentration n-type doping (28) and the first high concentration P
Type adulterates the distance between (20) S to adjust maintenance voltage to realize no echo effect characteristic.
Further, the method also includes: pass through and adjust the first high concentration n-type doping (28) and third high concentration
The size of the space D 1 of p-type doping (22) adjusts trigger voltage when its echo effect in a certain range.
Compared with prior art, the present invention discloses a kind of no echo effect thyristor type esd protection structure and in fact
Existing method, on the basis of existing no echo effect thyristor, by the N trap as reduction protection ring of original suspension joint
In N-type heavy doping and left side p-type heavy doping between shallow trench isolations layer remove, and by the N-type heavy doping directly and silicon
The anode of control rectifier is connected directly, and constitutes reinforced protection ring, when echo effect occurs, is injected into hole from anode
N trap simultaneously reaches N trap/p-well influence degree (barrier effectiveness) and greatly improves, required when can greatly reduce realization without echo effect
Protection ring width, reduce device size, in addition the N-type heavy doping is played the role of N trap and picked out a little simultaneously, it is possible to together
When the N trap that is initially positioned on the left of anode of removal pick out a little, device size may further be reduced.
Detailed description of the invention
Fig. 1 is high tension apparatus LDMOS echo effect curve graph；
Fig. 2 is the structural schematic diagram of existing no echo effect thyristor；
Fig. 3 is existing thyristor echo effect curve and D2 relational graph；
Fig. 4 is a kind of circuit knot of the preferred embodiment of no echo effect thyristor type esd protection structure of the present invention
Composition；
Fig. 5 is a kind of step process of the implementation method of no echo effect thyristor type esd protection structure of the present invention
Figure；
Fig. 6 is application scenarios schematic diagram of the invention.
Specific embodiment
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand further advantage and effect of the invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from
Various modifications and change are carried out under spirit of the invention.
Fig. 4 is a kind of circuit knot of the preferred embodiment of no echo effect thyristor type esd protection structure of the present invention
Composition.As shown in figure 4, the present invention discloses a kind of no echo effect thyristor type esd protection structure, including multiple shallow channels
Separation layer (STI, Shallow Trench Isolation) the 10, first high concentration p-type adulterates (P+) 20, third high concentration p-type
It adulterates (P+) 22, second the 24, second high concentration p-type of high concentration n-type doping (N+) and adulterates (P+) 26, first high concentration n-type doping
(N+) 28, N trap (N-Well) 60, p-well (P-Well) 70 and semiconductor substrate (Psub) 80.
Entire esd protection structure is placed in semiconductor substrate (Psub) 80, is generated on 80 left side of semiconductor substrate (Psub)
One N trap (N-Well) 60 generates a p-well (P-Well) 70, the first high concentration p-type on 80 the right of semiconductor substrate (Psub)
Doping (P+) 20, first high concentration n-type doping (N+) 28 is placed in 60 top of N trap (N-Well), and the first high concentration p-type adulterates (P+)
20, N trap (N-Well) 60 and p-well (P-Well) 70 constitute equivalent PNP triode structure, the second high concentration n-type doping (N+)
24, the second high concentration p-type doping (P+) 26 is placed in 70 top of p-well (P-Well), N trap (N-Well) 60, semiconductor substrate
(Psub) 80/P trap (P-Well) 70 and the second high concentration n-type doping (N+) 24 constitute equivalent N PN audion, and third is highly concentrated
Degree p-type doping (P+) 22 is placed in above N trap (N-Well) 60 and p-well (P-Well) 70 boundary, and the first high concentration p-type adulterates (P
+) it is a part of N trap (N-Well) 60 between the 20, first high concentration n-type doping (N+) 28 and spacing is S, the first high concentration N-type
Adulterating is a part of N trap (N-Well) 60 between (N+) 28 and third high concentration p-type doping (P+) 22 and spacing is D1, the model of D1
It encloses for 0~2um, 28 width of the first high concentration n-type doping (N+) is D2, and D2 range is 0.2um~10um, preferred values 2um, the
It is D3 that three high concentration p-types, which adulterate (P+) 22 width, and D3 range is 0.2um~10um, preferred values 2um, and the first high concentration p-type mixes
It is a part of N trap (60) between miscellaneous (20), the first high concentration n-type doping (28) and spacing is S, S range is 0.2um~10um,
First high concentration p-type adulterates 20 left side (P+) and places shallow trench isolation layer (STI, Shallow Trench Isolation) 10,
Third high concentration p-type is used shallowly between adulterating (P+) 22, second the 24, second high concentration p-type of high concentration n-type doping (N+) doping (P+) 26
Channel isolation layer (STI, Shallow Trench Isolation) 10 is isolated, and 26 right side of the second high concentration p-type doping (P+) is put
Set shallow trench isolation layer (STI, Shallow Trench Isolation) 10；The first high concentration p-type, which is connected, with metal adulterates (P
+) the 20, first high concentration n-type doping (N+) 28 constitute the novel no echo effect thyristor type esd protection structure anode
A connects second the 24, second high concentration p-type of high concentration n-type doping (N+) doping (P+) 26 with metal and constitutes novel no hysteresis effect
Answer the cathode K of silicon control rectification ESD device.
As it can be seen that the present invention is in existing no echo effect silicon without echo effect thyristor type esd protection structure
Being realized on the basis of control rectifier (such as Fig. 2).The of first high concentration p-type doping (P+) 20 and its right side in N trap of the present invention
One high concentration n-type doping (N+) 28 is connected directly to anode (Anode) A, the first high concentration n-type doping (N+) 28 because directly and
Anode is connected, the positive voltage with higher when echo effect occurs, so reinforced protection ring (guard can be played
Ring effect), in addition the present invention will be between the first high concentration p-type doping (P+) 20 and the first high concentration n-type doping (N+) 28
Shallow trench isolations layer (STI) removal, compared to the suspension joint structure in existing no echo effect thyristor, can drop significantly
(P+) 20 is adulterated from P knot the first high concentration p-type in the hole of parasitic PNP triode in the low novel thyristor) it is injected into N
In trap (N-Well) 60 and the efficiency at 70 interface of N trap (N-Well) 60 and p-well (P-Well) is reached, to further reduced this
The current gain of parasitic triode, that is, this protection ring (Guard Ring) are more efficient.So relative to existing
Without the novel silicon-controlled rectifier structure of echo effect, width D 2 and the third high concentration p-type of the first high concentration n-type doping (N+) 28 are mixed
The width D 3 of miscellaneous (P+) 22 can design smaller.Still further aspect, the first high concentration n-type doping (N+) 28 and anode A are direct
It is connected, the effect of 60 contact point of N trap (N-Well) is had both, so the N trap (N- of the device leftmost side can will be initially positioned at herein
Well) 60 contact point N-type heavily doped regions (N+) 30 remove, and can further reduce device size, save chip area.
The present invention can be by adjusting this without the first high concentration N-type in echo effect thyristor type esd protection structure
Adulterate the size and the first high concentration N-type of the width D 2 of (N+) 28 and the width D 3 of third high concentration p-type doping (P+) 22
Doping (N+) 28 and the first high concentration p-type adulterate (P+) the distance between 20 S and realize no echo effect to adjust maintenance voltage
Characteristic, can be by adjusting this without the first high concentration n-type doping (N+) 28 in echo effect thyristor type esd protection structure
The size for adulterating the space D 1 between (P+) 22 with third high concentration p-type adjusts triggering electricity when its echo effect in a certain range
It presses (Vt1).
Fig. 5 is a kind of step process of the implementation method of no echo effect thyristor type esd protection structure of the present invention
Figure.As shown in figure 5, a kind of implementation method of no echo effect thyristor type esd protection structure of the present invention, including walk as follows
It is rapid:
Step 501, semi-conductive substrate is provided, in the specific embodiment of the invention, provides a P type substrate (P-Sub) 80.
Step 502, N trap and p-well, i.e. N trap (N-Well) 60, p-well (P-Well) 70 are generated in the semiconductor substrate,
In the specific embodiment of the invention, a N trap (N-Well) 60 is generated on 80 left side of P-type semiconductor substrate (P-Sub), in semiconductor
80 the right of substrate (Psub) generates a p-well (P-Well) 70.
Step 503, the first high concentration p-type doping (P+) 20, first high concentration n-type doping (N+) 28 is placed in N trap (N-
Well) 60 top, the first high concentration p-type adulterate (P+) 20, N trap (N-Well) 60 and p-well (P-Well) 70 and constitute equivalent PNP
Audion, second the 24, second high concentration p-type of high concentration n-type doping (N+) doping (P+) 26 are placed in p-well (P-Well) 70
Portion, 24 structure of N trap (N-Well) 60, semiconductor substrate (Psub) 80/P trap (P-Well) 70 and the second high concentration n-type doping (N+)
At equivalent N PN audion, third high concentration p-type doping (P+) 22 is placed in N trap (N-Well) 60 and 70 points of p-well (P-Well)
It is N trap (N-Well) one of 60 between the first high concentration p-type doping (P+) 20, first high concentration n-type doping (N+) 28 above at boundary
Part and spacing are S, are N trap (N-Well) between the first high concentration n-type doping (N+) 28 and third high concentration p-type doping (P+) 22
60 a part and spacing is D1, and 28 width of the first high concentration n-type doping (N+) is D2, and third high concentration p-type adulterates (P+) 22
Width is D3, the first high concentration p-type adulterate 20 left side (P+) place shallow trench isolation layer (STI,
ShallowTrenchIsolation) 10, third high concentration p-type adulterates (P+) 22, second high concentration n-type doping (N+) 24, the
Two high concentration p-types are isolated between adulterating (P+) 26 with shallow trench isolation layer (STI, ShallowTrench Isolation) 10, and second
High concentration p-type adulterates 26 right side (P+) and places shallow trench isolation layer (STI, ShallowTrench Isolation) 10.
Step 504, the first high concentration p-type is connected using metal adulterate 28 structure of (P+) 20, first high concentration n-type doping (N+)
At the anode A without echo effect thyristor type esd protection structure, the second high concentration n-type doping (N is connected using metal
+) the 24, second high concentration p-type doping (P+) 26 constitute the cathode K without echo effect thyristor type esd protection structure.
New E SD of the invention can be applied in the protection circuit of the input/output terminal in esd protection circuit and electric
In the protection circuit of source over the ground, the ESD protection capability of Lai Tisheng chip entirety, as shown in Figure 6.
As it can be seen that the first high concentration p-type in N trap is adulterated the first high concentration n-type doping on (P+) 20 and its right side by the present invention
(N+) it 28 is connected directly to anode (Anode), the first high concentration n-type doping (N+) 28 is occurring because being directly connected with anode
Positive voltage with higher when echo effect, so reinforced protection ring (guardring) can be played the role of, other this hair
The bright shallow trench isolations layer (STI) by between the first high concentration p-type doping (P+) 20 and the first high concentration n-type doping (N+) 28 is gone
It removes, compared to the suspension joint structure having in novel no echo effect thyristor, novel silicon control rectification can be substantially reduced
The hole of parasitic PNP triode is injected into N trap (60) from P knot (the first high concentration p-type doping 20) and reaches N trap in device
(60) and the efficiency at p-well (70) interface, to further reduced the current gain of the triode of the parasitism, that is, this guarantor
Retaining ring (GuardRing) it is more efficient.So first is high relative to the existing no novel silicon-controlled rectifier structure of echo effect
The width D 3 of width D 2 and third high concentration p-type doping (P+) 22 of concentration N-dopant (N+) 28 can design smaller.In addition
On the one hand, the first high concentration n-type doping (N+) 28 and anode A are connected directly, and have both the effect of N trap contact point, so may be used herein
To remove the N trap contact point for being initially positioned at the device leftmost side, device size is further reduced, chip area is saved.
In conclusion the present invention discloses a kind of no echo effect thyristor type esd protection structure and its implementation,
On the basis of existing no echo effect thyristor, by the N-type in the N trap as reduction protection ring of original suspension joint
Between heavy doping and the p-type heavy doping in left side shallow trench isolations layer removal, and by the N-type heavy doping directly and thyristor
Anode be connected directly, constitute reinforced protection ring, echo effect occur when, to hole from anode be injected into N trap and to
It is greatly improved up to N trap/p-well influence degree (barrier effectiveness), protection required when realizing without echo effect can be greatly reduced
The width of ring reduces device size, and in addition the N-type heavy doping is played the role of N trap and picked out a little simultaneously, it is possible to remove simultaneously
It is initially positioned at the N trap on the left of anode to pick out a little, device size can be further reduced.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Without departing from the spirit and scope of the present invention, modifications and changes are made to the above embodiments by field technical staff.Therefore,
The scope of the present invention, should be as listed in the claims.
Claims (7)
1. a kind of no echo effect thyristor type esd protection structure, which is characterized in that the esd protection structure includes:
Semiconductor substrate (80)；
The N trap (60) and p-well (70) being created in the semiconductor substrate；
First high concentration p-type doping (20), the first high concentration n-type doping (28) are placed in N trap (60) top, the first high concentration p-type
Adulterate (20), N trap (60) and p-well (70) constitute equivalent PNP triode structure, the second high concentration n-type doping (24), second high
Concentration of P type doping (26) is placed in p-well (70) top, N trap (60), semiconductor substrate (80)/p-well (70) and the second high concentration N-type
It adulterates (24) and constitutes equivalent N PN audion, third high concentration p-type doping (22) is placed in N trap (60) and p-well (70) boundary
Top is a part and spacing of N trap (60) between the first high concentration p-type doping (20), the first high concentration n-type doping (28)
It is a part of N trap (60) for S, between the first high concentration n-type doping (28) and third high concentration p-type doping (22)；
Shallow trench isolation layer (10) are placed on the left of the first high concentration p-type doping (20)；
It is used between the third high concentration p-type doping (22), the second high concentration n-type doping (24), the second high concentration p-type doping (26)
Shallow trench isolation layer (10) isolation；
Shallow trench isolation layer (10) are placed on the right side of the second high concentration p-type doping (26)；
The first high concentration p-type doping (20) is connected using metal, the first high concentration n-type doping (28) constitutes the ESD and protects
The anode A of structure connects the second high concentration n-type doping (24) using metal, the second high concentration p-type doping (26) is constituted and is somebody's turn to do
The cathode K of esd protection structure.
2. a kind of no echo effect thyristor type esd protection structure as described in claim 1, it is characterised in that: described
First high concentration n-type doping (28) and third high concentration p-type doping (22) spacing are D1, in the range of 0~2um, described first
High concentration n-type doping (28) width is D2, and in the range of 0.2um~10um, it is D3 that third high concentration p-type, which adulterates (22) width,
It is N trap between the first high concentration p-type doping (20), the first high concentration n-type doping (28) in the range of 0.2um~10um
(60) a part and spacing is S, in the range of 0.2um~10um.
3. a kind of no echo effect thyristor type esd protection structure as claimed in claim 2, it is characterised in that: described
Esd protection structure adulterates (22) by the width D 2 and third high concentration p-type for adjusting the first high concentration n-type doping (28)
The distance between the size of width D 3 and the first high concentration n-type doping (28) and the first high concentration p-type doping (20) S
To adjust maintenance voltage to realize no echo effect characteristic.
4. a kind of no echo effect thyristor type esd protection structure as claimed in claim 2, it is characterised in that: described
Esd protection structure is by adjusting the first high concentration n-type doping (28) and the space D 1 of third high concentration p-type doping (22)
Size adjusts trigger voltage when its echo effect in a certain range.
5. a kind of implementation method of no echo effect thyristor type esd protection structure, includes the following steps:
Step 1 provides semi-conductive substrate；
Step 2 generates N trap and p-well in the semiconductor substrate；
First high concentration p-type is adulterated (20), the first high concentration n-type doping (28) and is placed in N trap (60) top by step 3, and first
High concentration p-type adulterates (20), N trap (60) and p-well (70) and constitutes equivalent PNP triode structure, the second high concentration n-type doping
(24), the second high concentration p-type doping (26) is placed in p-well (70) top, N trap (60), semiconductor substrate (80)/p-well (70) and the
Two high concentration n-type dopings (24) constitute equivalent N PN audion, and third high concentration p-type doping (22) is placed in N trap (60) and P
It is N trap (60) between the first high concentration p-type doping (20), the first high concentration n-type doping (28) above trap (70) boundary
A part and spacing are S, are the one of N trap (60) between the first high concentration n-type doping (28) and third high concentration p-type doping (22)
Part；Shallow trench isolation layer (10) are placed on the left of the first high concentration p-type doping (20)；The third high concentration p-type doping
(22), it is isolated between the second high concentration n-type doping (24), the second high concentration p-type doping (26) with shallow trench isolation layer (10)；It is described
Second high concentration p-type is adulterated and places shallow trench isolation layer (10) on the right side of (26)；
The first high concentration p-type doping (20) is connected using metal, the first high concentration n-type doping (28) constitutes the ESD and protects
The anode A of structure connects the second high concentration n-type doping (24) using metal, the second high concentration p-type doping (26) is constituted and is somebody's turn to do
The cathode K of esd protection structure.
6. a kind of implementation method of no echo effect thyristor type esd protection structure as claimed in claim 5, feature
It is, the method also includes: width D 2 and third high concentration p-type by adjusting the first high concentration n-type doping (28)
Adulterate (22) width D 3 size and the first high concentration n-type doping (28) and the first high concentration p-type doping (20) it
Between distance S adjust maintenance voltage to realize no echo effect characteristic.
7. a kind of implementation method of no echo effect thyristor type esd protection structure as claimed in claim 5, feature
It is, the method also includes: by adjusting the first high concentration n-type doping (28) and third high concentration p-type doping (22)
Trigger voltage when adjusting its echo effect in a certain range of the size of space D 1.
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| CN109037203A (en) * | 2018-07-13 | 2018-12-18 | 上海华力微电子有限公司 | Thyristor type esd protection structure and implementation method |
| CN109065535A (en) * | 2018-08-20 | 2018-12-21 | 上海华力微电子有限公司 | A kind of silicon-controlled rectifier structure and its manufacturing method |
| CN109148441A (en) * | 2018-08-31 | 2019-01-04 | 上海华力微电子有限公司 | Suitable for high-tension circuit antistatic protection without echo effect thyristor |
| CN109273532B (en) * | 2018-09-12 | 2022-03-11 | 上海华力微电子有限公司 | Silicon controlled rectifier without hysteresis effect for high-voltage circuit anti-static protection |
| CN111244090B (en) * | 2020-03-27 | 2023-12-01 | 上海华力微电子有限公司 | Bidirectional silicon controlled rectifier and preparation method thereof |
| CN111403382A (en) * | 2020-03-27 | 2020-07-10 | 上海华力微电子有限公司 | Bidirectional silicon controlled rectifier and preparation method thereof |
| CN111354724A (en) * | 2020-04-27 | 2020-06-30 | 上海华力微电子有限公司 | Silicon controlled rectifier and manufacturing method thereof |
| CN111403384B (en) * | 2020-04-28 | 2023-11-03 | 上海华力微电子有限公司 | Silicon controlled rectifier and manufacturing method thereof |
| CN111370409B (en) * | 2020-04-28 | 2023-11-03 | 上海华力微电子有限公司 | Silicon controlled rectifier and manufacturing method thereof |
| CN112510033A (en) * | 2020-10-14 | 2021-03-16 | 上海华力微电子有限公司 | Silicon controlled rectifier and manufacturing method thereof |
| CN112635458B (en) * | 2020-10-14 | 2024-04-30 | 上海华力微电子有限公司 | Silicon controlled rectifier and manufacturing method thereof |
| CN112117269A (en) * | 2020-10-30 | 2020-12-22 | 上海华力微电子有限公司 | Silicon controlled rectifier type ESD (electro-static discharge) protection structure without hysteresis effect and implementation method thereof |
| CN112086451A (en) * | 2020-10-30 | 2020-12-15 | 上海华力微电子有限公司 | Silicon controlled rectifier type ESD (electro-static discharge) protection structure without hysteresis effect and implementation method thereof |
| US11652097B2 (en) * | 2020-11-30 | 2023-05-16 | Amazing Microelectronic Corp. | Transient voltage suppression device |
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