CN106449635A - Novel low-trigger-voltage silicon-controlled rectifier and manufacturing method therefor - Google Patents
Novel low-trigger-voltage silicon-controlled rectifier and manufacturing method therefor Download PDFInfo
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- CN106449635A CN106449635A CN201610875402.5A CN201610875402A CN106449635A CN 106449635 A CN106449635 A CN 106449635A CN 201610875402 A CN201610875402 A CN 201610875402A CN 106449635 A CN106449635 A CN 106449635A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 35
- 239000010703 silicon Substances 0.000 title claims abstract description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 230000015556 catabolic process Effects 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000011159 matrix material Substances 0.000 claims description 44
- 238000002955 isolation Methods 0.000 claims description 16
- 239000007943 implant Substances 0.000 claims description 15
- 238000009792 diffusion process Methods 0.000 claims description 10
- 238000005242 forging Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 7
- 238000003780 insertion Methods 0.000 claims description 3
- 230000037431 insertion Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 7
- 238000002513 implantation Methods 0.000 abstract 2
- 238000002360 preparation method Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
Abstract
The invention discloses a novel low-trigger-voltage silicon-controlled rectifier and a manufacturing method therefor. The rectifier comprises a semiconductor basal body, an N well (50), a P well (60), an equivalent PNP triode structure, an equivalent NPN triode structure, a heavily-doped N junction, and an ESD implantation layer (40), wherein the N well (50) is generated on one side of the basal body while the P well (60) is generated on the other side of the basal body; the equivalent PNP triode structure is formed in the N well (50) through doping; the equivalent NPN triode structure is formed in the P well (60) through doping; the heavily-doped N junction is inserted between the N well and the P well; and the ESD implantation layer (40) is formed in a P well region below the N junction. According to the novel low-trigger-voltage silicon-controlled rectifier, by additionally setting a P type heavily-doped ESD-IMP in the P well region below the N junction between the N well and the P well of the existing silicon-controlled rectifier, an N+/P+ diode in a vertical direction is formed by the N junction and the ESD-IMP below the N junction, so that the reverse breakdown voltage on the P well from the N well is further lowered, and the trigger voltage of a hysteresis effect of the silicon-controlled rectifier is further lowered.
Description
Technical field
The present invention relates to semiconductor integrated circuit technical field, more particularly to a kind of new low trigger voltage silicon control rectification
Device (SCR) and preparation method thereof.
Background technology
In ESD design protection field, thyristor (SCR) is extensively paid attention to because having the strong characteristic of ESD discharge capacity,
But such device has two major defects limits its application：First defect is the triggering of snapback (echo effect)
Voltage is very high, because its trigger voltage is mainly limited to the breakdown reverse voltage of p-well by N trap；Second defect is snapback
Hold on (maintenance) voltage of (echo effect) very low it is easy to lead to latch-up.
For above-mentioned first defect, current industrial circle proposes some schemes to reduce snapback's (echo effect)
Trigger voltage.Fig. 1 is a kind of structural representation of thyristor (SCR) in prior art, as shown in figure 1, this silicon control rectification
Device (SCR) includes multiple shallow trench isolation layers (STI, Shallow Trench Isolation) 10, high concentration n-type doping (N+)
20th, high concentration p-type doping (P+) 22, high concentration n-type doping (N+) 24, high concentration n-type doping (N+) 26, the doping of high concentration p-type
(P+) 28, N trap (N-Well) 50, p-well (P-Well) 60, matrix (Psub) 70.
Whole device is placed on matrix (Psub) 70, generates a N trap (N-Well) 50 on matrix (Psub) 70 left side,
Matrix (Psub) 70 the right generates a p-well (P-Well) 60, high concentration n-type doping (N+) 20, high concentration p-type doping (P+) 22
It is placed in N trap (N-Well) 50 top, high concentration p-type doping (P+) 22, N trap (N-Well) 50 and matrix (Psub) 70 are constituted etc.
Effect PNP triode structure, high concentration n-type doping (N+) 20 and N trap (N-Well) 50 formation diffusion resistance Equivalent conjunction to this PNP
Transistor base, high concentration p-type doping (P+) 22 constitutes the emitter stage PN junction of this PNP triode, matrix with N trap (N-Well) 50
(Psub) 70 with N trap (N-Well) 50 constitute this PNP triode colelctor electrode PN junction, high concentration n-type doping (N+) 26, high concentration
P-type doping (P+) 28 is placed in p-well (P-Well) 60 top, N trap (N-Well) 50, matrix (Psub) 70 and high concentration n-type doping
(N+) 26 composition equivalent N PN audion, N trap (N-Well) 50 constitutes the current collection of this NPN triode with matrix (Psub) 70
Pole PN junction, matrix (Psub) 70 constitutes the emitter stage PN junction of equivalent N PN audion, high concentration P with high concentration n-type doping (N+) 26
Type doping (P+) 26, p-well (P-Well) 60, matrix (Psub) 70 constitute diffusion resistance and connect to the base of this equivalent N PN audion
Pole, high concentration n-type doping (N+) 24 is placed in above N trap (N-Well) 50 and p-well (P-Wel) 60 boundary, high concentration n-type doping
(N+) 20, high concentration p-type doping (P+) 22, high concentration n-type doping (N+) 24, high concentration n-type doping (N+) 26, high concentration p-type
With shallow trench isolation layer (STI, Shallow Trench Isolation) 10 isolation between doping (P+) 28；Connected highly concentrated with metal
Degree n-type doping (N+) 20, high concentration p-type doping (P+) 22 constitute the anode A of this new low trigger voltage silicon control ESD device, high
Concentration N-dopant (N+) 26, high concentration p-type doping (P+) 28 are the moon of the present invention new low trigger voltage silicon control ESD device
Pole K.
It is (highly concentrated that this thyristor passes through one heavily doped N knot across N trap and p-well of insertion between N trap and p-well
Degree n-type doping (N+) 24), thus reducing the purpose of the breakdown reverse voltage to p-well for the N trap, but reversely the hitting of the peering p-well of N
Wear voltage still also higher.
For reducing trigger voltage further, another kind of prior art thyristor (SCR) type ESD device is by the height on right side
Concentration N-dopant (N+) 26, high concentration p-type doping (P+) 28 move right, as shown in Fig. 2 in the p-well (P- being newly available
Well) 60 top increases by a N-type gate control diode 30, and connects to the negative electrode K of this thyristor (SCR), thus reaching
Reduce the purpose of the breakdown reverse voltage to p-well for the N trap further, but even so, the triggering of the thyristor shown in Fig. 2
Voltage is still relatively higher, and this trigger voltage is also constrained to existing technological parameter, and adjustment degree of freedom is little.
Content of the invention
For overcoming the shortcomings of above-mentioned prior art presence, the purpose of the present invention is to provide a kind of new low trigger voltage silicon
Control rectifier and preparation method thereof, it is by the p-well region of the N side of forging between the N trap of existing thyristor and p-well
Additionally add the heavily doped ESD_IMP of one p-type so that this N knot and ESD_IMP below form a vertical direction
N+/P+ (ESD_IMP) diode, thus reduce the breakdown reverse voltage to p-well for the N trap further.
For reaching above and other purpose, the present invention proposes a kind of new low trigger voltage silicon control rectifier, this commutator bag
Include：
Semiconductor substrate；
It is created on N trap (50) and the opposite side p-well (60) of side in described semiconductor substrate (70)；
Pass through the equivalent PNP triode structure that formed of doping in described N trap (50) and pass through doping in described p-well (60)
The equivalent N PN audion being formed；
It is inserted in the heavily doped N knot between described N trap and described p-well；
It is formed at the ESD implant layer (40) of the p-well region of the described N side of forging.
Further, high concentration n-type doping (20), high concentration p-type doping (22) are placed in described N trap (50) top, highly concentrated
Degree p-type doping (P+) 22, N trap (N-Well) 50 and matrix (Psub) 70 constitute equivalent PNP triode structure.
Further, described high concentration n-type doping (20) and described N trap (50) form diffusion resistance Equivalent conjunction and extremely should
PNP triode base stage, described high concentration p-type doping (22) and described N trap (50) constitute the emitter stage PN junction of this PNP triode,
Described matrix and described N trap (50) constitute the colelctor electrode PN junction of this PNP triode.
Further, high concentration n-type doping (26), high concentration p-type doping (28) are placed in described p-well (60) top, institute
State N trap (50), matrix and described high concentration n-type doping (26) and constitute described equivalent N PN audion.
Further, described N trap (50) and described matrix constitute the colelctor electrode PN junction of this NPN triode, described matrix 70
Constitute the emitter stage PN junction of described equivalent N PN audion, described high concentration p-type doping with described high concentration n-type doping (26)
(28), p-well (60), matrix constitute diffusion resistance and connect to the base stage of this equivalent N PN audion.
Further, described high concentration n-type doping (20), high concentration p-type doping (22), described N knot, high concentration N-type are mixed
Isolated with shallow trench isolation layer 10 between miscellaneous (26), high concentration p-type doping (28).
Further, described thyristor is adjusted by adjusting the dosage of the ESD_IMP of described ESD implant layer (40)
The breakdown reverse voltage of N+/P+ (ESD_IMP) diode of vertical direction that this N ties and this ESD implant layer (40) is formed.
For reaching above-mentioned purpose, the present invention also provides a kind of manufacture method of new low trigger voltage silicon control rectifier, bag
Include following steps：
Step one, provides semiconductor substrate (70)；
Step 2, generates a N trap (50) in the side of semiconductor substrate (70), in described matrix (70) opposite side
Generate a p-well (60)；
Step 3, passes through doping in described N trap (50) and forms equivalent PNP triode structure, passes through to mix in described p-well (60)
Miscellaneous formation equivalent N PN audion；
Step 4, inserts a heavily doped N across N trap and p-well between described N trap (50) and described p-well (60)
Knot；
Step 5, adds ESD implant layer (40) in the p-well region of this N side of forging.
Further, in step 5, adjust this N by adjusting the dosage of the ESD_IMP of described ESD implant layer (40)
The breakdown reverse voltage of the N+/P+ diode of vertical direction that knot and this ESD implant layer (40) are formed.
Further, the performance of the trigger voltage according to this thyristor and leakage current determines optimal ESD_IMP agent
Amount.
Compared with prior art, a kind of new low trigger voltage silicon control rectifier of the present invention and preparation method thereof, it passes through
The extra heavily doped ESD_ adding p-type together of the p-well region of the N side of forging between the N trap of existing thyristor and p-well
IMP is so that this N knot and ESD_IMP below form N+/P+ (ESD_IMP) diode of a vertical direction, thus entering one
Step reduces the breakdown reverse voltage to p-well for the N trap.
Brief description
Fig. 1 is a kind of structural representation of thyristor in prior art；
Fig. 2 is the structural representation of another kind of thyristor in prior art；
Fig. 3 is a kind of circuit structure diagram of the preferred embodiment of new low trigger voltage silicon control rectifier of the present invention；
Fig. 4 is a kind of flow chart of steps of the manufacture method of new low trigger voltage silicon control rectifier of the present invention；
Fig. 5 is the application scenarios schematic diagram of the present invention.
Specific embodiment
Below by way of specific instantiation and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand further advantage and effect of the present invention by content disclosed in the present specification easily.The present invention also can be by other different
Instantiation implemented or applied, the every details in this specification also can be based on different viewpoints and application, without departing substantially from
Carry out various modification and change under the spirit of the present invention.
Fig. 3 is a kind of circuit structure diagram of the preferred embodiment of new low trigger voltage silicon control rectifier of the present invention.As Fig. 3
Shown, a kind of new low trigger voltage silicon control rectifier (SCR) of the present invention, including matrix (Psub) 70, in matrix (Psub) 70
Side generates a N trap (N-Well) 50, generates a p-well (P-Well) 60 in matrix (Psub) 70 opposite side, in the present invention
In preferred embodiment, N trap 50 is arranged at matrix (Psub) 70 left side, and p-well (P-Well) 60 is arranged on the right of matrix (Psub) 70,
High concentration n-type doping (N+) 20, high concentration p-type doping (P+) 22 are placed in N trap (N-Well) 50 top, high concentration p-type doping (P
+) 22, N trap (N-Well) 50 and matrix (Psub) 70 constitute equivalent PNP triode structure, high concentration n-type doping (N+) 20 with
N trap (N-Well) 50 forms diffusion resistance Equivalent conjunction to this PNP triode base stage, high concentration p-type doping (P+) 22 and N trap
(N-Well) the emitter stage PN junction of 50 this PNP triode of composition, matrix (Psub) 70 constitutes this PNP tri- with N trap (N-Well) 50
The colelctor electrode PN junction of pole pipe, high concentration n-type doping (N+) 26, high concentration p-type doping (P+) 28 are placed in p-well (P-Well) 60
Portion, N trap (N-Well) 50, matrix (Psub) 70 and high concentration n-type doping (N+) 26 constitute equivalent N PN audion, N trap
(N-Well) 50 with matrix (Psub) 70 constitute this NPN triode colelctor electrode PN junction, matrix (Psub) 70 and high concentration N-type are mixed
Miscellaneous (N+) 26 constitutes the emitter stage PN junction of equivalent N PN audion, high concentration p-type doping (P+) 26, p-well (P-Well) 60, matrix
(Psub) 70 composition diffusion resistances connect to the base stage of this equivalent N PN audion, and high concentration n-type doping (N+) 24 is placed in N trap (N-
Well) 50 with p-well (P-Well) 60 boundary top, high concentration n-type doping (N+) 20, high concentration p-type doping (P+) 22, highly concentrated
Between degree n-type doping (N+) 24, high concentration n-type doping (N+) 26, high concentration p-type doping (P+) 28 with shallow trench isolation layer (STI,
Shallow Trench Isolation) 10 isolation, ESD implant layer (ESD_IMP) 40 is placed in high concentration n-type doping (N+) 24
The lower section of the part in p-well (P-Well) 60, it is preferred that for ensureing all there is ESD_IMP in the p-well below N+, preferably super
Go out high concentration n-type doping (N+) 24 right side boundary 0.5um；Connect high concentration n-type doping (N+) 20, high concentration P with metal
Type doping (P+) 22 constitutes the anode A of this new low trigger voltage silicon control rectifier, high concentration n-type doping (N+) 26, high concentration P
Type doping (P+) 28 is the negative electrode K of this new low trigger voltage silicon control rectifier of the present invention.
It can be seen that, the N side of forging on the basis of the thyristor (Fig. 1) of prior art, between N trap/p-well for the present invention
P-well region extra add heavily doped ESD_IMP together, the energy of this ESD_IMP will be controlled to ensure that it is located at the lower section of N knot,
The present invention can adjust the breakdown reverse voltage of this N+/P+ diode by adjusting the dosage of ESD_IMP.Preferable in the present invention
In embodiment, the energy range of ESD IMP：Can be write as 10Kev～100Kev, the dosage range of ESD IMP：1.0E11cm-2
～1.0E16cm-2.
Here it should be noted that, this ESD_IMP position can be only positioned in the p-well region of the N side of forging, and can not cover whole N
Knot, can determine optimal ESD_IMP dosage according to the performance of the trigger voltage of this thyristor and leakage current.
Fig. 4 is a kind of flow chart of steps of the manufacture method of new low trigger voltage silicon control rectifier of the present invention.As Fig. 4 institute
Show that a kind of manufacture method of new low trigger voltage silicon control rectifier of the present invention comprises the steps：
Step 401, provides semiconductor substrate (Psub) 70.
Step 402, generates a N trap (N-Well) 50 in the side of semiconductor substrate (Psub) 70, in matrix
(Psub) 70 opposite sides generate a p-well (P-Well) 60, and in present pre-ferred embodiments, N trap 50 is arranged at matrix
(Psub) 70 left side, p-well (P-Well) 60 is arranged on the right of matrix (Psub) 70.
Step 403, passes through doping in N trap 50 top and forms equivalent PNP triode structure, pass through doping in p-well 60 top
Form equivalent PNP triode structure.Specifically, high concentration n-type doping (N+) 20, high concentration p-type doping (P+) 22 are placed in N
Trap (N-Well) 50 top, high concentration p-type doping (P+) 22, N trap (N-Well) 50 and matrix (Psub) 70 constitute equivalent PNP
Audion, high concentration n-type doping (N+) 20 and N trap (N-Well) 50 form diffusion resistance Equivalent conjunction to this PNP tri- pole
Pipe base stage, high concentration p-type doping (P+) 22 constitutes the emitter stage PN junction of this PNP triode, matrix with N trap (N-Well) 50
(Psub) 70 constitute the colelctor electrode PN junction of this PNP triode with N trap (N-Well) 50, by high concentration n-type doping (N+) 26, highly concentrated
Degree p-type doping (P+) 28 is placed in p-well (P-Well) 60 top, and N trap (N-Well) 50, matrix (Psub) 70 are mixed with high concentration N-type
Miscellaneous (N+) 26 constitutes equivalent N PN audion, and N trap (N-Well) 50 constitutes the collection of this NPN triode with matrix (Psub) 70
Electrode PN junction, matrix (Psub) 70 and high concentration n-type doping (N+) 26 constitute the emitter stage PN junction of equivalent N PN audion, highly concentrated
Degree p-type doping (P+) 26, p-well (P-Well) 60, matrix (Psub) 70 constitute diffusion resistance and connect to this equivalent N PN audion
Base stage, between high concentration n-type doping (N+) 20, high concentration p-type doping (P+) 22 and high concentration n-type doping (N+) 26, highly concentrated
With shallow trench isolation layer (STI, Shallow Trench Isolation) 10 isolation between degree p-type doping (P+) 28
Step 404, one heavily doped N knot across N trap and p-well of insertion between N trap 50 and p-well 60.That is, will be highly concentrated
Degree n-type doping (N+) 24 is placed in N trap (N-Well) 50 and p-well (P-Wel) 60 boundary top, and high concentration p-type doping (P+)
With shallow between 22 and high concentration n-type doping (N+) 24, between high concentration n-type doping (N+) 24 and high concentration n-type doping (N+) 26
Channel isolation layer (STI, Shallow Trench Isolation) 10 is isolated.
Step 405, the p-well region in this N side of forging adds ESD implant layer (ESD_IMP) 40, this ESD implant layer (ESD_
IMP) 40 can be only positioned in the p-well region of the N side of forging, and whole N knot can not be covered, control the energy guarantee period position of this ESD IMP
In the lower section of N knot, the breakdown reverse voltage of this N+/P+ diode, Ke Yigen can be adjusted by adjusting the dosage of ESD_IMP
Determine optimal ESD IMP dosage according to the trigger voltage of this new thyristor and the performance of leakage current.
Step 406, connects high concentration n-type doping (N+) 20 using metal, that high concentration p-type doping (P+) 22 constitutes this is new
The anode A of low trigger voltage silicon control rectifier, high concentration n-type doping (N+) 26, high concentration p-type doping (P+) 28 are that this is new low
The negative electrode K of trigger voltage thyristor.
The new low trigger voltage silicon control rectifier of the present invention can be applied to the input/output terminal in esd protection circuit
Protection circuit in and power supply protection circuit over the ground in, to lift the overall ESD protection capability of chip, as shown in Figure 5.
In sum, a kind of new low trigger voltage silicon control rectifier of the present invention and preparation method thereof, it passes through existing
The N trap of thyristor and p-well between the N side of forging the extra heavily doped ESD_IMP adding p-type together of p-well region, make
Obtain this N knot and ESD_IMP below forms the N+/P+ diode of a vertical direction, thus reducing N trap further to p-well
Breakdown reverse voltage.
Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any
Skilled person all can be modified to above-described embodiment and changed without prejudice under the spirit and the scope of the present invention.Therefore,
The scope of the present invention, should be as listed by claims.
Claims (10)
1. a kind of new low trigger voltage silicon control rectifier is it is characterised in that this commutator includes：
Semiconductor substrate (70)；
It is created on N trap (50) and the opposite side p-well (60) of side in described semiconductor substrate (70)；
Pass through the equivalent PNP triode structure that formed of doping in described N trap (50) and formed by doping in described p-well (60)
Equivalent N PN audion；
It is inserted in heavily doped N knot (24) between described N trap and described p-well；
It is formed at the ESD implant layer (40) in the p-well region below described N knot (24).
2. as claimed in claim 1 a kind of new low trigger voltage silicon control rectifier it is characterised in that：High concentration n-type doping
(20), high concentration p-type doping (22) is placed in described N trap (50) top, high concentration p-type doping (P+) 22, N trap (N-Well) 50 with
And matrix (Psub) 70 constitutes equivalent PNP triode structure.
3. as claimed in claim 2 a kind of new low trigger voltage silicon control rectifier it is characterised in that：Described high concentration N-type
Doping (20) and described N trap (50) form diffusion resistance Equivalent conjunction to this PNP triode base stage, described high concentration p-type doping
(22) constitute the emitter stage PN junction of this PNP triode with described N trap (50), described matrix and described N trap (50) constitute this PNP tri-
The colelctor electrode PN junction of pole pipe.
4. as claimed in claim 3 a kind of new low trigger voltage silicon control rectifier it is characterised in that：High concentration N-type is mixed
Miscellaneous (26), high concentration p-type doping (28) are placed in described p-well (60) top, and described N trap (50), matrix and described high concentration N-type are mixed
Miscellaneous (26) constitute described equivalent N PN audion.
5. as claimed in claim 4 a kind of new low trigger voltage silicon control rectifier it is characterised in that：Described N trap (50) with
Described matrix constitutes the colelctor electrode PN junction of this NPN triode, and described matrix 70 and described high concentration n-type doping (26) constitute described
The emitter stage PN junction of equivalent N PN audion, described high concentration p-type doping (26), p-well (60), matrix constitute diffusion resistance and connect
Base stage to this equivalent N PN audion.
6. as claimed in claim 5 a kind of new low trigger voltage silicon control rectifier it is characterised in that：Described high concentration N-type
Between doping (20), high concentration p-type doping (22), described N knot (24), high concentration n-type doping (26), high concentration p-type doping (28)
With shallow trench isolation layer (10) isolation.
7. as claimed in claim 6 a kind of new low trigger voltage silicon control rectifier it is characterised in that：Described thyristor
By adjust described ESD implant layer (40) ESD_IMP dosage adjust this N knot and this ESD implant layer (40) formed hang down
Nogata to N+/P+ (ESD_IMP) diode breakdown reverse voltage.
8. a kind of manufacture method of new low trigger voltage silicon control rectifier, comprises the steps：
Step one, provides semiconductor substrate (70)；
Step 2, generates a N trap (50) in the side of semiconductor substrate (70), generates in described matrix (70) opposite side
One p-well (60)；
Step 3, passes through doping in described N trap (50) and forms equivalent PNP triode structure, pass through, in described p-well (60), shape of adulterating
Become equivalent N PN audion；
Step 4, one heavily doped N knot across N trap and p-well of insertion between described N trap (50) and described p-well (60)；
Step 5, adds ESD implant layer (40) in the p-well region of this N side of forging.
9. as claimed in claim 8 a kind of manufacture method of new low trigger voltage silicon control rectifier it is characterised in that：Yu Bu
In rapid five, adjust this N knot and this ESD implant layer (40) shape by adjusting the dosage of the ESD_IMP of described ESD implant layer (40)
The breakdown reverse voltage of N+/P+ (ESD_IMP) diode of vertical direction becoming.
10. as claimed in claim 9 a kind of manufacture method of new low trigger voltage silicon control rectifier it is characterised in that：Root
Determine optimal ESD_IMP dosage according to the trigger voltage of this thyristor and the performance of leakage current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610875402.5A CN106449635A (en) | 2016-09-30 | 2016-09-30 | Novel low-trigger-voltage silicon-controlled rectifier and manufacturing method therefor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610875402.5A CN106449635A (en) | 2016-09-30 | 2016-09-30 | Novel low-trigger-voltage silicon-controlled rectifier and manufacturing method therefor |
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|---|---|
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107516657A (en) * | 2017-07-31 | 2017-12-26 | 上海华力微电子有限公司 | A kind of new E SD protection structures and its implementation |
| CN107546223A (en) * | 2017-08-22 | 2018-01-05 | 湘潭大学 | A kind of small island diode triggered thyristor electrostatic protection device of waffle-type |
| CN109037203A (en) * | 2018-07-13 | 2018-12-18 | 上海华力微电子有限公司 | Thyristor type esd protection structure and implementation method |
| CN109065535A (en) * | 2018-08-20 | 2018-12-21 | 上海华力微电子有限公司 | A kind of silicon-controlled rectifier structure and its manufacturing method |
| CN109065534A (en) * | 2018-08-20 | 2018-12-21 | 上海华力微电子有限公司 | A kind of silicon-controlled rectifier structure and its manufacturing method |
| CN109148441A (en) * | 2018-08-31 | 2019-01-04 | 上海华力微电子有限公司 | Suitable for high-tension circuit antistatic protection without echo effect thyristor |
| CN109273532A (en) * | 2018-09-12 | 2019-01-25 | 上海华力微电子有限公司 | Applied to high-tension circuit antistatic protection without echo effect thyristor |
| CN109841609A (en) * | 2017-11-24 | 2019-06-04 | 力智电子股份有限公司 | Transient Voltage Suppressor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107516657A (en) * | 2017-07-31 | 2017-12-26 | 上海华力微电子有限公司 | A kind of new E SD protection structures and its implementation |
| CN107516657B (en) * | 2017-07-31 | 2019-10-25 | 上海华力微电子有限公司 | A kind of new E SD protection structure and its implementation |
| CN107546223A (en) * | 2017-08-22 | 2018-01-05 | 湘潭大学 | A kind of small island diode triggered thyristor electrostatic protection device of waffle-type |
| CN109841609A (en) * | 2017-11-24 | 2019-06-04 | 力智电子股份有限公司 | Transient Voltage Suppressor |
| CN109037203A (en) * | 2018-07-13 | 2018-12-18 | 上海华力微电子有限公司 | Thyristor type esd protection structure and implementation method |
| CN109065535A (en) * | 2018-08-20 | 2018-12-21 | 上海华力微电子有限公司 | A kind of silicon-controlled rectifier structure and its manufacturing method |
| CN109065534A (en) * | 2018-08-20 | 2018-12-21 | 上海华力微电子有限公司 | A kind of silicon-controlled rectifier structure and its manufacturing method |
| CN109148441A (en) * | 2018-08-31 | 2019-01-04 | 上海华力微电子有限公司 | Suitable for high-tension circuit antistatic protection without echo effect thyristor |
| CN109273532A (en) * | 2018-09-12 | 2019-01-25 | 上海华力微电子有限公司 | Applied to high-tension circuit antistatic protection without echo effect thyristor |
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