CN211858654U - High-protection-level unidirectional silicon controlled rectifier electrostatic protection device - Google Patents
High-protection-level unidirectional silicon controlled rectifier electrostatic protection device Download PDFInfo
- Publication number
- CN211858654U CN211858654U CN202020990483.5U CN202020990483U CN211858654U CN 211858654 U CN211858654 U CN 211858654U CN 202020990483 U CN202020990483 U CN 202020990483U CN 211858654 U CN211858654 U CN 211858654U
- Authority
- CN
- China
- Prior art keywords
- injection region
- deep well
- type deep
- region
- well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Thyristors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model discloses a high protection grade unidirectional silicon controlled rectifier electrostatic protection device, which comprises a P-type substrate; a first N-type deep well and a second N-type deep well are arranged in the substrate; a P well is arranged on the right side of the second N-type deep well; a first P + injection region and a first N + injection region are arranged in the first N-type deep well; a second P + injection region and a second N + injection region are arranged in the second N-type deep well; a fourth N + injection region in cross connection is arranged between the first N-type deep well and the second N-type deep well; a third P + injection region and a third N + injection region are arranged in the P well; the first P + injection region, the first N + injection region, the second P + injection region and the second N + injection region are connected together and used as an anode of the device, and the third P + injection region and the third N + injection region are connected together and used as a cathode of the device.
Description
Technical Field
The utility model relates to an electrostatic protection field, in particular to one-way silicon controlled rectifier electrostatic protection device of high protection level.
Background
With the progress of semiconductor manufacturing process, the failure of integrated circuit chips and electronic products caused by ESD is becoming more serious, and ESD protection of electronic products and integrated circuit chips becomes one of the major problems faced by product engineers.
Compared with other ESD devices, the traditional silicon controlled device has a double-conductance modulation mechanism, is high in unit-area discharge efficiency, small in unit parasitic capacitance and best in robustness, but in order to achieve a higher protection level, the device is often required to be made into a multi-fork finger shape, so that the problem that the maintaining voltage is reduced along with the increase of the fork index can be caused, a large amount of area is consumed, and important consideration needs to be given during design.
When ESD pulse is applied to an SCR anode, a second N-type deep well and a P well form a reverse bias PN node, when the pulse voltage is higher than the avalanche breakdown voltage of the PN node, a large amount of avalanche current can be generated in the device, and the current circulation path of the current flows to the other end, namely a cathode, through a P well parasitic resistor; when the voltage at two ends of the parasitic well resistor is higher than the forward conduction voltage of the cb junction (composed of the P well and the third N + injection region) of the parasitic NPN transistor, the transistor is turned on, after the transistor is turned on, the base current is provided for the PNP1 transistor, after the parasitic PNP1 transistor is also turned on, the base current is also provided for the parasitic NPN transistor, so as to form a positive feedback loop, and as the ESD current continues to increase, after the PNP1 provides sufficient base current for the PNP2, the PNP2 is also turned on in succession, and forms an SCR path with the NPN, so that static electricity can be discharged.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides a simple structure's one-way silicon controlled rectifier electrostatic protection device of high protection level.
The embodiment of the utility model provides a high protection grade unidirectional silicon controlled rectifier electrostatic protection device, which comprises a P-type substrate;
a first N-type deep well and a second N-type deep well are arranged in the P-type substrate; the first N-type deep well is positioned on the left side of the P-type substrate, and the second N-type deep well is positioned on the right side of the P-type substrate;
a P well is arranged on the right side of the second N-type deep well;
a first P + injection region and a first N + injection region are arranged in the first N-type deep well, wherein the first P + injection region is positioned on the right side of the first N-type deep well, and the first N + injection region is positioned on the left side of the first N-type deep well;
a second P + injection region and a second N + injection region are arranged in the second N-type deep well, wherein the second P + injection region is positioned on the right side of the second N-type deep well, and the second N + injection region is positioned on the left side of the second N-type deep well;
a bridged fourth N + injection region is arranged between the first N-type deep well and the second N-type deep well;
a third P + injection region and a third N + injection region are arranged in the P well, wherein the third P + injection region is positioned on the right side of the P well, and the third N + injection region is positioned on the left side of the P well;
the first P + injection region, the first N + injection region, the second P + injection region and the second N + injection region are connected together and serve as an anode of the device, and the third P + injection region and the third N + injection region are connected together and serve as a cathode of the device.
A first field oxide isolation region is arranged between the left side of the first N + injection region and the left side edge of the P-type substrate; the right side of the first N + injection region is connected with the left side of the first P + injection region, and a second field oxide isolation region is arranged between the right side of the first P + injection region and the fourth N + injection region bridged between the first N-type deep well and the second N-type deep well; a third field oxide isolation region is arranged between the fourth N + injection region and the right side of the second N + injection region, wherein the fourth N + injection region is bridged between the first N-type deep well and the second N-type deep well; a fourth field oxide isolation region is arranged between the right side of the second P + injection region and the third N + injection region, and the left side of the second P + injection region is connected with the right side of the second N + injection region; and a fifth field oxide isolation region is arranged between the right side of the third P + injection region on the right side and the edge of the right side of the P-type substrate.
The left part of the first field oxide isolation region is positioned on the surface of the P-type substrate, and the right part of the first field oxide isolation region is positioned on the surface of the first N-type deep well; the left part of the fifth field oxygen isolation region is positioned on the surface of the P well, and the right part of the fifth field oxygen isolation region is positioned on the surface of the P-type substrate; the second field oxide isolation region is positioned on the surface of the first N-type deep well, and the third field oxide isolation region is positioned on the surface of the second N-type deep well; the left part of the fourth field oxygen isolation region is positioned on the surface of the second N-type deep well, and the right part of the fourth field oxygen isolation region is positioned on the surface of the P well.
When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected with a low potential, the second P + injection region in the second N-type deep well, the second N-type deep well and the P well form a parasitic PNP1 triode structure; the second N-type deep well, the P well and the third N + injection region form a parasitic NPN triode; the first P + implantation region in the first N-type deep well, and the P-type substrate form a parasitic PNP2 triode structure.
Wherein a distance between the P well and the third N + implantation region is S1.
The beneficial effects of the utility model reside in that:
1. the utility model discloses can increase and decrease the quantity that N type deep well and N + injection zone, P + injection zone were gone into according to the difference of protection level, if protection level is high promptly, then increase the quantity that N type deep well and N + injection zone, P + injection zone improved device current evenly distributed's the condition, improved the robustness of device, protection level is low, then reduces the quantity that N type deep well and N + injection zone, P + injection zone, reduces the territory area.
2. The utility model discloses a distance S1 between P trap and the third N + injection region is adjustable, when S1 increases for the base region width of NPN type triode also increases thereupon, has reduced the magnification of vertical NPN type triode, and the holding voltage increases thereupon.
3. The utility model discloses the holding voltage of device can not reduce along with the increase of fork index, and the size of holding voltage is decided by the distance length on interior survey SCR route that the guide leads to.
Drawings
Fig. 1 is a cross-sectional view of a conventional unidirectional SCR electrostatic discharge protection device.
Fig. 2 is an equivalent circuit diagram of a conventional unidirectional SCR esd protection device.
Fig. 3 is a cross-sectional view of a high protection level unidirectional silicon controlled rectifier electrostatic discharge protection device according to an embodiment of the present invention.
Fig. 4 is an equivalent circuit diagram of the unidirectional scr electrostatic discharge protection device with high protection level according to an embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and examples.
As shown in fig. 3, a high protection level unidirectional silicon controlled rectifier electrostatic discharge protection device includes a P-type substrate 101; a first N-type deep well 201 and a second N-type deep well 202 are arranged in the substrate; a P well 301 is arranged on the right side of the second N-type deep well 202; a first P + injection region 402 and a first N + injection region 401 are arranged in the first N-type deep well 201; a second P + implantation region 405 and a second N + implantation region 404 are arranged in the second N-type deep well 202; a fourth N + injection region 403 in cross connection is arranged between the first N-type deep well 201 and the second N-type deep well 202; a third P + injection region 407 and a third N + injection region 406 are arranged in the P-well 301; the first P + implant region 402, the first N + implant region 401, the second P + implant region 405, and the second N + implant region 404 are coupled together and serve as the anode of the device, and the third P + implant region 407 and the third N + implant region 406 are coupled together and serve as the cathode of the device.
A first field oxide isolation region 501 is arranged between the left side of the first N + injection region 401 and the left side edge of the P-type substrate 101; the right side of the first N + injection region 401 is connected with the left side of the first P + injection region 402, and a second field oxide isolation region 502 is arranged between the right side of the first P + injection region 402 and a fourth N + injection region 403 bridged between the first N-type deep well 201 and the second N-type deep well 202; a third field oxide isolation region 503 is arranged between the fourth N + injection region 403 bridged between the first N-type deep well 201 and the second N + injection region 202 and the right side of the second N + injection region 404; a fourth field oxide isolation region 504 is arranged between the right side of the second P + implantation region 405 and the third N + implantation region 406, and the left side of the second P + implantation region 405 is connected to the right side of the second N + implantation region 404; a fifth field oxide isolation region 505 is disposed between the right side of the rightmost third P + implant region 407 and the right edge of the P-type substrate 101.
The left part of the first field oxide isolation region 501 is positioned on the surface of the P-type substrate 101, and the right part of the first field oxide isolation region 501 is positioned on the surface of the first N-type deep well 201; the left part of the fifth field oxide isolation region 505 is positioned on the surface of the P well 301, and the right part of the fifth field oxide isolation region 505 is positioned on the surface of the P-type substrate 101; the second field oxide isolation region 502 is located on the surface of the first N-type deep well 201, and the third field oxide isolation region 503 is located on the surface of the second N-type deep well 202; the left part of the fourth field oxide isolation region 504 is located on the surface of the second N-type deep well 202, and the right part of the fourth field oxide isolation region 504 is located on the surface of the P-well 301.
As shown in fig. 4, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the second P + implantation region 405 in the second N-type deep well 202, and the P well 301 form a parasitic PNP1 triode structure; the second N-type deep well 202, the P well 301 and the third N + injection region 406 form a parasitic NPN triode; meanwhile, the first P + implantation region 402 in the first N-type deep well 301, the first N-type deep well 201, and the P-type substrate 101 can also form a parasitic PNP2 triode structure. The parasitic PNP2 transistor in the first N-type deep well 201 and the parasitic PNP1 transistor in the second N-type deep well 202 may form a bidirectional SCR structure with the NPN transistor in the P-well 301.
When the ESD high-voltage pulse reaches the anode of the device, the first P + injection region, the first N + injection region, the second P + injection region and the second N + injection region are high potential, and the third P + injection region and the third N + injection region are low potential cathodes. The second N-type deep well 202 and the P-well 301 are reversely biased, when the pulse voltage is higher than the avalanche breakdown voltage of the junction, a large amount of avalanche current is generated in the device, so that two parasitic resistors Rn well 1、RP-wellThe voltages at two ends are increased, one parasitic triode is firstly conducted, and the base current is further provided for the other parasitic triode. Because the innermost SCR path is short and has small on-resistance, the SCR formed by the innermost T1 and the T2 is firstly conducted, the parasitic PNP1 triode at the inner side is conducted and then provides trigger current for the T3 triode at the outer side, and then the T2 and the T3 also form an SCR structure to continuously discharge static current, so that the whole device is completely started.
Compared with the traditional unidirectional silicon controlled rectifier electrostatic protection device, the device is additionally provided with a parasitic triode at the anode, and the device is started firstly because the internal SCR path is shorter, and the maintaining voltage of the device is determined by the internal SCR path. As the current continues to increase, the internal parasitic transistor PNP1 provides base current to the external parasitic transistor PNP2, which also turns on the external SCR. Meanwhile, as the leakage paths are arranged, the conduction work is realized, the current distribution is more uniform, and the static electricity can be better leaked, so that the protection grade of the device is higher.
The device can increase and decrease the number of the N-type deep well, the N + injection region and the P + injection region thereof according to the requirements of an ESD design window under different application scenes according to different protection grades, namely if the protection grade is high, the number of the N-type deep well, the N + injection region and the P + injection region thereof is increased, the condition of uniform distribution of device current is improved, the robustness of the device is improved, the protection grade is low, the number of the N-type deep well, the N + injection region and the P + injection region thereof is reduced, and the layout area is reduced.
A manufacturing method of a high-protection-level unidirectional silicon controlled rectifier electrostatic protection device comprises the following steps:
the method comprises the following steps: growing a silicon dioxide film on a P-type substrate 101, and then depositing a silicon nitride film; spin-coating a photoresist layer on a wafer, and adding a mask plate to expose and develop the wafer to form an isolation shallow slot; etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed;
step two: a first field oxide isolation region 501, a second field oxide isolation region 502, a third field oxide isolation region 503, a fourth field oxide isolation region 504 and a fifth field oxide isolation region 505 are sequentially formed in the substrate from left to right;
step three: forming a first N-type deep well 201 and a second N-type deep well 202 in a substrate;
step four: annealing the first N-type deep well 201 and the second N-type deep well 202 to eliminate impurity diffusion;
step five: forming a first N + implantation region 401 and a first P + implantation region 402 in the first N-type deep well 201; forming a second N + implantation region 404 and a second P + implantation region 405 in the second N-type deep 202 well; forming a third N + implantation region 406 and a third P + implantation region 407 in the P-well 301; forming a fourth N + implantation region 403 at the cross-over between the right side of the first N-type deep well 201 and the left side of the second N-type deep well 202;
step six: annealing the first N + injection region 401, the first P + injection region 402, the second N + injection region 404, the second P + injection region 405, the third N + injection region 406, the third P + injection region 407 and the fourth N + injection region 403 to eliminate the migration of impurities in the injection regions;
step seven: the first P + implant region 402, the first N + implant region 401, the second P + implant region 405, and the second N + implant region 404 are coupled together and serve as the anode of the device, and the third P + implant region 407 and the third N + implant region 406 are coupled together and serve as the cathode of the device.
The utility model discloses high protection level one-way silicon controlled rectifier electrostatic protection device's manufacturing method process is simple, convenient operation. The manufactured unidirectional silicon controlled electrostatic protection device structure can improve the uniform current distribution condition of the device and improve the robustness of the device by increasing the number of the N-type deep well, the N + injection region and the P + injection region thereof; if the required protection level is lower, the number of the N-type deep well and the N + injection region and the P + injection region thereof can be reduced, and the purpose of reducing the layout area is achieved; the sustain voltage can be increased by increasing the distance S1. The device can be applied to an ESD protection design, and effectively protects an internal chip from the risk of latch-up. The utility model discloses the example device adopts 0.5 mu m's CMOS technology.
Claims (5)
1. A high protection level unidirectional silicon controlled rectifier electrostatic protection device is characterized by comprising a P-type substrate;
a first N-type deep well and a second N-type deep well are arranged in the P-type substrate; the first N-type deep well is positioned on the left side of the P-type substrate, and the second N-type deep well is positioned on the right side of the P-type substrate;
a P well is arranged on the right side of the second N-type deep well;
a first P + injection region and a first N + injection region are arranged in the first N-type deep well, wherein the first P + injection region is positioned on the right side of the first N-type deep well, and the first N + injection region is positioned on the left side of the first N-type deep well;
a second P + injection region and a second N + injection region are arranged in the second N-type deep well, wherein the second P + injection region is positioned on the right side of the second N-type deep well, and the second N + injection region is positioned on the left side of the second N-type deep well;
a bridged fourth N + injection region is arranged between the first N-type deep well and the second N-type deep well;
a third P + injection region and a third N + injection region are arranged in the P well, wherein the third P + injection region is positioned on the right side of the P well, and the third N + injection region is positioned on the left side of the P well;
the first P + injection region, the first N + injection region, the second P + injection region and the second N + injection region are connected together and serve as an anode of the device, and the third P + injection region and the third N + injection region are connected together and serve as a cathode of the device.
2. The ESD device with high protection level SCR according to claim 1, wherein a first field oxide isolation region is disposed between the left side of the first N + injection region and the left side edge of the P-type substrate; the right side of the first N + injection region is connected with the left side of the first P + injection region, and a second field oxide isolation region is arranged between the right side of the first P + injection region and the fourth N + injection region bridged between the first N-type deep well and the second N-type deep well; a third field oxide isolation region is arranged between the fourth N + injection region and the right side of the second N + injection region, wherein the fourth N + injection region is bridged between the first N-type deep well and the second N-type deep well; a fourth field oxide isolation region is arranged between the right side of the second P + injection region and the third N + injection region, and the left side of the second P + injection region is connected with the right side of the second N + injection region; and a fifth field oxide isolation region is arranged between the right side of the third P + injection region on the right side and the edge of the right side of the P-type substrate.
3. The high-protection-level unidirectional silicon controlled rectifier electrostatic discharge protection device according to claim 2, wherein the left part of the first field oxide isolation region is located on the surface of the P-type substrate, and the right part of the first field oxide isolation region is located on the surface of the first N-type deep well; the left part of the fifth field oxygen isolation region is positioned on the surface of the P well, and the right part of the fifth field oxygen isolation region is positioned on the surface of the P-type substrate; the second field oxide isolation region is positioned on the surface of the first N-type deep well, and the third field oxide isolation region is positioned on the surface of the second N-type deep well; the left part of the fourth field oxygen isolation region is positioned on the surface of the second N-type deep well, and the right part of the fourth field oxygen isolation region is positioned on the surface of the P well.
4. The ESD protection device with high protection rating as claimed in claim 2, wherein when the high voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to the low potential, the second P + injection region, the second N-type deep well and the P-well in the second N-type deep well form a parasitic PNP1 triode structure; the second N-type deep well, the P well and the third N + injection region form a parasitic NPN triode; the first P + implantation region in the first N-type deep well, and the P-type substrate form a parasitic PNP2 triode structure.
5. The ESD device according to claim 4, wherein the distance between the P-well and the third N + implant region is S1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020990483.5U CN211858654U (en) | 2020-06-02 | 2020-06-02 | High-protection-level unidirectional silicon controlled rectifier electrostatic protection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020990483.5U CN211858654U (en) | 2020-06-02 | 2020-06-02 | High-protection-level unidirectional silicon controlled rectifier electrostatic protection device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211858654U true CN211858654U (en) | 2020-11-03 |
Family
ID=73236810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020990483.5U Active CN211858654U (en) | 2020-06-02 | 2020-06-02 | High-protection-level unidirectional silicon controlled rectifier electrostatic protection device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211858654U (en) |
-
2020
- 2020-06-02 CN CN202020990483.5U patent/CN211858654U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8692289B2 (en) | Fast turn on silicon controlled rectifiers for ESD protection | |
| US10373944B2 (en) | ESD protection circuit with integral deep trench trigger diodes | |
| CN108336085B (en) | Grid embedded island type silicon controlled electrostatic protection device | |
| US8476672B2 (en) | Electrostatic discharge protection device and method for fabricating the same | |
| US8598625B2 (en) | ESD protection device with tunable design windows | |
| CN214848632U (en) | Bidirectional thyristor electrostatic protection device with low trigger and high holding voltage | |
| CN110690270A (en) | PMOS device with embedded silicon controlled rectifier and implementation method thereof | |
| CN111799258B (en) | Interdigital asymmetric bidirectional silicon controlled electrostatic discharge device and manufacturing method thereof | |
| CN110289257B (en) | Bidirectional enhanced gate-controlled silicon controlled electrostatic protection device and manufacturing method thereof | |
| CN113764403A (en) | Silicon controlled electrostatic protection device capable of being quickly started through resistance-capacitance coupling and manufacturing method thereof | |
| CN114783997B (en) | Silicon controlled rectifier electrostatic discharge protection structure | |
| CN115513201B (en) | High-maintenance low-resistance uniform-conduction bidirectional silicon controlled electrostatic protection device and manufacturing method thereof | |
| CN211858654U (en) | High-protection-level unidirectional silicon controlled rectifier electrostatic protection device | |
| CN215815877U (en) | High-maintenance high-failure bidirectional thyristor electrostatic protection device | |
| CN111710674A (en) | Ultra-low voltage trigger device and manufacturing method thereof | |
| CN214848631U (en) | Low-voltage grid unidirectional silicon controlled electrostatic protection device | |
| US11894362B2 (en) | PNP controlled ESD protection device with high holding voltage and snapback | |
| CN113764402A (en) | High-protection-level unidirectional silicon controlled rectifier electrostatic protection device and manufacturing method thereof | |
| CN212517201U (en) | Silicon controlled electrostatic protection device capable of being quickly turned on by resistance-capacitance coupling | |
| CN110518010B (en) | PMOS device with embedded silicon controlled rectifier and implementation method thereof | |
| CN115528019A (en) | ESD protection device, protection circuit and preparation method | |
| CN112447703A (en) | Electrostatic discharge protection element | |
| CN115831960A (en) | High-robustness asymmetric bidirectional thyristor electrostatic protection device and manufacturing method thereof | |
| CN116564961B (en) | LVTSCR device and chip electrostatic discharge circuit | |
| CN118335742A (en) | Strong-robustness vertical silicon controlled electrostatic protection device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |