CN115831960A - High-robustness asymmetric bidirectional thyristor electrostatic protection device and manufacturing method thereof - Google Patents

Abstract

The invention provides a strong robustness asymmetric bidirectional controllable silicon electrostatic protection device and a manufacturing method thereof, wherein the device comprises a P-type substrate, an N-type deep well, an N-type well, a P-type well and the like; the first N well and the second P + injection region, and the second N well and the fifth P + injection region reduce the trigger voltage of the device through highly doped P + injection and N well avalanche breakdown; two electrodes of the first P + injection region and the third N + injection region are connected together to be used as a cathode of the device; the four electrodes of the first N + injection region, the third P + injection region, the second N + injection region and the fourth P + injection region are connected together to be used as an anode of the device; under the condition of reducing the trigger voltage of the device, the device realizes the bidirectional protection of an I/O port by utilizing different Electrostatic Discharge (ESD) Discharge paths, thereby effectively protecting the I/O signal port of a chip for transmitting positive and negative levels; the device has the characteristics of low trigger voltage and high failure current, and can be applied to bidirectional ESD protection of an I/O port.

Description

High-robustness asymmetric bidirectional thyristor electrostatic protection device and manufacturing method thereof

Technical Field

The invention relates to the field of electrostatic protection, in particular to a strong-robustness asymmetric bidirectional thyristor electrostatic protection device and a manufacturing method thereof.

Background

With the continuous development of integrated circuit manufacturing processes, the device size is continuously reduced. The failure of integrated circuit chips and electronic products due to Electrostatic Discharge (ESD) is becoming more serious. According to relevant statistics, the damage losses due to ESD in the microelectronics field are up to about $ 100 million per year. This data illustrates the necessity for ESD protection measures for integrated circuit chips as well as for electronic products.

Compared with other ESD devices, the traditional Silicon Controlled Rectifier (SCR) device has the advantages of strong current discharge capacity per unit area, small parasitic capacitance and the like. However, the traditional silicon controlled rectifier device has the defects of over-high trigger voltage, over-low maintaining voltage after the device is triggered and the like. The over-high trigger voltage can cause the protection device not to protect the core circuit in time, and the over-low maintenance voltage can cause the latch-up effect of the device, which causes the ESD protection device not to play a normal role, and can not ensure the integrity of the I/O port transmission signal.

The asymmetric bidirectional controllable silicon device is improved on the basis of the traditional controllable silicon, has asymmetric structural layout, has the same working principle as the traditional unidirectional controllable silicon, and can discharge ESD current from two directions. The cross-sectional view of the conventional triac electrostatic protection device is shown in fig. 1, and the equivalent circuit diagram thereof is shown in fig. 2. When the ESD pulse is applied to the bidirectional SCR anode, the N-type deep well and the second P well form a reverse bias PN junction. When the ESD pulse voltage is higher than the avalanche breakdown voltage of the reverse biased PN junction, the device generates avalanche breakdown current, and the avalanche breakdown current flows through the parasitic resistance Rp2 of the second P well. And when the voltage at the two ends of the Rp2 is higher than the forward conduction voltage of the longitudinal NPN triode, the longitudinal NPN triode is started. After the longitudinal NPN triode is started, base current is provided for the transverse PNP triode to enable the transverse PNP triode to be started, and the two triodes provide base current to each other to promote each other to form a positive feedback link. And when the two triodes are completely started, an SCR (selective catalytic reduction) passage is formed to discharge ESD current. The bidirectional SCR is of a symmetrical structure, and when an ESD pulse is applied to the cathode, the N-type deep well and the first P well form reverse-biased PN junction avalanche breakdown, so that the PNP triode and the NPN triode are sequentially conducted to discharge static electricity. However, the conventional SCR has the disadvantages of high trigger voltage and low holding voltage, the high trigger voltage can cause the device not to meet the requirement of a design window, the low holding voltage is low, and the latch-up effect is easy to occur, so the trigger voltage needs to be reduced, the device is ensured to start a protection core circuit in time when the ESD current comes, and the holding voltage of the bidirectional thyristor is improved to avoid the latch-up effect.

Disclosure of Invention

In order to solve the technical problem, the invention provides a strong-robustness asymmetric bidirectional thyristor electrostatic protection device and a manufacturing method thereof, and the device is applied to an ESD protection design of an I/O port with 0-5.5V working voltage.

The invention provides a strong-robustness asymmetric bidirectional thyristor electrostatic protection device with a simple structure and a manufacturing method thereof.

In order to achieve the above purpose, the technical solution of the embodiment of the present invention is realized as follows:

the invention provides a strong robustness asymmetric bidirectional controllable silicon electrostatic protection device, which comprises a P-type substrate; an N-type deep well is arranged in the P-type substrate; a first N well, a first P well, a second N well and a second P well are arranged above the N-type deep well from left to right; a first P + injection region is arranged in the first N well; a first N + injection region and a third P + injection region are arranged in the first P well; a second N + injection region and a fourth P + injection region are arranged in the second N well; a third N + injection region is arranged in the second P well; a second P + injection region is arranged between the first N well and the first P well; a fifth P + injection region is arranged between the second N well and the second P well; the two electrodes of the first P + injection region and the third N + injection region are connected together to serve as a cathode of the device, and the four electrodes of the first N + injection region, the third P + injection region, the second N + injection region and the fourth P + injection region are connected together to serve as an anode of the device.

Preferably, a first field oxide isolation region is arranged between the left side of the first P + implantation region and the left side edge of the P-type substrate; a second field oxide isolation region is arranged on the right side of the first P + injection region and on the left side of the second P + injection region; a third field oxide isolation region is arranged on the right side of the second P + injection region and the left side of the first N + injection region; a fourth field oxide isolation region is arranged on the right side of the first N + injection region and the left side of the third P + injection region; a fifth field oxide isolation region is arranged on the right side of the third P + injection region and the left side of the second N + injection region; a sixth field oxide isolation region is arranged on the right side of the second N + injection region and the left side of the fourth P + injection region; a seventh field oxide isolation region is arranged on the right side of the fourth P + injection region and the left side of the fifth P + injection region; an eighth field oxide isolation region is arranged on the right side of the fifth P + injection region and the left side of the third N + injection region; and a ninth field oxide isolation region is arranged between the right side of the third N + injection region and the right side edge of the P-type substrate.

Preferably, the first field oxide isolation region and the second field oxide isolation region are positioned on the surface of the first N well; the third field oxide isolation region and the fourth field oxide isolation region are positioned on the surface of the first P well; the left side of the fifth field oxide isolation region is positioned on the surface of the first P well, and the right side of the fifth field oxide isolation region is positioned on the surface of the second N well; the sixth field oxide isolation region and the seventh field oxide isolation region are positioned on the surface of the second N well; the eighth field oxide isolation region and the ninth field oxide isolation region are located on the surface of the second P well.

Preferably, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the fourth P + injection region, the second N well, and the second P well form a PNP type triode, the second N well, the second P well, and the third N + injection region form an NPN type triode, and a forward SCR path is formed when the parasitic PNP and parasitic NPN are turned on. When the high-voltage ESD pulse reaches the cathode of the device and the anode of the device is connected with a low potential, the first P + injection region, the first N well and the first P trap form a PNP type triode, the first N well, the first P well and the first N + injection region form an NPN type triode, and a reverse SCR path is formed after the parasitic PNP and parasitic NPN are started.

Preferably, when the high-voltage ESD pulse reaches the anode of the device, the cathode of the device is connected to a low potential, the ESD current flows into the second N well, the second P well, and the third N + injection region along the fourth P + injection region, when the ESD current increases to a certain value, an avalanche breakdown occurs at a reverse PN junction formed by the fifth P + injection region and the second N well, an avalanche breakdown current is generated, and a voltage drop is formed on an equivalent resistance of the second N well, when the voltage drop on the equivalent resistance reaches 0.7V, the longitudinal PNP triode is turned on and provides a base current for the lateral NPN triode to further promote the conduction thereof, so as to form a positive feedback effect, and at this time, the forward SCR path is successfully turned on. When the high-voltage ESD pulse reaches the cathode of the device, the anode of the device is connected with a low potential, ESD current flows into the first N well, the first P well and the first N + injection region along the first P + injection region, when the ESD current is increased to a certain value, avalanche breakdown occurs in a reverse PN junction formed by the second P + injection region and the first N well, avalanche breakdown current is generated, voltage drop is formed on the equivalent resistance of the second P well, when the voltage drop on the equivalent resistance reaches 0.7V, the transverse NPN type triode is conducted, base current is provided for the longitudinal PNP triode, conduction of the longitudinal PNP triode is further promoted, a positive feedback effect is formed, and at the moment, the reverse SCR path is successfully started.

The invention provides a manufacturing method of a strong robustness asymmetric bidirectional thyristor electrostatic protection device, which comprises the following steps:

the method comprises the following steps: forming an N-type deep well in a P-type substrate;

step two: generating a first N well, a first P well, a second N well and a second P well above the N-type deep well;

step three: sequentially generating a first field oxide isolation region, a second field oxide isolation region, a third field oxide isolation region, a fourth field oxide isolation region, a fifth field oxide isolation region, a sixth field oxide isolation region, a seventh field oxide isolation region, an eighth field oxide isolation region and a ninth field oxide isolation region from left to right in the P-type substrate;

step four: sequentially forming a first P + injection region in the first N well from left to right, sequentially forming a first N + injection region and a third P + injection region in the first P well from left to right, simultaneously forming a second P + injection region between the first N well and the contact surface of the first P well, sequentially forming a second N + injection region and a fourth P + injection region in the second N well from left to right, sequentially forming a third N + injection region in the second P well from left to right, and simultaneously forming a fifth P + injection region between the second N well and the contact surface of the second P well; the left side of the first field oxide isolation region is in contact with the edge of the left side of the P-type substrate, the right side of the first field oxide isolation region is in contact with the left side of the first P + injection region, the right side of the first P + injection region is in contact with the left side of the second field oxide isolation region, the right side of the second field oxide isolation region is in contact with the left side of the second P + injection region, and the right side of the second P + injection region is in contact with the left side of the third field oxide isolation region; the third field oxide isolation region right side is in contact with the first N + implant region left side, the first N + implant region right side is in contact with the fourth field oxide isolation region left side, the fourth field oxide isolation region right side is in contact with the third P + implant region left side, the third P + implant region right side is in contact with the fifth field oxide isolation region left side, the fifth field oxide isolation region right side is in contact with the second N + implant region left side, the second N + implant region right side is in contact with the sixth field oxide isolation region left side, the sixth field oxide isolation region right side is in contact with the fourth P + implant region left side, the fourth P + implant region right side is in contact with the seventh field oxide isolation region left side, the seventh field oxide isolation region right side is in contact with the fifth P + implant region left side, the fifth P + implant region right side is in contact with the eighth field oxide isolation region left side, the eighth field oxide isolation region right side is in contact with the third N + implant region left side, the third N + implant region right side is in contact with the third field oxide isolation region left side, and the ninth field oxide isolation region right side is in contact with the ninth field oxide isolation region edge P substrate right side;

step five: annealing the first P + injection region, the second P + injection region, the first N + injection region, the third P + injection region, the second N + injection region, the fourth P + injection region, the fifth P + injection region and the third N + injection region to eliminate the migration of impurities in the injection regions;

step six: and connecting the first N + injection region, the third P + injection region, the second N + injection region and the fourth P + injection region together to serve as an anode of the device, and connecting the first P + injection region and the third N + injection region together to serve as a cathode of the device.

Preferably, the method further comprises the following steps:

growing a silicon dioxide film on the P-type substrate, and then depositing a silicon nitride film; spin-coating a photoresist layer on a wafer, and adding a mask plate to expose and develop the wafer to form an isolation shallow slot; and etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed.

The invention provides a strong robustness asymmetric bidirectional controllable silicon electrostatic protection device and a manufacturing method thereof, and the device has the beneficial effects that:

1. the invention can reduce the trigger voltage and improve the holding voltage by changing the device process level under the condition of not increasing the device layout area. When ESD current is applied to the cathode, the first N well is connected with the second P + injection region, an additional conductive path can be formed, and the conductive path passes through the first P + injection region, the first N well, the second P + injection region, the first P well, the first N + injection region, the first P + injection region of the main path, the first N well, the first P well and the first N + injection region to be shunted so as to improve reverse maintaining voltage. The reverse PN junction formed by the first N well and the second P + injection region has smaller breakdown voltage, and the structural design can effectively reduce the trigger voltage of a reverse device. When ESD current is applied to the anode, the second N well is connected with the fifth P + injection region, an additional conducting path can be formed, and the conducting path passes through the fourth P + injection region, the second N well, the fifth P + injection region, the second P well, the third N + injection region, the main path fourth P + injection region, the second N well, the second P well and the third N + injection region to be shunted so as to improve forward maintaining voltage. The reverse PN junction formed by the second N well and the fifth P + injection region has smaller breakdown voltage, and the structural design can effectively reduce the forward trigger voltage of the device.

2. The first P trap and the second P trap are adjustable in size, so that the distance between the cathode and the anode of the device is increased, the effective length of a discharge current path for discharging ESD current can be prolonged, the equivalent resistance of the device is increased, the maintaining voltage of the device is improved, the main structure of the silicon controlled rectifier can be completely isolated from the P-type substrate by the N-type deep trap, and the anti-leakage capacity of the device is effectively improved.

3. The sizes S2 of the first P + injection region and the fourth P + injection region in the first N well and the second N well are adjustable, when the size S2 is increased, the parasitic PNP tube gain is increased, the positive feedback link is strengthened, and the failure current is improved, so that the failure current of the device is increased along with the increase of the size S2.

Drawings

FIG. 1 is a cross-sectional view of a conventional bidirectional SCR electrostatic protection device;

FIG. 2 is an equivalent circuit diagram of a conventional bidirectional SCR ESD protection device;

FIG. 3 is a cross-sectional view of an asymmetric bidirectional thyristor ESD device with high robustness according to the present invention;

FIG. 4 is an equivalent circuit diagram of the strong robustness asymmetric bidirectional thyristor electrostatic discharge protection device provided by the present invention;

fig. 5 is a simulation diagram of the total current density distribution of the strong robustness asymmetric bidirectional thyristor electrostatic protection device provided by the invention.

Detailed Description

The present invention will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

As shown in fig. 3, a strong robustness asymmetric bidirectional triode thyristor electrostatic discharge protection device includes a P-type substrate 101; an N-type deep well 201 is arranged in the P-type substrate 101; a first N well 301, a first P well 401, a second N well 302 and a second P well 402 are arranged above the N-type deep well 201 from left to right; a first P + injection region 501 is arranged in the first N well 301; a first N + injection region 503 and a third P + injection region 504 are arranged in the first P well 401; a second N + implantation region 505 and a fourth P + implantation region 506 are arranged in the second N well 302; a third N + implantation region 508 is disposed in the second P well 402; a second P + injection region 502 is arranged between the first N well 301 and the first P well 401; a fifth P + injection region 507 is arranged between the second N well 302 and the second P well 402; two electrodes of the first P + injection region 501 and the third N + injection region 508 are connected together to serve as a cathode of the device, and four electrodes of the first N + injection region 503, the third P + injection region 504, the second N + injection region 505 and the fourth P + injection region 506 are connected together to serve as an anode of the device.

In one embodiment, a first field oxide isolation region 601 is disposed between the left side of the first P + implantation region 501 and the left side edge of the P-type substrate 101; a second field oxide isolation region 602 is arranged on the right side of the first P + implantation region 501 and the left side of the second P + implantation region 502; a third field oxide isolation region 603 is disposed on the right side of the second P + implantation region 502 and the left side of the first N + implantation region 503; a fourth field oxide isolation region 604 is disposed on the right side of the first N + implantation region 503 and the left side of the third P + implantation region 504; a fifth field oxide isolation region 605 is arranged on the right side of the third P + implantation region 504 and the left side of the second N + implantation region 505; a sixth field oxide isolation region 606 is arranged on the right side of the second N + implantation region 505 and the left side of the fourth P + implantation region 506; a seventh field oxide isolation region 607 is arranged on the right side of the fourth P + implantation region 506 and the left side of the fifth P + implantation region 507; an eighth field oxide isolation region 608 is disposed on the right side of the fifth P + implantation region 507 and the left side of the third N + implantation region 508; a ninth field oxide isolation region 609 is disposed between the right side of the third N + implantation region 508 and the right side edge of the P-type substrate 101.

In one embodiment, the first field oxide isolation region 601 and the second field oxide isolation region 602 are located on the surface of the first N well 301; the third field oxide isolation region 603 and the fourth field oxide isolation region 604 are located on the surface of the first P well 401; the left side of the fifth field oxide isolation region 605 is located on the surface of the first P-well 401, and the right side of the fifth field oxide isolation region 605 is located on the surface of the second N-well 302; the sixth field oxide isolation region 606 and the seventh field oxide isolation region 607 are located on the surface of the second N well 302; the eighth field oxide isolation region 608 and the ninth field oxide isolation region 609 are located on the surface of the second P well 402.

In an embodiment, as shown in fig. 3, when the high voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to the low potential, the fourth P + injection region 506, the second N well 302, and the second P well 402 form a PNP type transistor, the second N well 302, the second P well 402, and the third N + injection region 508 form an NPN type transistor, and a forward SCR path is formed after the parasitic PNP and parasitic NPN are turned on. When the high-voltage ESD pulse reaches the cathode of the device and the anode of the device is connected to the low potential, the first P + injection region 501, the first N well 301, and the first P well 401 constitute a PNP type triode, the first N well 301, the first P well 401, and the first N + injection region 503 constitute an NPN type triode, and a reverse SCR path is formed when the parasitic PNP and parasitic NPN are turned on.

When the high-voltage ESD pulse reaches the anode of the device, the cathode of the device is connected to a low potential, the ESD current flows into the second N well 302, the second P well 402, and the third N + injection region 508 along the fourth P + injection region 506, when the ESD current increases to a certain value, the reverse PN junction formed by the fifth P + injection region 507 and the second N well 302 is avalanche-broken, so as to generate an avalanche-broken current and form a voltage drop on the equivalent resistance of the second N well 302, as can be seen from the equivalent circuit diagram of fig. 4, when the equivalent resistance is R, the voltage drop is formed on the equivalent resistance _n When the voltage drop reaches 0.7V, the longitudinal PNP type triode is conducted and provides base current for the transverse NPN triode to further promote the conduction, and positive feedback is formedThe effect is that the forward SCR path is electrostatically drained at this time. When a high-voltage ESD pulse reaches the cathode of the device, the anode of the device is connected with a low potential, ESD current flows into the first N well 301, the first P well 401 and the first N + injection region 503 along the first P + injection region 501, when the ESD current increases to a certain value, an avalanche breakdown occurs at a reverse PN junction formed by the second P + injection region 502 and the first N well 301, avalanche breakdown current is generated, and a voltage drop is formed on the equivalent resistance of the second P well 401, as can be seen from an equivalent circuit diagram 4, when the equivalent resistance R is equal to the equivalent resistance R _P When the voltage drop reaches 0.7V, the transverse NPN type triode is conducted and provides base current for the longitudinal PNP triode so as to promote the conduction of the longitudinal PNP triode, a positive feedback effect is formed, and at the moment, the reverse SCR path carries out electrostatic discharge.

Compared with the traditional bidirectional symmetrical silicon controlled electrostatic protection device, the device changes the path of the traditional symmetrical bidirectional silicon controlled electrostatic protection device, the reverse bias PN junction formed by the fifth P + injection region 507, the second N well 302, the second P + injection region 502 and the first N well 301 enables the device to have lower trigger voltage, meanwhile, the device has an additional leakage path, and as can be seen from the simulation chart 5 of total current density distribution of the device, the current density distribution below the second P + injection region 502 and the fifth P + injection region 506 is the most intensive, which indicates that the path is a main leakage path, and meanwhile, the current is also intensive in the N-type deep well 201, which indicates that the leakage path is a secondary leakage path, which can guide the current to flow to the deep part of the device, and can effectively improve the maintaining voltage and the failure current of the device.

The first P well 401 and the second P well 402 can increase the distance between the cathode and the anode of the device, the holding voltage of the device can be effectively improved, the main structure of the silicon controlled rectifier can be completely isolated from the P-type substrate 101 by the N-type deep well 201, and the anti-leakage capacity of the device is effectively improved.

The sizes S2 of the first P + injection region 501 and the fourth P + injection region 506 in the first N well 301 and the second N well 302 are adjustable, and when S2 is increased, the parasitic PNP transistor gain is increased, the positive feedback link is strengthened, and the failure current is increased, so that the failure current of the device is increased along with the increase of the size S2.

The embodiment of the invention also provides a manufacturing method of the high-robustness asymmetric bidirectional thyristor electrostatic protection device, which comprises the following steps:

the method comprises the following steps: forming an N-type deep well 201 in a P-type substrate 101;

step two: a first N well 301, a first P well 401, a second N well 302 and a second P well 402 are generated above the N-type deep well 201;

step three: a first field oxide isolation region 601, a second field oxide isolation region 602, a third field oxide isolation region 603, a fourth field oxide isolation region 604, a fifth field oxide isolation region 605, a sixth field oxide isolation region 606, a seventh field oxide isolation region 607, an eighth field oxide isolation region 608 and a ninth field oxide isolation region 609 are sequentially formed in the P-type substrate 101 from left to right;

step four: forming a first P + injection region 501 in the first N well 301 from left to right in sequence, forming a first N + injection region 503 and a third P + injection region 504 in the first P well 401 from left to right in sequence, forming a second P + injection region 502 between the contact surfaces of the first N well 301 and the first P well 401, forming a second N + injection region 505 and a fourth P + injection region 506 in the second N well 302 from left to right in sequence, forming a third N + injection region 508 in the second P well 402 from left to right in sequence, and forming a fifth P + injection region 507 between the contact surfaces of the second N well 302 and the second P well 402; the left side of the first field oxide isolation region 601 is in contact with the edge of the left side of the P-type substrate 101, the right side of the first field oxide isolation region 601 is in contact with the left side of the first P + implantation region 501, the right side of the first P + implantation region 501 is in contact with the left side of the second field oxide isolation region 602, the right side of the second field oxide isolation region 602 is in contact with the left side of the second P + implantation region 502, and the right side of the second P + implantation region 502 is in contact with the left side of the third field oxide isolation region 603; the right side of the third field oxide isolation region 603 is in contact with the left side of the first N + implantation region 503, the right side of the first N + implantation region 503 is in contact with the left side of the fourth field oxide isolation region 604, the right side of the fourth field oxide isolation region 604 is in contact with the left side of the third P + implantation region 504, the right side of the third P + implantation region 504 is in contact with the left side of the fifth field oxide isolation region 605, the right side of the fifth field oxide isolation region 605 is in contact with the left side of the second N + implantation region 505, the right side of the second N + implantation region 505 is in contact with the left side of the sixth field oxide isolation region 606, the right side of the sixth field oxide isolation region 606 is in contact with the left side of the fourth P + implantation region 506, the right side of the fourth P + implantation region 506 is in contact with the left side of the seventh field oxide region 607, the right side of the seventh field oxide isolation region 607 is in contact with the left side of the fifth P + implantation region 507, the right side of the fifth P + implantation region 507 is in contact with the left side of the eighth field oxide isolation region 608, the right side of the eighth field oxide isolation region 608 is in contact with the third N + implantation region 508, the right side of the ninth field oxide isolation region 508 is in contact with the ninth field oxide isolation region 508, and the ninth field oxide isolation region 508;

step five: annealing the first P + implantation region 501, the second P + implantation region 502, the first N + implantation region 503, the third P + implantation region 504, the second N + implantation region 505, the fourth P + implantation region 506, the fifth P + implantation region 507, and the third N + implantation region 508 to eliminate the migration of impurities in the implantation regions;

step six: the first N + implantation region 503, the third P + implantation region 504, the second N + implantation region 505, and the fourth P + implantation region 506 are connected together to serve as an anode of the device, and the first P + implantation region 501 and the third N + implantation region 508 are connected together to serve as a cathode of the device.

Optionally, the method further comprises:

growing a silicon dioxide film on the P-type substrate 101, and then depositing a silicon nitride film; spin-coating a photoresist layer on a wafer, and adding a mask plate to expose and develop the wafer to form an isolation shallow slot; and etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed.

The manufacturing method of the asymmetric bidirectional thyristor electrostatic protection device with strong robustness is simple in process and convenient to operate. The manufactured asymmetric bidirectional thyristor electrostatic protection device structure has a reverse avalanche breakdown surface with lower breakdown voltage, and can effectively reduce the trigger voltage of the device. Meanwhile, the design enables the device to have an extra ESD current discharge path, and the device maintenance voltage can be effectively improved. The device can be applied to ESD protection design of 0-5.5V I/O ports, and can effectively protect internal chips and keep away from the risk of latch-up. The device of the embodiment of the invention adopts a BCDMOS process with the thickness of 0.25 mu m.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.

Claims (7)

1. A strong robustness asymmetric bidirectional controllable silicon electrostatic protection device is characterized by comprising a P-type substrate; an N-type deep well is arranged in the P-type substrate; a first N well, a first P well, a second N well and a second P well are arranged above the N-type deep well from left to right; a first P + injection region is arranged in the first N well; a first N + injection region and a third P + injection region are arranged in the first P well; a second N + injection region and a fourth P + injection region are arranged in the second N well; a third N + injection region is arranged in the second P well; a second P + injection region is arranged between the first N well and the first P well; a fifth P + injection region is arranged between the second N well and the second P well; the two electrodes of the first P + injection region and the third N + injection region are connected together to serve as a cathode of the device, and the four electrodes of the first N + injection region, the third P + injection region, the second N + injection region and the fourth P + injection region are connected together to serve as an anode of the device.

2. The strong robustness asymmetric bidirectional thyristor electrostatic protection device of claim 1, wherein a first field oxide isolation region is disposed between a left side of the first P + implant region and a left side edge of the P-type substrate; a second field oxide isolation region is arranged on the right side of the first P + injection region and on the left side of the second P + injection region; a third field oxide isolation region is arranged on the right side of the second P + injection region and the left side of the first N + injection region; a fourth field oxide isolation region is arranged on the right side of the first N + injection region and the left side of the third P + injection region; a fifth field oxide isolation region is arranged on the right side of the third P + injection region and the left side of the second N + injection region; a sixth field oxide isolation region is arranged on the right side of the second N + injection region and the left side of the fourth P + injection region; a seventh field oxide isolation region is arranged on the right side of the fourth P + injection region and the left side of the fifth P + injection region; an eighth field oxide isolation region is arranged on the right side of the fifth P + injection region and the left side of the third N + injection region; and a ninth field oxide isolation region is arranged between the right side of the third N + injection region and the right side edge of the P-type substrate.

3. The strong robustness asymmetric triac electrostatic protection device of claim 2 wherein said first field oxide isolation region and said second field oxide isolation region are located on a surface of said first N-well; the third field oxygen isolation region and the fourth field oxygen isolation region are positioned on the surface of the first P well; the left side of the fifth field oxide isolation region is positioned on the surface of the first P well, and the right side of the fifth field oxide isolation region is positioned on the surface of the second N well; the sixth field oxide isolation region and the seventh field oxide isolation region are positioned on the surface of the second N well; the eighth field oxide isolation region and the ninth field oxide isolation region are located on the surface of the second P well.

4. The strong robustness asymmetric bidirectional triode thyristor electrostatic protection device according to claim 2, wherein when a high voltage ESD pulse reaches an anode of the device and a cathode of the device is connected with a low potential, the fourth P + injection region, the second N well and the second P well form a PNP type triode, the second N well, the second P well and the third N + injection region form an NPN type triode, and a forward SCR path is formed after a parasitic PNP and a parasitic NPN are turned on; when the high-voltage ESD pulse reaches the cathode of the device and the anode of the device is connected with a low potential, the first P + injection region, the first N well and the first P trap form a PNP type triode, the first N well, the first P well and the first N + injection region form an NPN type triode, and a reverse SCR path is formed after the parasitic PNP and parasitic NPN are started.

5. The strong robustness asymmetric bidirectional triode thyristor electrostatic discharge protection device according to claim 1, wherein when a high voltage ESD pulse reaches an anode of the device, a cathode of the device is connected with a low potential, an ESD current flows into the second N well, the second P well and the third N + injection region along the fourth P + injection region, when the ESD current increases to a certain value, a reverse PN junction formed by the fifth P + injection region and the second N well is subjected to avalanche breakdown to generate avalanche breakdown current and form a voltage drop on an equivalent resistance of the second N well, when the voltage drop on the equivalent resistance reaches 0.7V, a longitudinal PNP type triode is conducted and provides a base current for a transverse NPN triode to further promote the conduction of the transverse NPN triode to form a positive feedback effect, and then a forward SCR path is successfully started; when the high-voltage ESD pulse reaches the cathode of the device, the anode of the device is connected with a low potential, ESD current flows into the first N well, the first P well and the first N + injection region along the first P + injection region, when the ESD current is increased to a certain value, avalanche breakdown occurs in a reverse PN junction formed by the second P + injection region and the first N well, avalanche breakdown current is generated, voltage drop is formed on the equivalent resistance of the second P well, when the voltage drop on the equivalent resistance reaches 0.7V, the transverse NPN type triode is conducted, base current is provided for the longitudinal PNP triode, conduction of the longitudinal PNP triode is further promoted, a positive feedback effect is formed, and at the moment, the reverse SCR path is successfully started.

6. The manufacturing method of the high-robustness asymmetric bidirectional thyristor electrostatic protection device is characterized by comprising the following steps of:

the method comprises the following steps: forming an N-type deep well in a P-type substrate;

step two: generating a first N well, a first P well, a second N well and a second P well above the N-type deep well;

step three: sequentially generating a first field oxide isolation region, a second field oxide isolation region, a third field oxide isolation region, a fourth field oxide isolation region, a fifth field oxide isolation region, a sixth field oxide isolation region, a seventh field oxide isolation region, an eighth field oxide isolation region and a ninth field oxide isolation region from left to right in the P-type substrate;

step four: sequentially forming a first P + injection region in the first N well from left to right, sequentially forming a first N + injection region and a third P + injection region in the first P well from left to right, simultaneously forming a second P + injection region between the first N well and the contact surface of the first P well, sequentially forming a second N + injection region and a fourth P + injection region in the second N well from left to right, sequentially forming a third N + injection region in the second P well from left to right, and simultaneously forming a fifth P + injection region between the second N well and the contact surface of the second P well; the left side of the first field oxide isolation region is in contact with the edge of the left side of the P-type substrate, the right side of the first field oxide isolation region is in contact with the left side of the first P + injection region, the right side of the first P + injection region is in contact with the left side of the second field oxide isolation region, the right side of the second field oxide isolation region is in contact with the left side of the second P + injection region, and the right side of the second P + injection region is in contact with the left side of the third field oxide isolation region; the third field oxide isolation region right side is in contact with the first N + implant region left side, the first N + implant region right side is in contact with the fourth field oxide isolation region left side, the fourth field oxide isolation region right side is in contact with the third P + implant region left side, the third P + implant region right side is in contact with the fifth field oxide isolation region left side, the fifth field oxide isolation region right side is in contact with the second N + implant region left side, the second N + implant region right side is in contact with the sixth field oxide isolation region left side, the sixth field oxide isolation region right side is in contact with the fourth P + implant region left side, the fourth P + implant region right side is in contact with the seventh field oxide isolation region left side, the seventh field oxide isolation region right side is in contact with the fifth P + implant region left side, the fifth P + implant region right side is in contact with the eighth field oxide isolation region left side, the eighth field oxide isolation region right side is in contact with the third N + implant region left side, the third N + implant region right side is in contact with the third field oxide isolation region left side, and the ninth field oxide isolation region right side is in contact with the ninth field oxide isolation region edge P substrate right side;

step five: annealing the first P + injection region, the second P + injection region, the first N + injection region, the third P + injection region, the second N + injection region, the fourth P + injection region, the fifth P + injection region and the third N + injection region to eliminate the migration of impurities in the injection regions;

step six: and connecting the first N + injection region, the third P + injection region, the second N + injection region and the fourth P + injection region together to serve as an anode of the device, and connecting the first P + injection region and the third N + injection region together to serve as a cathode of the device.

7. The method for manufacturing a strong robustness asymmetric bidirectional triode thyristor electrostatic discharge protection device according to claim 6, further comprising the steps of:

growing a silicon dioxide film on the P-type substrate, and then depositing a silicon nitride film; spin-coating a photoresist layer on the wafer, and adding a mask plate to expose and develop the wafer to form the shallow isolation trench; and etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed.

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