CN110211956B - Grid enhanced type light-operated silicon controlled electrostatic discharge device structure and manufacturing method thereof - Google Patents
Grid enhanced type light-operated silicon controlled electrostatic discharge device structure and manufacturing method thereof Download PDFInfo
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- CN110211956B CN110211956B CN201910577178.5A CN201910577178A CN110211956B CN 110211956 B CN110211956 B CN 110211956B CN 201910577178 A CN201910577178 A CN 201910577178A CN 110211956 B CN110211956 B CN 110211956B
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
Abstract
The invention discloses a grid enhanced photo-controlled silicon controlled electrostatic discharge device structure, which comprises a substrate P-Sub; a DN-Well area is arranged in the substrate P-Sub; a first P-Well area and a second P-Well area are arranged in the DN-Well area; a first polysilicon gate and a second P + injection region are arranged in the first P-Well region; and a third P + injection region and a second polysilicon gate are arranged in the second P-Well region. According to the invention, the first polysilicon gate, the second P + injection region, the third P + injection region and the second polysilicon gate form a gate enhanced light control structure, so that the holding voltage of the bidirectional silicon controlled device can be regulated, namely the concentration of P-Well and DN-Well is regulated by utilizing a photon-generated carrier generated by avalanche multiplication, thereby the concentration of a base region of a parasitic BJT is changed, and the purposes of changing emission efficiency and regulating and controlling the holding voltage are achieved.
Description
Technical Field
The invention relates to the field of electrostatic protection, in particular to a grid enhanced type light-operated silicon controlled electrostatic discharge device structure and a manufacturing method thereof.
Background
With the continuous progress of society and the continuous improvement of scientific level, the development of integrated circuits has entered the nanometer level. Electrostatic discharge (ESD) is one of the main causes of integrated circuit chip failure, and electrostatic accumulation is in the human daily life. Accordingly, more and more IC design engineers are beginning to focus on protection of semiconductor ESD. According to the relevant data, the electronic product failure caused by the ESD phenomenon reaches over 58 percent and the economic loss caused by the ESD phenomenon reaches hundreds of billions under the large environment in the field of integrated circuit microelectronics, and the data fully explains the importance of the electrostatic discharge protection. A high performance ESD protection device can improve the yield and robustness of electronic products. Under the environment of variable wide power supply voltage, factors such as large current, variable working voltage, strong electromagnetic interference and the like cause great troubles to ESD design, and the ESD protection device needs to occupy small area and has strong latch-up resistance, which is the biggest problem to be overcome by ESD designers at present.
A conventional bidirectional thyristor (DDSCR) device has forward and reverse symmetric ESD discharge paths. When the device is started, the trigger voltage of the thyristor is higher and the holding voltage is lower due to the latch-up positive feedback mechanism of the parasitic PNP and parasitic NPN in the device, so that the thyristor can bear higher ESD current stress without failure. As a very common ESD protection device, a thyristor structure is regarded as an ESD device having the best robustness per unit area, and various improved thyristor structures are widely used in various fields. However, the trigger voltage of the structure is higher because the trigger of the traditional silicon controlled rectifier depends on the avalanche breakdown voltage of a reverse bias PN junction of a trigger surface. When the BJT is turned on completely, the holding voltage of the device is very low and is not controllable, which is easy to generate latch-up inside the device, and when the conventional silicon controlled rectifier is applied in a high voltage environment, the ESD protection capability of the device is slightly insufficient. These defects will cause the internal core circuitry of the protected chip to be effectively protected. Therefore, in the ESD design in the wide power voltage field, when the thyristor structure is improved, the holding voltage of the structure should be increased to keep the holding voltage at 1.2 times VDD all the time, so as to achieve the purpose of being controllable. And reducing the trigger voltage of the structure, so that the trigger voltage of the device is lower than the breakdown voltage of the lowest gate oxide layer in the chip. And also to ensure that the structure has a high level of failure.
A cross-sectional view and equivalent circuit of a conventional triac device is shown in fig. 1. Because the bidirectional triode thyristor has a symmetrical structure, the working principle of the forward direction is consistent with that of the reverse direction. When the bidirectional controllable silicon is positively started, when the voltage difference between the anode and the cathode is lower than the trigger voltage of the device, the bidirectional controllable silicon device is in a high-resistance state, when the voltage difference between the anode and the cathode reaches the trigger voltage of the bidirectional controllable silicon device, the reverse bias PN junction of DN-Well and P + injection regions (close to the cathode) generates an avalanche breakdown effect, and carriers multiplied by avalanche pass through the parasitic resistance R of DN-Well n A voltage drop is generated, and when the voltage drop reaches the conduction voltage of the base-emitter of the parasitic PNP triode, the PNP is turned on, thereby causing the parasitic resistance R passing through the P-Well (close to the cathode) p2 The current increases rapidly, and the voltage drop produced by it conducts parasitic NPN 2 And in the triode, a parasitic PNPN path is gradually formed, ESD current is discharged, and the silicon controlled path is completely opened at the moment. When the bidirectional controllable silicon is reversely turned on, when the voltage difference between the anode and the cathode is lower than the trigger voltage of the device, the bidirectional controllable silicon device is in a high-resistance state, when the voltage difference between the anode and the cathode reaches the trigger voltage, the reverse-biased PN junctions of DN-Well and P + injection regions (close to the anode) generate an avalanche breakdown effect, and carriers multiplied by avalanche pass through a parasitic resistance R of DN-Well n A voltage drop is generated, and when the voltage drop reaches the base-emitter turn-on voltage of the parasitic PNP transistor, the PNP transistor turns on, resulting in a parasitic resistance R across the P-Well (near the anode) p1 The current of (2) increases rapidly, the voltage drop produced thereby decreasesAll parasitic NPN 1 And a triode and a parasitic PNPN path are gradually formed, ESD current is discharged, and the silicon controlled path is completely opened at the moment. At the moment, the bidirectional controllable silicon device generates a negative resistance phenomenon, the phenomenon that the current is continuously increased and the voltage is reduced occurs, and when the voltage is delayed to the maintaining voltage, the device works in a low-resistance area. When the current is finally increased to cause the bidirectional controllable silicon device to generate secondary breakdown, the structure of the device is completely failed at the moment.
Disclosure of Invention
In order to solve the technical problems, the invention provides a grid enhanced type light-operated silicon controlled rectifier electrostatic discharge device structure which is simple in structure and strong in ESD resistance, and a manufacturing method thereof.
The technical scheme for solving the problems is as follows: the utility model provides a grid enhancement mode light-operated silicon controlled rectifier electrostatic discharge device structure which characterized in that: comprises a P-type substrate; a deep N-well region is arranged in the P-type substrate; a first P-Well region and a second P-Well region are sequentially arranged in the deep N-Well region from left to right; a first field oxide isolation region, a first P + injection region, a second field oxide isolation region, a first N + injection region, a first polysilicon gate, a third field oxide isolation region and a second P + injection region are sequentially arranged in the first P-Well region from left to right; a third P + injection region, a sixth field oxide isolation region, a second polysilicon gate, a third N + injection region, a seventh field oxide isolation region, a fourth P + injection region and an eighth field oxide isolation region are sequentially arranged in the second P-Well region from left to right; the second P + injection region crosses the surfaces of the first P-Well region and the deep N-Well region, the third P + injection region crosses the surfaces of the deep N-Well region and the second P-Well region, and a fourth field oxide isolation region, a second N + injection region and a fifth field oxide isolation region are sequentially arranged between the second P + injection region and the second P + injection region from left to right; the first P + injection region, the first N + injection region and the first polysilicon gate are connected together and used as a cathode of the device; and the second polysilicon gate, the third N + injection region and the fourth P + injection region are connected together and used as an anode of the device.
According to the grid enhanced type light-controlled silicon controlled electrostatic discharge device structure, the first polysilicon grid, the second P + injection area and the third P + injection area in the first P-Well area and the second polysilicon grid in the second P-Well area form the grid enhanced type light-controlled structure, and electric field forces consistent with an ESD current discharge path are respectively generated by the grid enhanced type light-controlled structure at the anode and the cathode of the device, so that the movement of current carriers in the device is promoted, and the failure current of the device is improved.
Above-mentioned light-operated silicon controlled rectifier electrostatic discharge device structure of grid enhancement mode, the left side of first field oxygen isolation region and the left side edge parallel and level of P type substrate, the right side of first field oxygen isolation region is connected with the left side in first P + injection region, the right side in first P + injection region is connected with the left side in second field oxygen isolation region, the right side in second field oxygen isolation region is connected with the left side in first N + injection region, the right side in first N + injection region is connected with the left side in first polysilicon gate, the right side in first polysilicon gate is connected with the left side in third field oxygen isolation region, the right side in third field oxygen isolation region is connected with the left side in second P + injection region.
According to the structure of the grid enhanced light-controlled silicon controlled electrostatic discharge device, the right side of the second P + injection region is connected with the left side of the fourth field oxygen isolation region, the right side of the fourth field oxygen isolation region is connected with the left side of the second N + injection region, the right side of the second N + injection region is connected with the left side of the fifth field oxygen isolation region, and the right side of the fifth field oxygen isolation region is connected with the left side of the third P + injection region.
Above-mentioned light-operated silicon controlled rectifier electrostatic discharge device structure of grid enhancement mode, the right side in third P + injection district is connected with the left side in sixth field oxygen isolation district, the right side in sixth field oxygen isolation district is connected with the left side of second polycrystalline silicon gate, the right side in second polycrystalline silicon gate is connected with the left side in third N + injection district, the right side in third N + injection district is connected with the left side in seventh field oxygen isolation district, the right side in seventh field oxygen isolation district is connected with the left side in fourth P + injection district, the right side in fourth P + injection district is connected with the left side in eighth field oxygen isolation district, the right side in eighth field oxygen isolation district and the right side edge parallel and level of P type substrate.
The gate-enhanced photo-controlled silicon controlled electrostatic discharge device structure is just rightWhen ESD stress comes to the anode of the device and the cathode of the device is grounded, the first N + injection region, the first P-Well region and the DN-Well form a longitudinal NPN 2 The triode, the first P-Well region, the DN-Well region and the fourth P + injection region form a first transverse PNP triode, and the base electrode and the longitudinal NPN triode of the first transverse PNP triode 2 The collectors of the transistors are connected together by a parasitic resistor DN-Well, a longitudinal NPN 2 The base of the transistor and the collector of the first lateral PNP transistor are connected together through a parasitic resistance in the first P-Well region, i.e. the NPN transistor 2 The triode and the first transverse PNP triode form a silicon controlled structure.
According to the grid enhanced type photo-controlled silicon controlled electrostatic discharge device structure, when reverse ESD stress comes to the anode of the device and the cathode of the device is at the ground potential, the third N + injection region, the second P-Well region and the DN-Well form a longitudinal NPN 1 The triode, the second P-Well region, DN-Well and the first P + injection region form a second lateral PNP triode, and the base electrode and the longitudinal NPN transistor of the second lateral PNP triode 1 The collectors of the transistors are connected together by a parasitic resistor DN-Well, a longitudinal NPN 1 The base of the transistor and the collector of the second lateral PNP transistor are connected together through a parasitic resistance in the second P-Well region, i.e. the vertical NPN 1 The triode and the second transverse PNP triode form a silicon controlled structure.
A manufacturing method of a grid enhanced type light-operated silicon controlled electrostatic discharge device structure comprises the following steps:
the method comprises the following steps: forming a deep N-well region in a P-type substrate;
step two: forming first to eighth field oxide isolation regions on a P-type substrate by photolithography;
step three: forming a first P-Well region and a second P-Well region in the deep N-Well region through photoetching;
step four: forming a first polysilicon gate in the first P-Well region, and forming a second polysilicon gate in the second P-Well region;
step five: forming a first P + injection region and a second P + injection region in the first P-Well region, and forming a third P + injection region and a fourth P + injection region in the second P-Well region by photoetching;
step six: and forming a first N + injection region in the first P-Well region, forming a second N + injection region in the deep N-Well region and forming a third N + injection region in the second P-Well region by photoetching.
The technical scheme for solving the problems is as follows:
1. according to the invention, the first polysilicon gate, the second P + injection region, the third P + injection region and the second polysilicon gate in the first P-Well region and the second P-Well region form the grid enhanced light control structure, the grid enhanced light control structure is adopted to enable the maintenance voltage of the bidirectional silicon controlled device to be adjustable, namely the concentration of P-Well and DN-Well is adjusted by utilizing a photon-generated carrier generated by avalanche multiplication, so that the concentration of a base region of a BJT (bipolar junction transistor) is changed, the purposes of changing emission efficiency and adjusting and controlling the maintenance voltage are achieved, the latch-up effect of the device can be effectively prevented, and the signal integrity of a chip kernel circuit is ensured.
2. The invention adopts the grid enhanced light control structure to reduce the on resistance of the bidirectional controllable silicon device, the electric field effect generated by the grid enhances the discharge capacity of the positive feedback loop of the controllable silicon, and the failure current of the device is obviously improved. Therefore, the device can bear high-strength ESD stress without premature breakdown, the leakage current of the device is always kept at a lower order of magnitude, and a surface ESD channel path generated by an electric field effect can be blocked and inhibited by the isolation layer.
3. The invention has simple process and convenient operation. The manufactured gate enhanced type light-operated silicon controlled rectifier electrostatic discharge device structure does not violate layout design rules, and layers except a CMOS (complementary metal oxide semiconductor) process are not used, so that the bidirectional silicon controlled rectifier device structure can be applied to the ESD protection design in a variable wide power supply voltage environment, an inner core chip is effectively protected, the latch-up effect is prevented, and the ESD resistance of the chip is improved.
Drawings
Fig. 1 is a cross-sectional view and an equivalent circuit schematic diagram of a conventional triac structure.
Fig. 2 is a circuit diagram of a structure of a gate-enhanced scr electrostatic discharge device according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a three-dimensional parasitic structure of a gate-enhanced photo-controlled silicon electrostatic discharge device structure in an embodiment of the present invention.
Fig. 4 is an equivalent circuit of the gate-enhanced photo-controlled silicon electrostatic discharge device structure for forward ESD protection, i.e., an ESD current discharge path, according to an embodiment of the present invention.
Fig. 5 is an ESD current discharge path, which is an equivalent circuit of the gate-enhanced photothyristor electrostatic discharge device structure for reverse ESD protection in the embodiment of the present invention.
Fig. 6 is a top view of a gate-enhanced triac electrostatic discharge device in an embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the drawings and examples.
As shown in fig. 1 to 6, a gate enhanced scr electrostatic discharge device structure is characterized in that: comprises a P-type substrate P-Sub101; a deep N-well region 102 is arranged in the P-type substrate P-Sub101; a first P-Well region 103 and a second P-Well region 104 are sequentially arranged in the deep N-Well region 102 from left to right; a first field oxide isolation region 201, a first P + injection region 105, a second field oxide isolation region 202, a first N + injection region 106, a first polysilicon gate 209, a third field oxide isolation region 203 and a second P + injection region 107 are sequentially arranged in the first P-Well region 103 from left to right; a third P + implantation region 109, a sixth field oxide isolation region 206, a second polysilicon gate 210, a third N + implantation region 110, a seventh field oxide isolation region 207, a fourth P + implantation region 111, and an eighth field oxide isolation region 208 are sequentially disposed in the second P-Well region 104 from left to right; the second P + implantation region 107 crosses over the surfaces of the first P-Well region 103 and the deep N-Well region 102, the third P + implantation region 109 crosses over the surfaces of the deep N-Well region 102 and the second P-Well region 104, and a fourth field oxide isolation region 204, a second N + implantation region 108, and a fifth field oxide isolation region 205 are sequentially arranged between the second P + implantation region 107 and the second P + implantation region 107 from left to right. P-Sub is the P-type substrate region, DN-Well is the deep N-Well region.
The first P + injection region 105 is connected with the first metal layer 211 through a contact hole, the first N + injection region 106 is connected with the second metal layer 212 through a contact hole, the first polysilicon gate 209 is connected with the third metal layer 213 through a contact hole, a metal through hole 302 is arranged on the seventh metal layer 301 of the metal layer 2, and the first metal layer 211, the second metal layer 212 and the third metal layer 213 are all connected with the seventh metal layer 301 through the metal through hole 302 and used as a cathode of a device.
The second polysilicon gate 210 is connected with a fourth metal layer 214 through a contact hole, the third N + injection region 110 is connected with a fifth metal layer 215 through a contact hole, the fourth P + injection region 111 is connected with a sixth metal layer 216 through a contact hole, a metal through hole 304 is formed in an eighth metal layer 303, the fourth metal layer 214, the fifth metal layer 215 and the sixth metal layer 216 are connected with the eighth metal layer 303 through the metal through hole 304 and serve as an anode of a device.
The left side of the first field oxide isolation region 201 is flush with the left side edge of the P-type substrate P-Sub101, the right side of the first field oxide isolation region 201 is connected with the left side of the first P + implantation region 105, the right side of the first P + implantation region 105 is connected with the left side of the second field oxide isolation region 202, the right side of the second field oxide isolation region 202 is connected with the left side of the first N + implantation region 106, the right side of the first N + implantation region 106 is connected with the left side of the first polysilicon gate 209, the right side of the first polysilicon gate 209 is connected with the left side of the third field oxide isolation region 203, and the right side of the third field oxide isolation region 203 is connected with the left side of the second P + implantation region 107.
The right side of the second P + implantation region 107 is connected to the left side of the fourth field oxide isolation region 204, the right side of the fourth field oxide isolation region 204 is connected to the left side of the second N + implantation region 108, the right side of the second N + implantation region 108 is connected to the left side of the fifth field oxide isolation region 205, and the right side of the fifth field oxide isolation region 205 is connected to the left side of the third P + implantation region 109.
The right side of the third P + implantation region 109 is connected to the left side of a sixth field oxide isolation region 206, the right side of the sixth field oxide isolation region 206 is connected to the left side of a second polysilicon gate 210, the right side of the second polysilicon gate 210 is connected to the left side of a third N + implantation region 110, the right side of the third N + implantation region 110 is connected to the left side of a seventh field oxide isolation region 207, the right side of the seventh field oxide isolation region 207 is connected to the left side of a fourth P + implantation region 111, the right side of the fourth P + implantation region 111 is connected to the left side of an eighth field oxide isolation region 208, and the right side of the eighth field oxide isolation region 208 is flush with the edge of the right side of the P-Sub 101.
A manufacturing method of a grid enhanced type light-operated silicon controlled electrostatic discharge device structure comprises the following steps:
the method comprises the following steps: a deep N-well region 102 is formed in a P-type substrate P-Sub 101. The method specifically comprises the following steps:
and manufacturing the deep N-well region 102 on the surface of the P-type substrate P-Sub101, and then forming a silicon dioxide film by thermal oxidation to relieve stress damage caused by silicon nitride formed in the subsequent process steps. A layer of silicon nitride is deposited by means of a chemical vapor deposition (LPCVD) technique as a stop layer for CMP in a subsequent process step.
And uniformly coating photoresist on the wafer, and exposing and developing the photoresist, wherein the step is used for defining the shallow trench isolation. And then etching the silicon nitride, the silicon dioxide and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide by using chemical vapor deposition (LPCVD), then polishing by using chemical machinery until the silicon nitride thin film layer is reached, and removing the silicon nitride thin film layer by using hot phosphoric acid wet etching.
Step two: first to eighth field oxygen isolation regions 208 are formed on the P-type substrate P-Sub101 by photolithography. The method specifically comprises the following steps:
using a field oxide isolation (LOCOS) isolation technique, growing a silicon dioxide thin film layer as a buffer layer by using a thermal oxidation method, then depositing silicon nitride by using a chemical vapor deposition (LPCVD) technique, coating a photoresist on a wafer, and defining a first field oxide isolation region 201, a second field oxide isolation region 202, a third field oxide isolation region 203, a fourth field oxide isolation region 204, a fifth field oxide isolation region 205, a sixth field oxide isolation region 206, a seventh field oxide isolation region 207, and an eighth field oxide isolation region 208 by using a photolithography technique. Then, the reactive ions will etch away the silicon nitride on the first field oxide isolation region 201, the second field oxide isolation region 202, the third field oxide isolation region 203, the fourth field oxide isolation region 204, the fifth field oxide isolation region 205, the sixth field oxide isolation region 206, the seventh field oxide isolation region 207, and the eighth field oxide isolation region 208, and then, field implantation is performed to prevent the field from being opened.
Step three: a first P-Well region 103 and a second P-Well region 104 are formed in the deep N-Well region 102 by photolithography. The method specifically comprises the following steps:
photoresist is coated on the wafer for defining the first P-Well region 103 and the second P-Well region 104 (104), then high-energy boron ions are implanted to form a local P-type region, and the photoresist is removed.
And annealing the first P-Well region 103 and the second P-Well region 104, repairing crystal damage of the silicon surface caused by ion implantation, activating implanted impurities, and eliminating further diffusion of the impurities by using an RTP (real-time thermal process).
Step four: a first polysilicon gate 209 is formed in the first P-Well region 103 and a second polysilicon gate 210 is formed in the second P-Well region 104. The method comprises the following specific steps:
the growth of the sacrificial oxide layer is used to trap defects on the silicon surface. The gate oxide layer grows to serve as a gate insulating layer of the transistor, the first polysilicon gate 209, the second polysilicon gate 210, photoresist molding, polysilicon etching, and the specific shape of polysilicon required to be accurately obtained from photoresist are deposited by chemical vapor deposition (LPCVD), and the photoresist layer is removed. And oxidizing the polysilicon for buffering and isolating the polysilicon and the silicon nitride formed in the subsequent step. Depositing a layer of silicon nitride by using chemical vapor deposition (LPCVD), etching the silicon nitride, leaving an isolation side wall, and accurately positioning the ion implantation of a transistor source region and a transistor drain region.
Step five: by photolithography, a first P + implantation region 105 and a second P + implantation region 107 are formed in the first P-Well region 103, and a third P + implantation region 109 and a fourth P + implantation region 111 are formed in the second P-Well region 104. The method specifically comprises the following steps:
and forming photoresist, wherein the photoresist is used for controlling ion implantation, implanting shallow-depth and heavily-doped boron ions, and removing the photoresist layer to form the first P + implantation region 105, the second P + implantation region 107, the third P + implantation region 109 and the fourth P + implantation region 111. Wherein the second P + implantation region 107 and the third P + implantation region 109 are photosensitive regions.
Step six: by photolithography, a first N + implantation region 106 is formed in the first P-Well region 103, a second N + implantation region 108 is formed in the deep N-Well region 102, and a third N + implantation region 110 is formed in the second P-Well region 104. The method specifically comprises the following steps:
and forming photoresist for controlling ion implantation, implanting shallow-depth and heavily-doped arsenic ions, and removing the photoresist layer to form the first N + implantation region 106, the second N + implantation region 108 and the third N + implantation region 110.
The first polysilicon gate 209 in the first P-Well region 103, the second P + implantation region 107, the third P + implantation region 109 in the second P-Well region 104, and the second polysilicon gate 210 form a gate-enhanced light control structure, the first N + implantation region 106 and the third field oxide isolation region 203 are isolated by the first polysilicon gate 209, and the first polysilicon gate 209 is connected to a cathode. The sixth field oxide isolation regions 206 are isolated from the third N + implant regions 110 by the second polysilicon gate 210, and the second polysilicon gate 210 is connected to the anode, as shown in fig. 2 and 3. The existence of the grid enhanced type light control structure enables the maintaining voltage of the bidirectional controllable silicon device to be adjustable, namely the concentration of P-Well and DN-Well is adjusted by utilizing a photon-generated carrier generated by avalanche multiplication, so that the concentration of a base region of a parasitic BJT is changed, and the purposes of changing the emission efficiency and adjusting the maintaining voltage are achieved. Effectively preventing the device from generating latch-up effect and ensuring the signal integrity of the chip core circuit. And due to the existence of the grid structure, the on resistance of the bidirectional controllable silicon device is reduced, the discharge capacity of a positive feedback loop of the controllable silicon is enhanced by the electric field effect generated by the grid, and the failure current of the device is obviously improved. Therefore, the device can bear high-strength ESD stress without premature breakdown, the leakage current of the device is always kept at a lower order of magnitude, and a surface ESD channel path generated by an electric field effect can be blocked and inhibited by the isolation layer.
When positive ESD stress comes to the anode of the device and the cathode is at the ground potential, the first N + injection region 106, the first P-Well region 103 and the deep N-Well region 102 form a longitudinal NPN 2 The transistors, the DN-Well of the first P-Well region 103 and the fourth P + injection region 111 form a first lateral PNP transistor, and the base and the NPN of the first lateral PNP transistor 2 The collector of the triode passes through the parasitic resistance R of the deep N-well region 102 N Connected together, longitudinal NPN 2 The parasitic resistance R of the base of the transistor and the collector of the first lateral PNP transistor through the first P-Well region 103 p2 Connected together, i.e. the longitudinal NPN 2 The triode and the first transverse PNP triode form a silicon controlled structure.
When reverse ESD stress comes to the anode and the cathode is at ground potential, the third N + implantation region 110, the second P-Well region 104 and the deep N-Well region 102 form a longitudinal NPN 1 The transistor, the second P-Well region 104, the deep N-Well region 102 and the first P + implant region 105 form a second lateral PNP transistor, and the base and the longitudinal NPN of the second lateral PNP transistor 1 Parasitic resistance R of the collector of the triode through DN-Well N Connected together, longitudinal NPN 1 The base of the transistor and the collector of the second lateral PNP transistor pass through the parasitic resistance R of the second P-Well region 104 p1 Connected together, i.e. the longitudinal NPN 1 The triode and the second transverse PNP triode form a silicon controlled structure.
The second polysilicon gate 210, based on the first polysilicon gate 209 in the first P-Well region 103, the second P + implant region 107 and the third P + implant region 109 in the second P-Well region 104, constitutes a gate-enhanced photocontrol structure, and the trigger voltage of the device is determined by the reverse avalanche breakdown voltages of the second P + implant region 107 and the DN-Well when forward ESD current stress is applied to the anode, the cathode ground potential, of the device. When reverse ESD current stress comes to the anode of the device, the cathode is at ground potential, the trigger voltage of the device is determined by the reverse avalanche breakdown voltage of the third P + implant region 109 and the DN-Well. The second P + injection region 107 and the third P + injection region 109 which float empty are used as photosensitive regions, the P + injection region and a depletion layer of DN-Well are used for photosensitive, and a large number of photon-generated carriers can be generated under an avalanche effect besides existing avalanche carriers, so that the concentrations of P-Well and DN-Well are increased, the base region concentration of a parasitic BJT is increased, the emission efficiency of an emitter junction is reduced, and the holding voltage of a device is effectively increased. And by changing the illumination power, the maintaining voltage can be regulated and controlled, so that the device can realize a controllable ESD window. Due to the existence of the gate structure, when the device is conducted in the forward direction, the second polysilicon gate 210 positioned at the anode of the device generates a vertically downward electric field force, the first polysilicon gate 209 positioned at the cathode of the device generates a vertically upward electric field force, the movement of carriers in the second P-Well region 104 and the first P-Well region 103 is promoted, and the direction of the electric field force action is consistent with the current direction. The channel ESD path generated by the electric field effect at the anode of the device is blocked by the sixth field oxide isolation region 206, suppressing the surface path and reducing the risk of surface breakdown. When the device is turned on in the reverse direction, the conduction principle is consistent with the forward conduction condition. The electric field effect formed by the first polysilicon gate 209 and the second polysilicon gate 210 plays a role in promoting current discharge in the positive feedback loop of the thyristor, so that the on-resistance of the device can be effectively reduced, and the purpose of improving the failure current is achieved. Due to the generation of the photon-generated carriers, the holding voltage of the device is improved, the latch-up behavior of the device can be effectively prevented, and the robustness of the protected chip is improved.
The invention provides a manufacturing method of a grid enhanced type photo-controlled silicon controlled electrostatic discharge device structure, which is simple in process and convenient to operate. The manufactured gate enhanced type photo-controlled silicon controlled electrostatic discharge device structure does not violate layout design rules, and layers except a CMOS (complementary metal oxide semiconductor) process can be avoided, so that the bidirectional silicon controlled device structure can be applied to the ESD protection design in a variable wide power supply voltage environment, a core chip is effectively protected, the latch-up effect is prevented, and the ESD resistance of the chip is improved.
Claims (8)
1. The utility model provides a grid enhancement mode light-operated silicon controlled rectifier electrostatic discharge device structure which characterized in that: comprises a P-type substrate;
a deep N-well region is arranged in the P-type substrate;
a first P-Well region and a second P-Well region are sequentially arranged in the deep N-Well region from left to right;
a first field oxide isolation region, a first P + injection region, a second field oxide isolation region, a first N + injection region, a first polysilicon gate, a third field oxide isolation region and a second P + injection region are sequentially arranged in the first P-Well region from left to right;
a third P + injection region, a sixth field oxide isolation region, a second polysilicon gate, a third N + injection region, a seventh field oxide isolation region, a fourth P + injection region and an eighth field oxide isolation region are sequentially arranged in the second P-Well region from left to right;
the second P + injection region crosses over the surfaces of the first P-Well region and the deep N-Well region, the third P + injection region crosses over the surfaces of the deep N-Well region and the second P-Well region, and a fourth field oxide isolation region, a second N + injection region and a fifth field oxide isolation region are sequentially arranged between the second P + injection region and the second P + injection region from left to right;
the first P + injection region, the first N + injection region and the first polysilicon gate are connected together and used as a cathode of the device;
and the second polysilicon gate, the third N + injection region and the fourth P + injection region are connected together and used as an anode of the device.
2. The gate-enhanced scr electrostatic discharge device structure of claim 1, wherein: the first polysilicon gate, the second P + injection region in the first P-Well region, the third P + injection region in the second P-Well region and the second polysilicon gate form a grid enhanced light control structure, and the grid enhanced light control structure respectively generates electric field force consistent with an ESD current discharge path at the anode and the cathode of the device, so that the movement of carriers in the device is promoted, and the failure current of the device is improved.
3. The gate-enhanced scr electrostatic discharge device structure of claim 2, wherein: the left side of first field oxygen isolation region and the left side edge parallel and level of P type substrate, the right side of first field oxygen isolation region is connected with the left side in first P + injection zone, the right side in first P + injection zone is connected with the left side in second field oxygen isolation region, the right side in second field oxygen isolation region is connected with the left side in first N + injection zone, the right side in first N + injection zone is connected with the left side in first polysilicon gate, the right side in first polysilicon gate is connected with the left side in third field oxygen isolation region, the right side in third field oxygen isolation region is connected with the left side in second P + injection zone.
4. The gate-enhanced photo-controlled silicon electrostatic discharge device structure of claim 3, wherein: the right side of the second P + injection region is connected with the left side of the fourth field oxygen isolation region, the right side of the fourth field oxygen isolation region is connected with the left side of the second N + injection region, the right side of the second N + injection region is connected with the left side of the fifth field oxygen isolation region, and the right side of the fifth field oxygen isolation region is connected with the left side of the third P + injection region.
5. The gate-enhanced photo-controlled thyristor electrostatic discharge device structure of claim 4, wherein: the right side in third P + injection district is connected with the left side in sixth field oxygen isolation district, the right side in sixth field oxygen isolation district is connected with the left side of second polycrystalline silicon gate, the right side in second polycrystalline silicon gate is connected with the left side in third N + injection district, the right side in third N + injection district is connected with the left side in seventh field oxygen isolation district, the right side in seventh field oxygen isolation district is connected with the left side in fourth P + injection district, the right side in fourth P + injection district is connected with the left side in eighth field oxygen isolation district, the right side in eighth field oxygen isolation district is along the parallel and level with the right side edge of P type substrate.
6. The gate-enhanced photo-controlled thyristor electrostatic discharge device structure of claim 5, wherein: when the positive ESD stress comes to the anode of the device and the cathode of the device is at the ground potential, the first N + injection region, the first P-Well region and the deep N-Well region form a longitudinal NPN 2 The triode, the first P-Well region, the deep N-Well region and the fourth P + injection region form a first transverse PNP triode, and the base electrode and the longitudinal NPN triode of the first transverse PNP triode 2 The collector electrodes of the triodes are connected together through the parasitic resistance of the deep N-well region, and are longitudinally NPN 2 The base of the transistor and the collector of the first lateral PNP transistor are connected together through a parasitic resistance in the first P-Well region, i.e. the NPN transistor 2 The triode and the first transverse PNP triode form a silicon controlled structure.
7. The gate-enhanced photo-controlled silicon electrostatic discharge device structure of claim 5, wherein: when reverse ESD stress comes to the anode of the device and the cathode of the device is at ground potential, the third N + injection region, the second P-Well region and the deep N-Well region form a longitudinal NPN 1 The triode, the second P-Well region, the deep N-Well region and the first P + injection region form a second lateral PNP triode, and the base and the longitudinal NPN of the second lateral PNP triode 1 The collectors of the triodes are connected together by the parasitic resistance of the deep N-well region, and the vertical NPN 1 The base of the transistor and the collector of the second lateral PNP transistor are connected together through a parasitic resistance in the second P-Well region, i.e. the vertical NPN 1 The triode and the second transverse PNP triode form a silicon controlled structure.
8. A method for fabricating a gate-enhanced scr electrostatic discharge device structure according to any one of claims 1 to 7, comprising the steps of:
the method comprises the following steps: forming a deep N-well region in a P-type substrate;
step two: forming first to eighth field oxide isolation regions on a P-type substrate by photolithography;
step three: forming a first P-Well region and a second P-Well region in the deep N-Well region through photoetching;
step four: forming a first polysilicon gate in the first P-Well region, and forming a second polysilicon gate in the second P-Well region;
step five: forming a first P + injection region and a second P + injection region in the first P-Well region, and forming a third P + injection region and a fourth P + injection region in the second P-Well region through photoetching;
step six: through photoetching, a first N + injection region is formed in the first P-Well region, a second N + injection region is formed in the deep N-Well region, and a third N + injection region is formed in the second P-Well region.
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| US9318481B1 (en) * | 2015-05-15 | 2016-04-19 | Allegro Microsystems, Llc | Electrostatic discharge protection device |
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| CN206040643U (en) * | 2016-08-24 | 2017-03-22 | 比亚迪股份有限公司 | Static electricity discharge ESD protection architecture and contain its chip |
| CN107452735A (en) * | 2017-09-07 | 2017-12-08 | 湖南静芯微电子技术有限公司 | A kind of bidirectional thyristor electrostatic protection device of insertion without channel-type LDPMOS |
| CN108389891B (en) * | 2018-01-19 | 2019-03-01 | 湖南师范大学 | A kind of double grid grid-control silicon controlled rectifier (SCR) Electro-static Driven Comb device and preparation method thereof |
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