CN102034811A - Low-voltage SCR (Silicon Controlled Rectifier) structure for ESD (Electronic Static Discharge) protection of integrated circuit chip - Google Patents
Low-voltage SCR (Silicon Controlled Rectifier) structure for ESD (Electronic Static Discharge) protection of integrated circuit chip Download PDFInfo
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Abstract
The invention relates to a low-voltage SCR (Silicon Controlled Rectifier) structure for ESD (Electronic Static Discharge) protection of an integrated circuit chip, belonging to the technical field of electronics. The structure comprises two kinds of low-voltage SCR ESD protection devices, wherein the first kind of SCR ESD protection device integrates two N-well diodes and two NMOSs (N-channel Metal Oxide Semiconductors); the N-well diodes are connected between I/O (Input/Output) and a VDD (Virtual Device Driver); the NMOSs are connected between the VDD and VSS (Visual Source Safe); and the N-well diodes and the NMOSs form an SCR structure which provides ESD protection between PS and PD modes and VDD-VSS. The second kind of device integrates two P-well diodes and two PMOSs (P-channel Metal Oxide Semiconductors), wherein the P-well diodes are connected between the I/O and the VSS, and the PMOSs are connected between the VSS and the VDD, and the P-well diodes and the PMOSs jointly form an SCR structure which provides ESD protection between ND and NS modes and VDD-VSS. According to the invention, the chip has higher maintaining voltage and latch-up resistance effect during normal working and has lower triggering voltage and higher triggering speed during ESD; and the low-voltage SCR structure can effectively reduce the relative chip-occupying area of the protection devices and decrease parasitic capacitance at the same time of providing a plurality of modes of ESD protection functions and excellent ESD protection performance.
Description
Technical field
The invention belongs to electronic technology field; the static that relates to semiconductor integrated circuit chip discharges (ElectroStatic Discharge; abbreviate ESD as) the protective circuit designing technique; especially the single control circuit of a kind of usefulness of finger is controlled a plurality of protection devices; make the protection device ESD electric current of can releasing timely and effectively, can also save the shared silicon area of control circuit simultaneously.
Background technology
The static discharge phenomenon be semiconductor device or circuit make, produce, assemble, test, deposit, a kind of common phenomena in the process of carrying etc., the excessive charge that it brought, can in the extremely short time, import in the integrated circuit by the pin via integrated circuit, and the internal circuit of destruction integrated circuit.For head it off; usually can be when chip design in protective circuit of the other placement of I/O pin; this protective circuit must make internal circuit start before being damaged in the pulse of static discharge in advance, with the too high voltage of clamper promptly, and then reduces the destruction that the ESD phenomenon is caused.Yet along with reducing of integrated circuit technology characteristic size, it is also reducing the protective capacities of static discharge, makes cmos device become responsive more to static, and the situation of damaging because of ESD is more serious.And under equal electrostatic protection measure, advanced technology (as the lightly doped drain structure etc.) make device ESD protective capacities descend easily; Even if size of devices is strengthened, the ability of its anti-ESD can not be enhanced yet, and causes chip area to increase because device size increases simultaneously yet, and its ghost effect that brings is also more obvious.Therefore, how improving the anti-ESD ability of chip, and reduce the employed area of esd protection circuit as far as possible, has been the major issue that integrated circuit must be considered when design.
In CMOS technology, the most frequently used I/O mouth protective circuit is to be made of GGNMOS (Gate-Grounded NMOS) pipe of a pair of complementation and GDPMOS (Gate-VDD PMOS) pipe, as shown in Figure 1.When positive esd pulse (with respect to source and substrate terminal) takes place in the drain terminal of metal-oxide-semiconductor; avalanche breakdown will take place in the drain region of metal-oxide-semiconductor and substrate zone; therefore and produce avalanche current; this electric current will make between substrate zone and the source region and produce potential difference; when this potential difference during greater than the cut-in voltage of diode; the parasitic bipolar transistor (BJT) that leakage/substrate/source of being changed by MOS is formed is opened, and the ESD electric current of releasing thus, to play the protective effect to the chip internal circuit.But often need very big width owing to be used for the metal-oxide-semiconductor of esd protection; and in order to increase the uniformity that many finger-like metal-oxide-semiconductor is opened when ESD takes place; through regular meeting the drain terminal of MOS is expanded; promptly elongate distance (the Drain Contact to Gate Spacing of drain terminal contact hole to the grid edge; be called for short DCGS); with the steady resistance of increase drain terminal, but can bring very big parasitic capacitance like this, cause the load capacitance of I/O mouth to increase.
For reducing load capacitance and save chip area, should reduce the shared area of esd protection device that is in parallel with I/O, be issued to higher esd protection ability in the less area situation, can be with Fig. 2 or protective circuit shown in Figure 3.
In Fig. 2; diode with two small sizes is done protection; and between the other VDD-VSS of I/O pad, made a large-area power supply clamp circuit; make and betide between I/O and the VDD; or the ESD electric current between I/O and the VSS can be released by the power supply clamp circuit simultaneously respectively by the forward conduction of the diode between the diode between I/O and VDD or I/O and VSS.Though the load capacitance of this circuit I/O mouth is little, (for the forward conduction voltage of diode and power supply clamp circuit keep the voltage sum) may be bigger because its pressure drop when releasing the ESD electric current, so be difficult to obtain higher anti-ESD ability.
---SCR that low pressure triggers (Low-Voltage Trigger SCR is called for short LVTSCR)---replaces GGNMOS pipe and GDPMOS pipe among Fig. 1 in Fig. 3, to have used a kind of distressed structure of SCR (Silicon Controlled Rectifier).Because LVTSCR is under forward esd pulse (be that I/O PAD is a positive potential, VSS is a zero potential), in the device by N
+District, P trap, N
+Avalanche breakdown can take place in the metal-oxide-semiconductor that the district forms, and cause entozoic PNP of device and NPN transistor to be opened and the ESD electric current of releasing, and (be that I/O PAD is a negative potential at reverse esd pulse, VSS is a zero potential) under, it shows as the character of a forward-biased diode, therefore, for the ESD that occurs between I/O pin and the VSS pin, can directly release in the mode of SCR or forward-biased diode by the LVTSCR that is connected between I/O and VSS; For the ESD that occurs between I/O pin and the VDD pin, then can and be connected in the mode that the LVTSCR (in the mode of forward-biased diode or SCR) between VDD and the VSS is in series by this LVTSCR (in the mode of SCR or forward-biased diode) and release.Use the SCR device can obtain very strong anti-ESD ability, but when the chip operate as normal, because outside interference, false triggering may appear in SCR, causes latch-up (latch-up), causes the inefficacy of chip.For avoiding this phenomenon, often adopt to improve the means of keeping voltage of SCR, make and keep voltage and be higher than supply voltage, keep voltage and can increase the pressure drop on the LVTSCR when releasing the ESD electric current but improve, and and then increase power consumption, therefore tend to make the anti-ESD ability of device to reduce.This also is a design difficulty of making the esd protection device of SCR.
Summary of the invention
The invention provides a kind of low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection, can provide protection to the I/O port of integrated circuit (IC) chip, simultaneously to the protection based on NMOS structure and PMOS structure is provided between integrated circuit (IC) chip power rail VDD and the VSS based on PS pattern, PD pattern, NS pattern and the ND pattern of SCR structure; The present invention has the higher voltage of keeping when the integrated circuit (IC) chip operate as normal, anti-latch-up, and the trigger voltage when ESD takes place is lower, triggering speed is very fast; The present invention can also effectively reduce the relative area of the shared chip of protection device and reduce parasitic capacitance in the esd protection performance of esd protection function that various modes is provided and excellence.
A kind of low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection; as shown in Figure 4; comprise two types low pressure SCR esd protection device, the integrated circuit (IC) chip that described two types SCR esd protection device and they are protected is integrated on the same chip substrate.
Described first type low pressure SCR esd protection device comprises a N well region that is positioned at substrate surface, two P well regions, three P
+District and four N
+The district, described N well region is sandwiched between two P well regions; The one P well region crown center is a N
+The district, a P well region top is a P away from a side of N well region
+The district; The 2nd P well region crown center is the 2nd N
+The district, the 2nd P well region top is the 2nd P away from a side of N well region
+The district; N well region crown center is the 3rd P
+The district; The 3rd N
+The district is positioned at the zone that the first P well region top is connected with N well region top, the 4th N
+The district is positioned at the zone that the second P well region top is connected with N well region top; The one N
+District and the 3rd N
+P well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the P well region; The 2nd N
+District and the 4th N
+The 2nd P well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd P well region.The 3rd P
+The district links to each other with the I/O port of the integrated circuit (IC) chip of being protected by plain conductor, the 3rd, the 4th N
+The district links to each other first, second P by the VDD rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected
+District and first, second N
+District and first, second multi-crystal silicon area all link to each other by the VSS rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected.
Described second type low pressure SCR esd protection device comprises a P well region that is positioned at substrate surface, two N well regions, three N
+District and four P
+The district, described P well region is sandwiched between two N well regions; The one N well region crown center is a P
+The district, a N well region top is a N away from a side of P well region
+The district; The 2nd N well region crown center is the 2nd P
+The district, the 2nd N well region top is the 2nd N away from a side of P well region
+The district; P well region crown center is the 3rd N
+The district; The 3rd P
+The district is positioned at the zone that the first N well region top is connected with P well region top, the 4th P
+The district is positioned at the zone that the second N well region top is connected with P well region top; The one P
+District and the 3rd P
+N well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the N well region; The 2nd P
+District and the 4th P
+The 2nd N well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd N well region.The 3rd N
+The district links to each other with the I/O port of the integrated circuit (IC) chip of being protected by plain conductor, the 3rd, the 4th P
+The district links to each other first, second N by the VSS rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected
+District and first, second P
+District and first, second multi-crystal silicon area all link to each other by the VDD rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected.
Technique scheme also can have some deformation programs:
(1), as shown in Figure 5, on the basis of technical scheme shown in Figure 4, above the N well region of first type low pressure SCR esd protection device, increase by the 3rd, the 4th multi-crystal silicon area; Described the 3rd multi-crystal silicon area is positioned at the 3rd N
+District and the 3rd P
+N well region top between the district, described the 4th multi-crystal silicon area is positioned at the 4th N
+District and the 3rd P
+N well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the N well region; Described the 3rd, the 4th multi-crystal silicon area links to each other with the I/O port of the integrated circuit (IC) chip of being protected by plain conductor.Above the P well region of second type low pressure SCR esd protection device, increase by the 3rd, the 4th multi-crystal silicon area; Described the 3rd multi-crystal silicon area is positioned at the 3rd P
+District and the 3rd N
+P well region top between the district, described the 4th multi-crystal silicon area is positioned at the 4th P
+District and the 3rd N
+P well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the P well region; Described the 3rd, the 4th multi-crystal silicon area links to each other with the I/O port of the integrated circuit (IC) chip of being protected by plain conductor.
(2), as shown in Figure 6, on the basis of technical scheme shown in Figure 4, above the N well region of first type low pressure SCR esd protection device, increase by the 3rd, the 4th multi-crystal silicon area; Described the 3rd multi-crystal silicon area is positioned at the 3rd N
+District and the 3rd P
+N well region top between the district, described the 4th multi-crystal silicon area is positioned at the 4th N
+District and the 3rd P
+N well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the N well region; Described the 3rd, the 4th multi-crystal silicon area links to each other by the VDD rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected.Above the P well region of second type low pressure SCR esd protection device, increase by the 3rd, the 4th multi-crystal silicon area; Described the 3rd multi-crystal silicon area is positioned at the 3rd P
+District and the 3rd N
+P well region top between the district, described the 4th multi-crystal silicon area is positioned at the 4th P
+District and the 3rd N
+P well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the P well region; Described the 3rd, the 4th multi-crystal silicon area links to each other by the VSS rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected.
(3), as shown in Figure 7, on technical scheme basis shown in Figure 6, increase an electric capacity between the VDD rail in the power supply double track of first multi-crystal silicon area in first type low pressure SCR esd protection device and the integrated circuit (IC) chip of being protected, resistance of increase between the VSS rail in the power supply double track of first multi-crystal silicon area and the integrated circuit (IC) chip of being protected; Increase an electric capacity between the VDD rail in the power supply double track of second multi-crystal silicon area and the integrated circuit (IC) chip protected, resistance of increase between the VSS rail in the power supply double track of second multi-crystal silicon area and the integrated circuit (IC) chip of being protected.Increase an electric capacity between the VSS rail in the power supply double track of first multi-crystal silicon area in second type low pressure SCR esd protection device and the integrated circuit (IC) chip of being protected, resistance of increase between the VDD rail in the power supply double track of first multi-crystal silicon area and the integrated circuit (IC) chip of being protected; Increase an electric capacity between the VSS rail in the power supply double track of second multi-crystal silicon area and the integrated circuit (IC) chip protected, resistance of increase between the VDD rail in the power supply double track of second multi-crystal silicon area and the integrated circuit (IC) chip of being protected.
In the such scheme; described first type low pressure SCR esd protection device provides the PS pattern, and (I/O pin current potential is for just; VSS pin current potential is zero; all the other pins are all floating empty) and the PD pattern (I/O pin current potential is for just; VDD pin current potential is zero, and all the other pins are all floating empty) and VDD-VSS between the ESD protection.Described second type low pressure SCR esd protection device provides the ND pattern, and (I/O pin current potential is for negative; VDD pin current potential is zero; all the other pins are all floating empty) and NS pattern (I/O pin current potential is for negative, and VSS pin current potential is zero, and all the other pins are all floating empty) and VDD-VSS between ESD protect.
The low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection provided by the invention comprises two class low pressure SCR esd protection devices; first kind device is integrated 2 N n structures and 2 NMOS structures; wherein 2 N ns are connected between I/O mouth and the VDD; 2 NMOS are connected between VDD and the VSS, and N n and NMOS form the SCR structure jointly.First type low pressure SCR esd protection device provides the ESD between PS pattern, PD pattern and the VDD-VSS protection.The second class device is integrated 2 P n structures and 2 PMOS structures, wherein 2 P ns are connected between I/O mouth and the VSS, and 2 PMOS are connected between VSS and the VDD, and P n and PMOS form the SCR structure jointly.Second type low pressure SCRESD protection device provides the ESD between ND pattern, NS pattern and the VDD-VSS protection.
The low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection provided by the invention has following characteristics:
1, used the esd protection device of SCR structure as the I/O mouth, needed area is littler than conventional MOS structure, and therefore its parasitic capacitance of bringing also will reduce.
2, in the protection structure of I/O port, utilized parasitic capacitance between VDD rail and the VSS rail, made that the trigger voltage of device when ESD takes place is lower, triggering speed is faster, therefore to the protection better effects if of internal circuit by diode.
3, direct well region with I/O port place is connected to VDD rail or VSS rail in the protection structure of I/O port; make integrated circuit (IC) chip esd protection device when operate as normal trigger difficulty, therefore be difficult for causing false triggering by external interference and influencing the chip operate as normal.
4, the directly integrated MOS device that can be used for esd protection between VDD rail and the VSS rail in the protection structure of I/O fracture; and almost therefore do not increase area of chip, therefore can reduce or save special area as protection device between VDD rail and the VSS rail.And when a certain I/O fracture generation esd discharge, in other I/O mouths protection structures integrated this VDD rail and the protection device between the VSS rail auxiliary ESD current drain passage also can be provided.
Description of drawings
Fig. 1 is the schematic diagram of one of chip I/O mouth esd protection circuit commonly used.
Fig. 2 is two a schematic diagram of chip I/O mouth esd protection circuit commonly used.
Fig. 3 is three a schematic diagram of chip I/O mouth esd protection circuit commonly used.
Fig. 4 is first kind of low pressure SCR structure chart that is used for the integrated circuit (IC) chip esd protection provided by the invention.
Fig. 5 is second kind of low pressure SCR structure chart that is used for the integrated circuit (IC) chip esd protection provided by the invention.
Fig. 6 is used for the low pressure SCR structure chart of integrated circuit (IC) chip esd protection for provided by the invention the third.
Fig. 7 is the 4th a kind of low pressure SCR structure chart that is used for the integrated circuit (IC) chip esd protection provided by the invention.
Fig. 8 is the current drain path schematic diagram of first type of protection device of low pressure SCR structure under PS pattern esd pulse (the I/O mouth is to the positive pulse of VSS) that is used for the integrated circuit (IC) chip esd protection provided by the invention.
Fig. 9 is the equivalent circuit diagram of Fig. 8.
Figure 10 is the 50 microns wide simulation curve of first type of protection device when transient state takes place ESD among 50 microns wide common LVTSCR device and the present invention.
Figure 11 is the current drain path schematic diagram of first type of protection device of low pressure SCR structure under PD pattern esd pulse (the I/O mouth is to the positive pulse of VDD) that is used for the integrated circuit (IC) chip esd protection provided by the invention.
Figure 12 is the current drain path schematic diagram of second type of protection device of low pressure SCR structure under ND pattern esd pulse (the I/O mouth is to the negative pulse of VDD) that is used for the integrated circuit (IC) chip esd protection provided by the invention.
Figure 13 is the equivalent schematic diagram of Figure 12.
Figure 14 is the current drain path schematic diagram of second type of protection device of low pressure SCR structure under NS pattern esd pulse (the I/O mouth is to the negative pulse of VSS) that is used for the integrated circuit (IC) chip esd protection provided by the invention.
Embodiment
In order to make technical problem to be solved by this invention, technical scheme and good effect clearer, the present invention is further elaborated below in conjunction with accompanying drawing.
Embodiment one
A kind of low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection; as shown in Figure 4; comprise two types low pressure SCR esd protection device, the integrated circuit (IC) chip that described two types SCR esd protection device and they are protected is integrated on the same chip substrate.
Described first type low pressure SCR esd protection device comprises a N well region that is positioned at substrate surface, two P well regions, three P
+District and four N
+The district, described N well region is sandwiched between two P well regions; The one P well region crown center is a N
+The district, a P well region top is a P away from a side of N well region
+The district; The 2nd P well region crown center is the 2nd N
+The district, the 2nd P well region top is the 2nd P away from a side of N well region
+The district; N well region crown center is the 3rd P
+The district; The 3rd N
+The district is positioned at the zone that the first P well region top is connected with N well region top, the 4th N
+The district is positioned at the zone that the second P well region top is connected with N well region top; The one N
+District and the 3rd N
+P well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the P well region; The 2nd N
+District and the 4th N
+The 2nd P well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd P well region.The 3rd P
+The district links to each other with the I/O port of the integrated circuit (IC) chip of being protected by plain conductor, the 3rd, the 4th N
+The district links to each other first, second P by the VDD rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected
+District and first, second N
+District and first, second multi-crystal silicon area all link to each other by the VSS rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected.
Described second type low pressure SCR esd protection device comprises a P well region that is positioned at substrate surface, two N well regions, three N
+District and four P
+The district, described P well region is sandwiched between two N well regions; The one N well region crown center is a P
+The district, a N well region top is a N away from a side of P well region
+The district; The 2nd N well region crown center is the 2nd P
+The district, the 2nd N well region top is the 2nd N away from a side of P well region
+The district; P well region crown center is the 3rd N
+The district; The 3rd P
+The district is positioned at the zone that the first N well region top is connected with P well region top, the 4th P
+The district is positioned at the zone that the second N well region top is connected with P well region top; The one P
+District and the 3rd P
+N well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the N well region; The 2nd P
+District and the 4th P
+The 2nd N well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd N well region.The 3rd N
+The district links to each other with the I/O port of the integrated circuit (IC) chip of being protected by plain conductor, the 3rd, the 4th P
+The district links to each other first, second N by the VSS rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected
+District and first, second P
+District and first, second multi-crystal silicon area all link to each other by the VDD rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected.
Embodiment two
As shown in Figure 5, on the basis of technical scheme shown in Figure 4, above the N well region of first type low pressure SCR esd protection device, increase by the 3rd, the 4th multi-crystal silicon area; Described the 3rd multi-crystal silicon area is positioned at the 3rd N
+District and the 3rd P
+N well region top between the district, described the 4th multi-crystal silicon area is positioned at the 4th N
+District and the 3rd P
+N well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the N well region; Described the 3rd, the 4th multi-crystal silicon area links to each other with the I/O port of the integrated circuit (IC) chip of being protected by plain conductor.Above the P well region of second type low pressure SCR esd protection device, increase by the 3rd, the 4th multi-crystal silicon area; Described the 3rd multi-crystal silicon area is positioned at the 3rd P
+District and the 3rd N
+P well region top between the district, described the 4th multi-crystal silicon area is positioned at the 4th P
+District and the 3rd N
+P well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the P well region; Described the 3rd, the 4th multi-crystal silicon area links to each other with the I/O port of the integrated circuit (IC) chip of being protected by plain conductor.
Embodiment three
As shown in Figure 6, on the basis of technical scheme shown in Figure 4, above the N well region of first type low pressure SCR esd protection device, increase by the 3rd, the 4th multi-crystal silicon area; Described the 3rd multi-crystal silicon area is positioned at the 3rd N
+District and the 3rd P
+N well region top between the district, described the 4th multi-crystal silicon area is positioned at the 4th N
+District and the 3rd P
+N well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the N well region; Described the 3rd, the 4th multi-crystal silicon area links to each other by the VDD rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected.Above the P well region of second type low pressure SCR esd protection device, increase by the 3rd, the 4th multi-crystal silicon area; Described the 3rd multi-crystal silicon area is positioned at the 3rd P
+District and the 3rd N
+P well region top between the district, described the 4th multi-crystal silicon area is positioned at the 4th P
+District and the 3rd N
+P well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the P well region; Described the 3rd, the 4th multi-crystal silicon area links to each other by the VSS rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected.
Embodiment four
As shown in Figure 7, on technical scheme basis shown in Figure 6, increase an electric capacity between the VDD rail in the power supply double track of first multi-crystal silicon area in first type low pressure SCR esd protection device and the integrated circuit (IC) chip of being protected, resistance of increase between the VSS rail in the power supply double track of first multi-crystal silicon area and the integrated circuit (IC) chip of being protected; Increase an electric capacity between the VDD rail in the power supply double track of second multi-crystal silicon area and the integrated circuit (IC) chip protected, resistance of increase between the VSS rail in the power supply double track of second multi-crystal silicon area and the integrated circuit (IC) chip of being protected.Increase an electric capacity between the VSS rail in the power supply double track of first multi-crystal silicon area in second type low pressure SCR esd protection device and the integrated circuit (IC) chip of being protected, resistance of increase between the VDD rail in the power supply double track of first multi-crystal silicon area and the integrated circuit (IC) chip of being protected; Increase an electric capacity between the VSS rail in the power supply double track of second multi-crystal silicon area and the integrated circuit (IC) chip protected, resistance of increase between the VDD rail in the power supply double track of second multi-crystal silicon area and the integrated circuit (IC) chip of being protected.
In the such scheme; described first type low pressure SCR esd protection device provides the PS pattern, and (I/O pin current potential is for just; VSS pin current potential is zero; all the other pins are all floating empty) and the PD pattern (I/O pin current potential is for just; VDD pin current potential is zero, and all the other pins are all floating empty) and VDD-VSS between the ESD protection.Described second type low pressure SCR esd protection device provides the ND pattern, and (I/O pin current potential is for negative; VDD pin current potential is zero; all the other pins are all floating empty) and NS pattern (I/O pin current potential is for negative, and VSS pin current potential is zero, and all the other pins are all floating empty) and VDD-VSS between ESD protect.
Be that example is carried out operation principle explanation (operation principle of other embodiments is basic identical) to the low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection provided by the invention with technical scheme shown in Figure 6 below.
Under the esd pulse of PS pattern, the current drain path of first type low pressure SCR esd protection device as shown in Figure 8.Parasitic BJT device Q1 is (by N well region, the 3rd N
+District, a P well region and a N
+The district forms) with Q2 (by the 3rd P
+District, N well region, the 3rd N
+A district and a P well region) form the SCR structure, capacitor C is the parasitic capacitance between the VDD-VSS rail.Under the ESD of PS pattern condition, the equivalent schematic diagram of first type low pressure SCR esd protection device as shown in Figure 9, the NMOS structure in the SCR structure can puncture, breakdown potential fail to be convened for lack of a quorum make BJT device Q1 base-emitter junction (by a P well region and a N
+The district forms) positively biased, thus make the Q1 conducting; Simultaneously, because the VDD rail is floating empty under the PS pattern, therefore, the voltage of I/O mouth will launch by Q2-and Ji ties (by the 3rd P
+District, N well region and the 3rd N
+The district forms) diode pair parasitic capacitance C charging, thus the base current of formation Q2 is opened Q2.And the collector current of Q2 will provide electric current for the base stage of Q1, and the collector current of Q1 will provide electric current for the base stage of Q2, and final SCR structure conducting is with the ESD electric current of releasing.The conducting that general N type LVTSCR then just punctures the Q1 that causes by NMOS triggers, and therefore, first type the opening speed of low pressure SCR esd protection device when ESD takes place can be faster than common LVTSCR.The width of supposing device is 50um; at low pressure SCR esd protection device provided by the present invention first type; with the capacitance simulation VDD rail of 1pF and the parasitic capacitance between the VSS rail (in fact this parasitic capacitance will much larger than 1pF); as shown in figure 10; the due to voltage spikes of low pressure SCR esd protection device provided by the present invention first type is lower than common LVTSCR device, therefore can better protect internal circuit.In addition, different with General N type LVTSCR is, Q2 does not draw the trap resistance from the base to the emitter region, so the emitter region injection efficiency of Q2 can be higher, and the clamp voltage of SCR structure can be lower, and therefore reaches better esd protection effect.After this SCR opens; if the ESD voltage between this moment I/O port and the VSS is still very high, then the ESD electric current can be by other have adopted the NMOS structure and the PMOS structure that are connected between VDD rail and the VSS rail in the SCR structure of I/O port of same protection structure to release in the chip.In Fig. 9; in protected integrated circuit (IC) chip, there be N I/O port to use low pressure SCRESD protection device provided by the invention first type; in this SCR the contained NMOS structure; the extra NMOS number of structures that is connected in like this between VDD rail and the VSS rail is individual for (N-1), and the PMOS number of structures is N.Therefore when a plurality of I/O mouths had all used this protection structure, the anti-ESD ability of chip will be enhanced.Current path among Fig. 9 is described as follows:
Path 1: through the path of releasing of first type the SCR structure of low pressure SCR esd protection device own;
Path 2: the path of releasing of additionally passing through the PMOS structure;
Path 3: the path of releasing of additionally passing through the NMOS structure;
Parasitic capacitance C is to the trigger current path of SCR between path 4:VDD rail and the VSS rail.
Under the esd pulse of PD pattern, the current drain path of low pressure SCR esd protection device provided by the present invention first type as shown in figure 11.The ESD electric current from the I/O port through diode (by the 3rd P
+District, N well region and the 3rd N
+The district forms) release to the VDD rail.
For the ESD phenomenon that betides between VDD and the VSS, all can release by the NMOS structure in first type the low pressure SCR esd protection device.Therefore, low pressure SCR esd protection device provided by the present invention first type also can be for providing ESD protection when the ESD protection is provided for the I/O port between VDD rail and the VSS rail.
When protected integrated circuit (IC) chip operate as normal, the current potential of VSS rail is zero, and the VDD rail connects power supply, and the current potential of I/O port is between the current potential of VDD rail and VSS rail.VSS rail first, second P by being attached thereto
+The district makes first, second P well region be biased to zero potential respectively; the N well region then is biased in VDD rail current potential by the 3rd, the 4th N+ district that links to each other with the VDD rail; therefore, first type low pressure SCR esd protection device equivalence this moment for be connected in the NMOS structure between VDD rail and the VSS rail and be connected in the I/O port and the VDD rail between P
+/ N n.Even since noise cause the I/O port current potential a little more than VDD rail current potential, the electric current of generation also can pass through this P
+/ N n is released to the VDD rail, thus limiting carrier to the injection in tagma, when making operate as normal the triggering of this SCR structure very difficult, also promptly the anti-false triggering effect of first type low pressure SCR esd protection device can be better than common LVTSCR.In addition, for the I/O port, the parasitic capacitance that first type low pressure SCR esd protection device is introduced also will be only caused by diode, and therefore, the circuit of this structure in can image pattern 2 equally reaches the requirement of little parasitic capacitance.
Under the esd pulse of ND pattern, the current drain path of second type low pressure SCR esd protection device as shown in figure 12.Parasitic BJT device Q3 is (by P well region, the 3rd P in second type the low pressure SCRESD protection device
+District, a N well region and a P
+The district forms) with Q4 (by the 3rd N
+District, P well region, the 3rd P
+A district and a N well region are formed) form the SCR structure, capacitor C is the parasitic capacitance between VDD rail and the VSS rail.Under the ESD of ND pattern condition, the equivalent schematic diagram of second type low pressure SCR esd protection device as shown in figure 13.PMOS structure in this SCR structure can puncture, and the breakdown potential emission-Ji that makes Q3 that fails to be convened for lack of a quorum ties (by a P
+A district and a N well region are formed) positively biased, thus make the Q3 conducting; Simultaneously, because the VSS rail is floating empty under the ND pattern, therefore, the voltage of I/O port will be by Q4 base-emitter junction (by the 3rd P
+District, P well region and the 3rd N
+The district forms) diode pair parasitic capacitance C charging, thus the base current of formation Q4 is opened Q4.And the collector current of Q4 will provide electric current for the base stage of Q3, and the collector current of Q3 will provide electric current for the base stage of Q4, and final SCR structure conducting is with the ESD electric current of releasing.The conducting that general P type LVTSCR then just punctures the Q1 that causes by the PMOS structure triggers, and therefore, the opening speed of this device when ESD takes place can be faster than common LVTSCR.In addition, different with general P type LVTSCR is, Q4 does not draw the trap resistance from the base to the emitter region, so the emitter region injection efficiency of Q4 can be higher, and the clamp voltage of SCR structure can be lower, and therefore reaches better esd protection effect.After this SCR opens; if the ESD voltage between this moment VDD rail and the I/O port is still very high, then the ESD electric current can be by other have adopted the NMOS structure and the PMOS structure that are connected between VDD rail and the VSS rail in second type the low pressure SCR esd protection device of I/O port of same protection structure to release in the protected integrated circuit (IC) chip.In Figure 13; when having N I/O port to use second type low pressure SCR esd protection device in the protected integrated circuit (IC) chip; except that the contained PMOS structure of this low pressure SCR esd protection device of second type itself; the extra PMOS number of structures that is connected in like this between VDD rail and the VSS rail is individual for (N-1), and NMOS quantity is N.Therefore when a plurality of I/O ports had all used second type low pressure SCR esd protection device, the anti-ESD ability of protected integrated circuit (IC) chip will be enhanced.Current path among Figure 13 is described as follows:
Path 5: through the path of releasing of second type the SCR of low pressure SCR esd protection device own;
Path 6: the path of releasing of additionally passing through the PMOS structure;
Path 7: the path of releasing of additionally passing through the NMOS structure;
Parasitic capacitance C is to the trigger current path of SCR between path 8:VDD rail and VSS rail.
Under the esd pulse of NS pattern, the current drain path of second type low pressure SCR esd protection device as shown in figure 14.The ESD electric current from the VSS rail through diode (by the 3rd P
+District, P well region and the 3rd N
+The district forms) release to the I/O port.
For the ESD phenomenon that betides between VDD and the VSS, all can release by the PMOS structure in second type the low pressure SCR esd protection device.Therefore, second type low pressure SCR esd protection device is when providing the ESD protection, also for providing ESD protection between VDD rail and the VSS rail for the I/O port.
When protected integrated circuit (IC) chip operate as normal, the current potential of VSS rail is zero, and VDD connects power supply, and the current potential of I/O port is between the current potential of VDD rail and VSS rail.VDD rail first, second N by being attached thereto
+The district makes first, second N well region be biased to zero potential respectively, and the P well region is then by the 3rd, the 4th P that links to each other with the VSS rail
+The district is biased in VSS rail current potential, therefore, second type low pressure SCR esd protection device equivalence this moment for be connected in the PMOS structure between VDD rail and the VSS rail and be connected in the I/O port and the VSS rail between P trap/N
+Diode.Even since noise cause the I/O port current potential a little less than VSS rail current potential, the electric current of generation also can pass through this P trap/N
+Diode pair VSS rail is released, thus limiting carrier to the injection in tagma, when making operate as normal the triggering of this SCR very difficult, also promptly the anti-false triggering effect of second type low pressure SCRESD protection device can be better than common LVTSCR.In addition, for the I/O port, the parasitic capacitance that second type low pressure SCR esd protection device is introduced also will be only caused by diode, and therefore, the circuit of this structure in can image pattern 2 equally reaches the requirement of little parasitic capacitance.
Of particular note; because the low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection provided by the invention is a symmetrical structure; only described the operation principle of half structure in the description of above-mentioned operation principle process, the operation principle of second half structure is the same.
In sum, the low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection provided by the invention can be the ESD protection that the I/O port provides PS, PD, NS and four kinds of patterns of ND, simultaneously again can be for the protection of GGNMOS and GDPMOS is provided between VDD rail and VSS rail.If there are a plurality of ports to use the low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection provided by the invention in the integrated circuit (IC) chip, then protected integrated circuit (IC) chip just can provide more intense anti-ESD ability under the situation that does not have special VDD rail and VSS rail protective circuit.Therefore, the area utilization of this protection structure is very high.
More than be the specific descriptions of technical scheme shown in Figure 6, the operation principle of other three concrete technical schemes is the same substantially, does not repeat them here.Therefore technical scheme shown in Figure 4 has lacked two grid-control electrodes owing to there is not the 3rd, the 4th multi-crystal silicon area, and comparatively speaking, the triggering speed of this technical scheme decreases, and other performances do not have influence substantially.Technical scheme shown in Figure 5 is compared with technical scheme shown in Figure 6, the just variation of annexation, and its esd protection ability is essentially identical.The technical scheme of Fig. 7 shown in being then by add a RC circuit between VDD rail and VSS rail, improves the triggering speed of MOS structure by the voltage coupling of RC circuit, thereby has the speed that triggers faster, and other performances not have to influence substantially.
Claims (5)
1. a low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection comprises two types low pressure SCR esd protection device, and the integrated circuit (IC) chip that described two types SCR esd protection device and they are protected is integrated on the same chip substrate;
Described first type low pressure SCR esd protection device comprises a N well region that is positioned at substrate surface, two P well regions, three P
+District and four N
+The district, described N well region is sandwiched between two P well regions; The one P well region crown center is a N
+The district, a P well region top is a P away from a side of N well region
+The district; The 2nd P well region crown center is the 2nd N
+The district, the 2nd P well region top is the 2nd P away from a side of N well region
+The district; N well region crown center is the 3rd P
+The district; The 3rd N
+The district is positioned at the zone that the first P well region top is connected with N well region top, the 4th N
+The district is positioned at the zone that the second P well region top is connected with N well region top; The one N
+District and the 3rd N
+P well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the P well region; The 2nd N
+District and the 4th N
+The 2nd P well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd P well region;
The 3rd P
+The district links to each other with the I/O port of the integrated circuit (IC) chip of being protected by plain conductor, the 3rd, the 4th N
+The district links to each other first, second P by the VDD rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected
+District and first, second N
+District and first, second multi-crystal silicon area all link to each other by the VSS rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected;
Described second type low pressure SCR esd protection device comprises a P well region that is positioned at substrate surface, two N well regions, three N
+District and four P
+The district, described P well region is sandwiched between two N well regions; The one N well region crown center is a P
+The district, a N well region top is a N away from a side of P well region
+The district; The 2nd N well region crown center is the 2nd P
+The district, the 2nd N well region top is the 2nd N away from a side of P well region
+The district; P well region crown center is the 3rd N
+The district; The 3rd P
+The district is positioned at the zone that the first N well region top is connected with P well region top, the 4th P
+The district is positioned at the zone that the second N well region top is connected with P well region top; The one P
+District and the 3rd P
+N well region top between the district has first multi-crystal silicon area, has insulating barrier between first multi-crystal silicon area and the N well region; The 2nd P
+District and the 4th P
+The 2nd N well region top between the district has second multi-crystal silicon area, has insulating barrier between second multi-crystal silicon area and the 2nd N well region;
The 3rd N
+The district links to each other with the I/O port of the integrated circuit (IC) chip of being protected by plain conductor, the 3rd, the 4th P
+The district links to each other first, second N by the VSS rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected
+District and first, second P
+District and first, second multi-crystal silicon area all link to each other by the VDD rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected.
2. the low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection according to claim 1 is characterized in that: described first type low pressure SCR esd protection device also has the 3rd, the 4th multi-crystal silicon area: described the 3rd multi-crystal silicon area is positioned at the 3rd N
+District and the 3rd P
+N well region top between the district, described the 4th multi-crystal silicon area is positioned at the 4th N
+District and the 3rd P
+N well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the N well region; Described the 3rd, the 4th multi-crystal silicon area links to each other with the I/O port of the integrated circuit (IC) chip of being protected by plain conductor;
Described second type low pressure SCR esd protection device also has the 3rd, the 4th multi-crystal silicon area: described the 3rd multi-crystal silicon area is positioned at the 3rd P
+District and the 3rd N
+P well region top between the district, described the 4th multi-crystal silicon area is positioned at the 4th P
+District and the 3rd N
+P well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the P well region; Described the 3rd, the 4th multi-crystal silicon area links to each other with the I/O port of the integrated circuit (IC) chip of being protected by plain conductor.
3. the low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection according to claim 1 is characterized in that: described first type low pressure SCR esd protection device also has the 3rd, the 4th multi-crystal silicon area: described the 3rd multi-crystal silicon area is positioned at the 3rd N
+District and the 3rd P
+N well region top between the district, described the 4th multi-crystal silicon area is positioned at the 4th N
+District and the 3rd P
+N well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the N well region; Described the 3rd, the 4th multi-crystal silicon area links to each other by the VDD rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected;
Described second type low pressure SCR esd protection device also has the 3rd, the 4th multi-crystal silicon area: described the 3rd multi-crystal silicon area is positioned at the 3rd P
+District and the 3rd N
+P well region top between the district, described the 4th multi-crystal silicon area is positioned at the 4th P
+District and the 3rd N
+P well region top between the district has insulating barrier between the 3rd, the 4th multi-crystal silicon area and the P well region; Described the 3rd, the 4th multi-crystal silicon area links to each other by the VSS rail in the power supply double track of plain conductor and the integrated circuit (IC) chip of being protected.
4. the low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection according to claim 3, it is characterized in that: in the described first type low pressure SCR esd protection device, also have an electric capacity between the VDD rail in the power supply double track of first multi-crystal silicon area and the integrated circuit (IC) chip protected, also have a resistance between the VSS rail in the power supply double track of first multi-crystal silicon area and the integrated circuit (IC) chip protected; Also have an electric capacity between the VDD rail in the power supply double track of second multi-crystal silicon area and the integrated circuit (IC) chip protected, also have a resistance between the VSS rail in the power supply double track of second multi-crystal silicon area and the integrated circuit (IC) chip protected;
In the described second type low pressure SCR esd protection device, also have an electric capacity between the VSS rail in the power supply double track of first multi-crystal silicon area and the integrated circuit (IC) chip protected, also have a resistance between the VDD rail in the power supply double track of first multi-crystal silicon area and the integrated circuit (IC) chip protected; Also have an electric capacity between the VSS rail in the power supply double track of second multi-crystal silicon area and the integrated circuit (IC) chip protected, also have a resistance between the VDD rail in the power supply double track of second multi-crystal silicon area and the integrated circuit (IC) chip protected.
5. according to the arbitrary low pressure SCR structure that is used for the integrated circuit (IC) chip esd protection of claim 1-4, it is characterized in that described substrate is P type substrate, N type substrate or SOI substrate.
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Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102208412A (en) * | 2011-05-19 | 2011-10-05 | 电子科技大学 | SCR structure used for ESD protection of integrated circuit output stage |
| CN102544001A (en) * | 2012-03-15 | 2012-07-04 | 电子科技大学 | SCR (Silicon Controlled Rectifier) structure for providing ESD ( Electro-Static discharge) protection for I/O (Input/Output) port of integrated circuit under all modes |
| CN102569295A (en) * | 2012-03-09 | 2012-07-11 | 浙江大学 | Bidirectional thyristor device based on capacitor-assisted trigger |
| CN102769282A (en) * | 2011-05-04 | 2012-11-07 | 曾传滨 | Electro static discharge protective circuit for circuit board interface |
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| CN111370401A (en) * | 2020-02-12 | 2020-07-03 | 中国科学院微电子研究所 | ESD protection structure, integrated circuit and electronic equipment |
| CN114709210A (en) * | 2022-06-07 | 2022-07-05 | 深圳市晶扬电子有限公司 | Low clamping voltage electrostatic protection device suitable for nanoscale FinFET (field effect transistor) process |
| WO2023020020A1 (en) * | 2021-08-20 | 2023-02-23 | 长鑫存储技术有限公司 | Electro-static protection device and electronic apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101257005A (en) * | 2007-03-01 | 2008-09-03 | 和舰科技(苏州)有限公司 | Silicium control rectifier protecting electro-static discharge |
| US20090294855A1 (en) * | 2008-05-28 | 2009-12-03 | Dong-Ju Lim | Electrostatic Discharge Protection Device |
| CN101728428A (en) * | 2008-10-10 | 2010-06-09 | 和舰科技(苏州)有限公司 | Silicon controlled rectifier and manufacturing method thereof |
-
2010
- 2010-09-21 CN CN 201010289473 patent/CN102034811B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101257005A (en) * | 2007-03-01 | 2008-09-03 | 和舰科技(苏州)有限公司 | Silicium control rectifier protecting electro-static discharge |
| US20090294855A1 (en) * | 2008-05-28 | 2009-12-03 | Dong-Ju Lim | Electrostatic Discharge Protection Device |
| CN101728428A (en) * | 2008-10-10 | 2010-06-09 | 和舰科技(苏州)有限公司 | Silicon controlled rectifier and manufacturing method thereof |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769282A (en) * | 2011-05-04 | 2012-11-07 | 曾传滨 | Electro static discharge protective circuit for circuit board interface |
| CN102769282B (en) * | 2011-05-04 | 2015-01-07 | 北京中科新微特科技开发股份有限公司 | Electro static discharge protective circuit for circuit board interface |
| CN102208412B (en) * | 2011-05-19 | 2012-11-07 | 电子科技大学 | SCR structure used for ESD protection of integrated circuit output stage |
| CN102208412A (en) * | 2011-05-19 | 2011-10-05 | 电子科技大学 | SCR structure used for ESD protection of integrated circuit output stage |
| CN102569295A (en) * | 2012-03-09 | 2012-07-11 | 浙江大学 | Bidirectional thyristor device based on capacitor-assisted trigger |
| CN102544001A (en) * | 2012-03-15 | 2012-07-04 | 电子科技大学 | SCR (Silicon Controlled Rectifier) structure for providing ESD ( Electro-Static discharge) protection for I/O (Input/Output) port of integrated circuit under all modes |
| CN103414174A (en) * | 2013-08-21 | 2013-11-27 | 成都成电光信科技有限责任公司 | Electrostatic protection type interface circuit |
| CN103414174B (en) * | 2013-08-21 | 2016-02-03 | 成都成电光信科技有限责任公司 | Electrostatic protection type interface circuit |
| CN106876388B (en) * | 2017-03-09 | 2019-07-30 | 东南大学 | A kind of ghyristor circuit for prevention at radio-frequency port electrostatic discharge protective |
| CN106876388A (en) * | 2017-03-09 | 2017-06-20 | 东南大学 | A kind of ghyristor circuit for prevention at radio-frequency port electrostatic discharge protective |
| CN109427763A (en) * | 2017-08-22 | 2019-03-05 | 奇景光电股份有限公司 | Electrostatic discharge protective circuit |
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| CN109103184A (en) * | 2018-08-24 | 2018-12-28 | 电子科技大学 | Two-way high maintenance electric current ESD protection device |
| CN109407748A (en) * | 2018-11-20 | 2019-03-01 | 深圳讯达微电子科技有限公司 | A kind of ESD protective system of low pressure difference linear voltage regulator |
| CN109742070A (en) * | 2018-12-21 | 2019-05-10 | 中国电子科技集团公司第四十八研究所 | A kind of silicon-controlled electrostatic protection device of FDSOI |
| CN111370401A (en) * | 2020-02-12 | 2020-07-03 | 中国科学院微电子研究所 | ESD protection structure, integrated circuit and electronic equipment |
| CN111370401B (en) * | 2020-02-12 | 2023-01-17 | 中国科学院微电子研究所 | ESD protection structure, integrated circuit and electronic equipment |
| WO2023020020A1 (en) * | 2021-08-20 | 2023-02-23 | 长鑫存储技术有限公司 | Electro-static protection device and electronic apparatus |
| CN114709210A (en) * | 2022-06-07 | 2022-07-05 | 深圳市晶扬电子有限公司 | Low clamping voltage electrostatic protection device suitable for nanoscale FinFET (field effect transistor) process |
| CN114709210B (en) * | 2022-06-07 | 2022-09-02 | 深圳市晶扬电子有限公司 | Low clamping voltage electrostatic protection device suitable for nanoscale FinFET (field effect transistor) process |
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| CN102034811B (en) | 2012-07-04 |
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