WO2023020020A1 - Electro-static protection device and electronic apparatus - Google Patents

Abstract

Disclosed in the embodiments of the present disclosure are an electro-static protection device and an electronic apparatus. The electro-static protection device comprises: a P-type substrate; an N-well, which is located in the P-type substrate; a PMOS transistor, wherein the PMOS transistor comprises a gate electrode, and a first P-type heavily doped region and a second P-type heavily doped region, which are located on two sides of the gate electrode; and a pulse monitoring unit, wherein the gate electrode of the PMOS transistor is controlled by the pulse monitoring unit. The first P-type heavily doped region is connected between the P-type substrate and the N-well in a spanning manner; the P-type substrate is connected to a first bonding pad; and the second P-type heavily doped region is connected to a second bonding pad.

Description

An electrostatic protection device and electronic device

Cross References to Related Applications

This disclosure is based on the Chinese patent application with the application number 202110961092.X, the filing date is August 20, 2021, and the title of the invention is "an electrostatic protection device and electronic device", and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated by reference into this disclosure.

technical field

The present disclosure relates to the field of semiconductor integrated circuits, in particular to an electrostatic protection device and an electronic device.

Background technique

In all links of integrated circuits, charge accumulation may occur. Under certain conditions, the charge will be transferred, and the instantaneous large current may exceed the critical value of the device and cause the chip to burn. Statistical data show that: Electro Static Discharge (ESD) is the main reason for the failure of integrated circuits, especially in power integrated circuits. Therefore, electrostatic discharge has become the most important issue for designers.

Contents of the invention

In view of this, embodiments of the present disclosure provide an electrostatic protection device and an electronic device.

According to a first aspect of an embodiment of the present disclosure, there is provided an electrostatic protection device, including:

P-type substrate;

N well, located in the P-type substrate;

A PMOS transistor, the PMOS transistor includes a gate and a first P-type heavily doped region and a second P-type heavily doped region located on both sides of the gate;

A pulse monitoring unit, the gate of the PMOS transistor is controlled by the pulse monitoring unit; wherein,

The first P-type heavily doped region spans between the P-type substrate and the N well, the P-type substrate is connected to the first pad, and the second P-type heavily doped region is connected to the second pad.

In some embodiments, also include:

a first N-type heavily doped region, a second N-type heavily doped region, a third N-type heavily doped region, and a third P-type heavily doped region;

The first N-type heavily doped region, the third P-type heavily doped region and the second N-type heavily doped region are located in the P-type substrate;

The third N-type heavily doped region and the second P-type heavily doped region are located in the N well.

In some embodiments, the third P-type heavily doped region and the second N-type heavily doped region are connected to the first pad.

In some embodiments, the first N-type heavily doped region is connected to the second pad.

In some embodiments, also include:

A third pad; the third heavily doped N-type region is connected to the third pad.

In some embodiments, the second P-type heavily doped region, the N well and the P-type substrate form a parasitic PNP transistor;

The N well, the P-type substrate and the second N-type heavily doped region form a parasitic NPN transistor.

In some embodiments, the first N-type heavily doped region and the third P-type heavily doped region form a first parasitic diode;

The third P-type heavily doped region and the third N-type heavily doped region form a second parasitic diode;

The second P-type heavily doped region and the third N-type heavily doped region form a third parasitic diode.

In some embodiments, the pulse monitoring unit includes a resistor R and a capacitor C;

The gate of the PMOS transistor is connected to the third pad through a resistor R, and connected to the first pad through a capacitor C.

In some embodiments, the second P-type heavily doped region, the parasitic PNP transistor, the parasitic NPN transistor, and the second N-type heavily doped region form a connection from the second pad to the A first electrostatic current discharge path of the first pad.

In some embodiments, the third P-type heavily doped region, the first parasitic diode, and the first N-type heavily doped region form a connection from the first pad to the second pad. The second electrostatic current discharge path.

In some embodiments, the second P-type heavily doped region, the third parasitic diode, and the third N-type heavily doped region form a connection from the second bonding pad to the third bonding pad. The third electrostatic current discharge path.

In some embodiments, the third P-type heavily doped region, the second parasitic diode, and the third N-type heavily doped region form a connection from the first pad to the third pad. The fourth electrostatic current discharge path.

In some embodiments, the first pad is a ground pad; the second pad is an input/output pad; and the third pad is a power pad.

According to a second aspect of the embodiments of the present disclosure, an electronic device is provided, the electronic device includes the electrostatic protection device described in any one of the above embodiments and an electronic component connected to the electrostatic protection device.

In the embodiment of the present disclosure, by adding the pulse monitoring unit and the PMOS tube controlled by the pulse monitoring unit, when static electricity occurs, the PMOS tube controlled by the pulse monitoring unit will be turned on, thereby triggering the connection from the second pad to the first The electrostatic current discharge path of the pad completes the discharge of electrostatic current. Moreover, the electrostatic protection device in the present disclosure has low trigger voltage and low leakage, which improves the electrostatic protection capability.

Description of drawings

Fig. 1 is a conventional electrostatic protection circuit in the related art;

Fig. 2 is a conventional SCR electrostatic protection IV characteristic diagram in the related art;

Fig. 3 is the ESD design window diagram in the related art;

FIG. 4 is a layout of an electrostatic protection device provided by an embodiment of the present disclosure;

5 is a schematic cross-sectional view of an electrostatic protection device provided by an embodiment of the present disclosure;

6 is a schematic diagram of an equivalent circuit of an electrostatic protection device provided by an embodiment of the present disclosure;

FIG. 7 is a schematic cross-sectional view of an electrostatic protection device provided by another embodiment of the present disclosure.

Explanation of reference signs:

13', 11-the first P-type heavily doped region; 12-the second P-type heavily doped region; 11', 13-the first N-type heavily doped region; 14-the third P-type heavily doped region; 12', 15-the second N-type heavily doped region; 14', 16-the third N-type heavily doped region;

21', 21-P type substrate; 22', 22-N well;

30', 30-gate; 31', 31-oxide layer; 32', 32-polysilicon layer; 33', 33-tungsten layer;

40', 40-pulse monitoring unit;

51 - the first parasitic diode; 52 - the second parasitic diode; 53 - the third parasitic diode.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment are not described here, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. , adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Whereas a second element, component, region, layer or section is discussed, it does not indicate that the present disclosure necessarily presents a first element, component, region, layer or section.

Spatial terms such as "below...", "below...", "below", "below...", "on...", "above" and so on, can be used here for convenience are used in description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not to be taken as a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be provided in the following description, so as to explain the technical solution of the present disclosure. Preferred embodiments of the present disclosure are described in detail as follows, however, the present disclosure may have other embodiments besides these detailed descriptions.

As the manufacturing process of modern semiconductors becomes more and more advanced, the channel length becomes shorter and shorter, and the junction depth (Junction Depth) becomes shallower and shallower. The application of silicide (silicide) and lightly doped drain (Lightly Doped Drain, LDD) , the oxide layer is getting thinner and thinner, the ESD protection design window (window) is getting smaller and smaller, and the ESD protection design is facing more and more challenges. In order to protect the integrated circuit from being harmed by static electricity, it is usually necessary to carry out conventional electrostatic protection on the integrated circuit. The conventional circuit diagram is shown in Figure 1. The electrostatic protection devices used usually include diodes, MOS and silicon controlled rectifiers (Silicon Controlled Rectifier) , SCR) and so on. However, the conventional SCR has high trigger voltage, low sustain voltage, and is prone to latch-up, so it is not suitable for electrostatic protection of DRAM products, specifically, as shown in FIG. 2 . And, as shown in Figure 3, conventional SCRs have deviated from the design window for ESD. In order to apply SCR in the electrostatic protection of DRAM products, a new electrostatic protection method must be found.

The identification method of the latch structure provided by the present invention will be described in detail below through specific embodiments. It should be noted that, in FIGS. The input and output pads are referred to as IO, the ground pads are referred to as VSS, and the power pads are referred to as VDD.

An embodiment of the present disclosure provides an electrostatic protection device. FIG. 4 is a layout of the electrostatic protection device provided by the embodiment of the present disclosure, FIG. 5 is a schematic cross-sectional view of the electrostatic protection device provided by the embodiment of the present disclosure, and FIG. 6 is a schematic diagram of an equivalent circuit of the electrostatic protection device provided by the embodiment of the present disclosure.

Referring to Figures 4 to 6, the electrostatic protection device includes:

P-type substrate 21; N well 22, located in the P-type substrate 21; PMOS transistor, the PMOS transistor includes a gate 30 and a first P-type heavily doped region 11 located on both sides of the gate 30 and the second P-type heavily doped region 12; a pulse monitoring unit 40, the gate 30 of the PMOS transistor is controlled by the pulse monitoring unit 40; wherein, the first P-type heavily doped region 11 spans Connected between the P-type substrate 21 and the N well 22, the P-type substrate 21 is connected to the first pad, and the second P-type heavily doped region 12 is connected to the second pad .

In the embodiment of the present disclosure, by adding the pulse monitoring unit and the PMOS tube controlled by the pulse monitoring unit, when static electricity occurs, the PMOS tube controlled by the pulse monitoring unit will be turned on, thereby triggering the connection from the second pad to the first pad. An electrostatic current discharge path of a pad completes the discharge of electrostatic current. Moreover, the electrostatic protection device in the present disclosure has low trigger voltage and low leakage, which improves the electrostatic protection capability.

The electrostatic protection device provided by the embodiment of the present disclosure includes a P-type substrate 21 . The substrate can be a single semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon germanium (SiGe) substrate, etc.), or an insulator Silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, etc. The substrate in the embodiments of the present disclosure is a P-type substrate doped with P-type dopant ions.

The first P-type heavily doped region 11 is the source of the PMOS transistor, and the second P-type heavily doped region 12 is the drain of the PMOS transistor.

The gate 30 of the PMOS transistor includes an oxide layer 31 , a polysilicon layer 32 and a tungsten layer 33 stacked in sequence. A titanium nitride layer (not shown in the figure) is also included between the polysilicon layer 32 and the tungsten layer 33 .

In one embodiment, the electrostatic protection device further includes: a first N-type heavily doped region 13, a second N-type heavily doped region 15, a third N-type heavily doped region 16 and a third P-type heavily doped region impurity region 14; the first N-type heavily doped region 13, the third P-type heavily doped region 14 and the second N-type heavily doped region 15 are located in the P-type substrate 21; the The third N-type heavily doped region 16 and the second P-type heavily doped region 12 are located in the N well 22 .

It should be noted that the first N-type heavily doped region 13, the third P-type heavily doped region 14, the second N-type heavily doped region 15, the first P-type heavily doped The region 11, the second P-type heavily doped region 12 and the third N-type heavily doped region 16 are isolated by a shallow trench isolation structure (not shown in the figure).

In one embodiment, the third P-type heavily doped region 14 and the second N-type heavily doped region 15 are connected to the first pad.

The first N-type heavily doped region 13 is connected to the second pad.

The electrostatic protection device further includes: a third pad; the third N-type heavily doped region 16 is connected to the third pad.

In one embodiment, as shown in FIG. 6, the second P-type heavily doped region 12, the N well 22 and the P-type substrate 21 form a parasitic PNP transistor Q1; the N well 22, the The P-type substrate 21 and the second N-type heavily doped region 15 form a parasitic NPN transistor Q2.

As shown in Figure 6, the first N-type heavily doped region 13 and the third P-type heavily doped region 14 form a first parasitic diode 51; the third P-type heavily doped region 14 and the The third N-type heavily doped region 16 forms a second parasitic diode 52 ; the second P-type heavily doped region 12 and the third N-type heavily doped region 16 form a third parasitic diode 53 .

In one embodiment, the pulse monitoring unit 40 includes a resistor R and a capacitor C;

The gate 30 of the PMOS transistor is connected to the third pad through a resistor R, and connected to the first pad through a capacitor C.

The pulse monitoring unit 40 is an RC coupling loop, and the PMOS transistor is an RC trigger PMOS transistor.

In an embodiment of the present disclosure, the first pad is a ground pad; the second pad is an input/output pad; and the third pad is a power pad.

In one embodiment, the second P-type heavily doped region 12, the parasitic PNP transistor Q1, the parasitic NPN transistor Q2 and the second N-type heavily doped region 15 constitute A first electrostatic current discharge path from the pad to the first pad.

When a positive pulse is applied from the input and output pads to the ground pad and static electricity occurs, the PMOS transistor will be turned on first, thereby triggering the SCR static electricity discharge path composed of the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2, thereby completing the process from Electrostatic current discharge from the input and output pads to the ground pad. Specifically, the first electrostatic current discharge path is the path ① shown in FIG. 6 .

When working normally, the gate of the PMOS tube is connected to the power supply pad through the resistor R to a high potential, and the PMOS tube will be turned off, so it does not affect the normal function of the input circuit and ensures the normal operation of the circuit.

In one embodiment, the third P-type heavily doped region 14, the first parasitic diode 51, and the first N-type heavily doped region 13 form a connection from the first pad to the second pad. The second electrostatic current discharge path of the pad.

When a reverse pulse from the input-output pad to the ground pad is applied and static electricity occurs, the electrostatic current will be discharged along the first parasitic diode 51, thereby completing the discharge of static electricity from the ground pad to the input-output pad . Specifically, the second electrostatic current discharge path is the path ② shown in FIG. 6 .

In one embodiment, the second P-type heavily doped region 12, the third parasitic diode 53, and the third N-type heavily doped region 16 form a connection from the second pad to the third The third electrostatic current discharge path of the pad.

When applying a positive pulse from the input and output pads to the power supply pads and static electricity occurs, the static electricity will be discharged along the third parasitic diode 53, thereby completing the discharge of static electricity from the input and output pads to the power supply pads . Specifically, the third electrostatic current discharge path is the path ③ shown in FIG. 6 .

In one embodiment, the third P-type heavily doped region 14, the second parasitic diode 52, and the third N-type heavily doped region 16 form a connection from the first pad to the third The fourth electrostatic current discharge path of the pad.

When a pulse from the ground pad to the power pad is applied and static electricity occurs, the static electricity will be discharged along the second parasitic diode 52 , thereby completing the discharge of the static electricity from the ground pad to the power pad. Specifically, the fourth electrostatic current discharge path is the path ④ shown in FIG. 6 .

The SCR in the electrostatic protection device has a double trigger function, and the trigger voltage is low, which can meet the requirements of DRAM products. Moreover, the area of the layout design is small, and the window of the original ESD design is restored.

In an embodiment of the present disclosure, the electrostatic protection device is a PMOS triggered silicon controlled rectifier (PTSCR).

The electrostatic protection device provided by the embodiments of the present disclosure can be applied to the ESD protection of the input and output circuits of semiconductor integrated circuits and the ESD protection of various semiconductor integrated circuits, such as logic circuits, analog circuits and various memory chips, and can also be applied to ESD protection for low working voltage of advanced process.

The embodiment of the present disclosure also provides an electrostatic protection device. Referring to Figure 7, the electrostatic protection device includes:

P-type substrate 21'; N well 22', located in the P-type substrate 21'; NMOS transistor, the NMOS transistor includes a gate 30' and a first N-type gate located on both sides of the gate 30' The heavily doped region 11' and the second N-type heavily doped region 12'; the pulse monitoring unit 40', the gate 30' of the NMOS transistor is controlled by the pulse monitoring unit 40'; wherein, the The second N-type heavily doped region 12' spans between the P-type substrate 21' and the N well 22'; the P-type substrate 21' is connected to the first pad, and the first An N-type heavily doped region 11' is connected to the second pad.

The electrostatic protection device provided by the embodiment of the present disclosure includes a P-type substrate 21'. The substrate can be a single semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon germanium (SiGe) substrate, etc.), or an insulator Silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, etc. The substrate in the embodiments of the present disclosure is a P-type substrate doped with P-type dopant ions.

The first N-type heavily doped region 11' is the source of the NMOS transistor, and the second N-type heavily doped region 12' is the drain of the NMOS transistor.

The gate 30' of the NMOS transistor includes an oxide layer 31', a polysilicon layer 32' and a tungsten layer 33' stacked in sequence. A titanium nitride layer (not shown in the figure) is also included between the polysilicon layer 32' and the tungsten layer 33'.

In one embodiment, the electrostatic protection device further includes: a first P-type heavily doped region 13' and a third N-type heavily doped region 14'; the first P-type heavily doped region 13' and the third An N-type heavily doped region 11' is located in the P-type substrate 21'; the third N-type heavily doped region 14' is located in the N well 22'.

It should be noted that, between the first P-type heavily doped region 13', the first N-type heavily doped region 11', the second N-type heavily doped region 12' and the third N-type heavily doped region 14' Isolation is performed by shallow trench isolation structures (not shown in the figure).

The first P-type heavily doped region 13' is connected to the first pad.

In one embodiment, the electrostatic protection device further includes: a third pad; the third N-type heavily doped region 14' is connected to the third pad.

In an embodiment of the present disclosure, the first pad is a ground pad; the second pad is an input/output pad; and the third pad is a power pad.

In one embodiment, the pulse monitoring unit 40' includes a resistor R and a capacitor C;

The gate 30' of the NMOS transistor is connected to the first pad through a resistor R, and connected to the third pad through a capacitor C.

The pulse monitoring unit 40' is an RC coupling loop, and the NMOS transistor is an RC trigger NMOS transistor.

In one embodiment, the first P-type heavily doped region 13', the first N-type heavily doped region 11' and the P-type substrate 21' form a parasitic PNP transistor; the first N The N-type heavily doped region 11', the P-type substrate 21' and the second N-type heavily doped region 12' form a parasitic NPN transistor (not shown in the figure).

An embodiment of the present disclosure further provides an electronic device, the electronic device includes the electrostatic protection device described in any one of the above embodiments and an electronic component connected to the electrostatic protection device.

Since the electrostatic protection device described in any of the above embodiments has better electrostatic protection capability, the electronic device also has the above advantages.

The electronic device can be any electronic product or equipment such as mobile phone, tablet computer, notebook computer, TV set, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP, etc. Intermediate products of protection devices, such as mobile phone motherboards with the ESD protection device.

The above is only a preferred embodiment of the present disclosure, and is not used to limit the protection scope of the present disclosure. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure shall be included in the within the protection scope of the present disclosure.

Industrial Applicability

In the embodiment of the present disclosure, by adding the pulse monitoring unit and the PMOS tube controlled by the pulse monitoring unit, when static electricity occurs, the PMOS tube controlled by the pulse monitoring unit will be turned on, thereby triggering the connection from the second pad to the first The electrostatic current discharge path of the pad completes the discharge of electrostatic current. Moreover, the electrostatic protection device in the present disclosure has low trigger voltage and low leakage, which improves the electrostatic protection capability.

Claims (14)

1. An electrostatic protection device, comprising:

   P-type substrate;

   N well, located in the P-type substrate;

   A PMOS transistor, the PMOS transistor includes a gate and a first P-type heavily doped region and a second P-type heavily doped region located on both sides of the gate;

   A pulse monitoring unit, the gate of the PMOS transistor is controlled by the pulse monitoring unit; wherein,

   The first P-type heavily doped region spans between the P-type substrate and the N well, the P-type substrate is connected to the first pad, and the second P-type heavily doped region is connected to the second pad.
2. The electrostatic protection device according to claim 1, further comprising:

   a first N-type heavily doped region, a second N-type heavily doped region, a third N-type heavily doped region, and a third P-type heavily doped region;

   The first N-type heavily doped region, the third P-type heavily doped region and the second N-type heavily doped region are located in the P-type substrate;

   The third N-type heavily doped region and the second P-type heavily doped region are located in the N well.
3. The electrostatic protection device according to claim 2, wherein,

   The third P-type heavily doped region and the second N-type heavily doped region are connected to the first pad.
4. The electrostatic protection device according to claim 2, wherein,

   The first N-type heavily doped region is connected to the second pad.
5. The electrostatic protection device according to claim 2, further comprising:

   A third pad; the third heavily doped N-type region is connected to the third pad.
6. The electrostatic protection device according to claim 2, wherein,

   The second P-type heavily doped region, the N well and the P-type substrate form a parasitic PNP transistor;

   The N well, the P-type substrate and the second N-type heavily doped region form a parasitic NPN transistor.
7. The electrostatic protection device according to claim 5, wherein,

   The first N-type heavily doped region and the third P-type heavily doped region form a first parasitic diode;

   The third P-type heavily doped region and the third N-type heavily doped region form a second parasitic diode;

   The second P-type heavily doped region and the third N-type heavily doped region form a third parasitic diode.
8. The electrostatic protection device according to claim 5, wherein,

   The pulse monitoring unit includes a resistor R and a capacitor C;

   The gate of the PMOS transistor is connected to the third pad through a resistor R, and connected to the first pad through a capacitor C.
9. The electrostatic protection device according to claim 6, wherein,

   The second P-type heavily doped region, the parasitic PNP transistor, the parasitic NPN transistor, and the second N-type heavily doped region form a second pad from the second pad to the first pad. An electrostatic current discharge path.
10. The electrostatic protection device according to claim 7, wherein,

    The third P-type heavily doped region, the first parasitic diode, and the first N-type heavily doped region form a second electrostatic current discharge from the first pad to the second pad. path.
11. The electrostatic protection device according to claim 7, wherein,

    The second P-type heavily doped region, the third parasitic diode, and the third N-type heavily doped region form a third electrostatic current discharge from the second pad to the third pad path.
12. The electrostatic protection device according to claim 7, wherein,

    The third P-type heavily doped region, the second parasitic diode, and the third N-type heavily doped region form a fourth electrostatic current discharge from the first pad to the third pad. path.
13. The electrostatic protection device according to claim 5, wherein,

    The first pad is a ground pad; the second pad is an input/output pad; and the third pad is a power pad.
14. An electronic device, comprising the electrostatic protection device according to any one of claims 1 to 13 and electronic components connected to the electrostatic protection device.

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